| 1 |
2 |
robfinch |
`timescale 1ns / 1ps
|
| 2 |
|
|
// ============================================================================
|
| 3 |
|
|
// __
|
| 4 |
|
|
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
|
| 5 |
|
|
// \ __ / All rights reserved.
|
| 6 |
|
|
// \/_// robfinch@finitron.ca
|
| 7 |
|
|
// ||
|
| 8 |
|
|
//
|
| 9 |
|
|
// BSD 3-Clause License
|
| 10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
| 11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
| 12 |
|
|
//
|
| 13 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
| 14 |
|
|
// list of conditions and the following disclaimer.
|
| 15 |
|
|
//
|
| 16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
| 17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
| 18 |
|
|
// and/or other materials provided with the distribution.
|
| 19 |
|
|
//
|
| 20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
| 21 |
|
|
// contributors may be used to endorse or promote products derived from
|
| 22 |
|
|
// this software without specific prior written permission.
|
| 23 |
|
|
//
|
| 24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
| 25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
| 26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
| 27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
| 28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
| 29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
| 30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
| 31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
| 32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
| 33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 34 |
|
|
//
|
| 35 |
|
|
// ============================================================================
|
| 36 |
|
|
//
|
| 37 |
|
|
import mpmc8_pkg::*;
|
| 38 |
|
|
|
| 39 |
|
|
module mpmc8_strm_read_cache(rst, wclk, wr, wadr, wdat, inv,
|
| 40 |
|
|
rclk, radr, rdat, hit
|
| 41 |
|
|
);
|
| 42 |
|
|
input rst;
|
| 43 |
|
|
input wclk;
|
| 44 |
|
|
input wr;
|
| 45 |
|
|
input [31:0] wadr;
|
| 46 |
|
|
input [127:0] wdat;
|
| 47 |
|
|
input inv;
|
| 48 |
|
|
input rclk;
|
| 49 |
|
|
input [31:0] radr;
|
| 50 |
|
|
output reg [127:0] rdat;
|
| 51 |
|
|
output reg hit;
|
| 52 |
|
|
|
| 53 |
|
|
(* ram_style="distributed" *)
|
| 54 |
|
|
reg [127:0] lines [0:31];
|
| 55 |
|
|
(* ram_style="distributed" *)
|
| 56 |
|
|
reg [27:0] tags [0:31];
|
| 57 |
|
|
(* ram_style="distributed" *)
|
| 58 |
|
|
reg [31:0] vbit;
|
| 59 |
|
|
reg [31:0] radrr;
|
| 60 |
|
|
reg [27:0] tago;
|
| 61 |
|
|
reg vbito;
|
| 62 |
|
|
|
| 63 |
|
|
always_ff @(posedge rclk)
|
| 64 |
|
|
radrr <= radr;
|
| 65 |
|
|
always_ff @(posedge wclk)
|
| 66 |
|
|
if (wr) lines[wadr[8:4]] <= wdat;
|
| 67 |
|
|
always_ff @(posedge rclk)
|
| 68 |
|
|
rdat <= lines[radrr[8:4]];
|
| 69 |
|
|
always_ff @(posedge rclk)
|
| 70 |
|
|
tago <= tags[radrr[8:4]];
|
| 71 |
|
|
always_ff @(posedge rclk)
|
| 72 |
|
|
vbito <= vbit[radrr[8:4]];
|
| 73 |
|
|
always_ff @(posedge wclk)
|
| 74 |
|
|
if (wr) tags[wadr[8:4]] <= wadr[31:4];
|
| 75 |
|
|
always_ff @(posedge wclk)
|
| 76 |
|
|
if (rst)
|
| 77 |
|
|
vbit <= 'b0;
|
| 78 |
|
|
else begin
|
| 79 |
|
|
if (wr)
|
| 80 |
|
|
vbit[wadr[8:4]] <= 1'b1;
|
| 81 |
|
|
else if (inv)
|
| 82 |
|
|
vbit[wadr[8:4]] <= 1'b0;
|
| 83 |
|
|
end
|
| 84 |
|
|
always_comb
|
| 85 |
|
|
hit = (tago==radrr[31:4]) && (vbito==1'b1);
|
| 86 |
|
|
|
| 87 |
|
|
endmodule
|
