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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpcm10_cache_wb.sv] - Blame information for rev 7

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Line No. Rev Author Line
1 5 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
13
// 1. Redistributions of source code must retain the above copyright notice, this
14
//    list of conditions and the following disclaimer.
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//
16
// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
19
//
20
// 3. Neither the name of the copyright holder nor the names of its
21
//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
//
35
// ============================================================================
36
//
37
import const_pkg::*;
38
import wishbone_pkg::*;
39
import mpmc10_pkg::*;
40
 
41
module mpmc10_cache_wb (input rst, wclk, inv,
42
        input wb_write_request128_t wchi,
43
        output wb_write_response_t wcho,
44
        input wb_write_request128_t ld,
45
        input ch0clk,
46
        input ch1clk,
47
        input ch2clk,
48
        input ch3clk,
49
        input ch4clk,
50
        input ch5clk,
51
        input ch6clk,
52
        input ch7clk,
53
        input wb_write_request128_t ch0i,
54
        input wb_write_request128_t ch1i,
55
        input wb_write_request128_t ch2i,
56
        input wb_write_request128_t ch3i,
57
        input wb_write_request128_t ch4i,
58
        input wb_write_request128_t ch5i,
59
        input wb_write_request128_t ch6i,
60
        input wb_write_request128_t ch7i,
61
        input ch0wack,
62
        input ch1wack,
63
        input ch2wack,
64
        input ch3wack,
65
        input ch4wack,
66
        input ch5wack,
67
        input ch6wack,
68
        input ch7wack,
69
        output wb_read_response128_t ch0o,
70
        output wb_read_response128_t ch1o,
71
        output wb_read_response128_t ch2o,
72
        output wb_read_response128_t ch3o,
73
        output wb_read_response128_t ch4o,
74
        output wb_read_response128_t ch5o,
75
        output wb_read_response128_t ch6o,
76
        output wb_read_response128_t ch7o
77
);
78
parameter DEP=1024;
79
parameter LOBIT=4;
80
parameter HIBIT=13;
81
 
82
integer n,n2,n3,n4,n5;
83
 
84
(* ram_style="distributed" *)
85
reg [1023:0] vbit [0:CACHE_ASSOC-1];
86
initial begin
87
        for (n5 = 0; n5 < CACHE_ASSOC; n5 = n5 + 1)
88
                vbit[n5] <= 'd0;
89
end
90
 
91
reg [31:0] radrr [0:8];
92
reg wchi_stb, wchi_stb_r;
93
reg [15:0] wchi_sel, wchi_sel_r;
94 7 robfinch
reg [31:0] wchi_adr, wchi_adr1;
95 5 robfinch
reg [127:0] wchi_dat;
96
 
97
mpmc10_quad_cache_line_t doutb [0:8];
98
mpmc10_quad_cache_line_t wrdata, wdata;
99
 
100
reg [31:0] wadr;
101 7 robfinch
reg [127:0] lddat1, lddat2;
102
reg [31:0] wadr2;
103 5 robfinch
reg wstrb;
104
reg [$clog2(CACHE_ASSOC)-1:0] wway;
105
 
106
reg [CACHE_ASSOC-1:0] vbito0a;
107
reg [CACHE_ASSOC-1:0] vbito1a;
108
reg [CACHE_ASSOC-1:0] vbito2a;
109
reg [CACHE_ASSOC-1:0] vbito3a;
110
reg [CACHE_ASSOC-1:0] vbito4a;
111
reg [CACHE_ASSOC-1:0] vbito5a;
112
reg [CACHE_ASSOC-1:0] vbito6a;
113
reg [CACHE_ASSOC-1:0] vbito7a;
114
reg [CACHE_ASSOC-1:0] vbito8a;
115
 
116
reg [CACHE_ASSOC-1:0] hit0a;
117
reg [CACHE_ASSOC-1:0] hit1a;
118
reg [CACHE_ASSOC-1:0] hit2a;
119
reg [CACHE_ASSOC-1:0] hit3a;
120
reg [CACHE_ASSOC-1:0] hit4a;
121
reg [CACHE_ASSOC-1:0] hit5a;
122
reg [CACHE_ASSOC-1:0] hit6a;
123
reg [CACHE_ASSOC-1:0] hit7a;
124
reg [CACHE_ASSOC-1:0] hit8a;
125
 
126
reg stb0;
127
reg stb1;
128
reg stb2;
129
reg stb3;
130
reg stb4;
131
reg stb5;
132
reg stb6;
133
reg stb7;
134
reg [8:0] rstb;
135
 
136
always_ff @(posedge ch0clk) radrr[0] <= ch0i.adr;
137
always_ff @(posedge ch1clk) radrr[1] <= ch1i.adr;
138
always_ff @(posedge ch2clk) radrr[2] <= ch2i.adr;
139
always_ff @(posedge ch3clk) radrr[3] <= ch3i.adr;
140
always_ff @(posedge ch4clk) radrr[4] <= ch4i.adr;
141
always_ff @(posedge ch5clk) radrr[5] <= ch5i.adr;
142
always_ff @(posedge ch6clk) radrr[6] <= ch6i.adr;
143
always_ff @(posedge ch7clk) radrr[7] <= ch7i.adr;
144
always_ff @(posedge wclk) radrr[8] <= ld.cyc ? ld.adr : wchi.adr;
145 7 robfinch
always_ff @(posedge wclk) wchi_adr1 <= wchi.adr;
146
always_ff @(posedge wclk) wchi_adr <= wchi_adr1;
147 5 robfinch
 
148
always_ff @(posedge ch0clk) stb0 <= ch0i.stb;
149
always_ff @(posedge ch1clk) stb1 <= ch1i.stb;
150
always_ff @(posedge ch2clk) stb2 <= ch2i.stb;
151
always_ff @(posedge ch3clk) stb3 <= ch3i.stb;
152
always_ff @(posedge ch4clk) stb4 <= ch4i.stb;
153
always_ff @(posedge ch5clk) stb5 <= ch5i.stb;
154
always_ff @(posedge ch6clk) stb6 <= ch6i.stb;
155
always_ff @(posedge ch7clk) stb7 <= ch7i.stb;
156
 
157
always_comb rstb[0] <= ch0i.stb & ~ch0i.we;
158
always_comb rstb[1] <= ch1i.stb & ~ch1i.we;
159
always_comb rstb[2] <= ch2i.stb & ~ch2i.we;
160
always_comb rstb[3] <= ch3i.stb & ~ch3i.we;
161
always_comb rstb[4] <= ch4i.stb & ~ch4i.we;
162
always_comb rstb[5] <= ch5i.stb & ~ch5i.we;
163
always_comb rstb[6] <= ch6i.stb & ~ch6i.we;
164
always_comb rstb[7] <= ch7i.stb & ~ch7i.we;
165 7 robfinch
always_comb rstb[8] <= ld.cyc ? ld.stb : wchi.stb;
166 5 robfinch
 
167
always_ff @(posedge wclk) wchi_stb_r <= wchi.stb;
168
always_ff @(posedge wclk) wchi_stb <= wchi_stb_r;
169
always_ff @(posedge wclk) wchi_sel_r <= wchi.sel;
170
always_ff @(posedge wclk) wchi_sel <= wchi_sel_r;
171
always_ff @(posedge wclk) wchi_dat <= wchi.dat;
172
 
173
reg [8:0] rclkp;
174
always_comb
175
begin
176
        rclkp[0] = ch0clk;
177
        rclkp[1] = ch1clk;
178
        rclkp[2] = ch2clk;
179
        rclkp[3] = ch3clk;
180
        rclkp[4] = ch4clk;
181
        rclkp[5] = ch5clk;
182
        rclkp[6] = ch6clk;
183
        rclkp[7] = ch7clk;
184
        rclkp[8] = wclk;
185
end
186
 
187
reg [HIBIT-LOBIT:0] radr [0:8];
188
always_comb
189
begin
190
        radr[0] = ch0i.adr[HIBIT:LOBIT];
191
        radr[1] = ch1i.adr[HIBIT:LOBIT];
192
        radr[2] = ch2i.adr[HIBIT:LOBIT];
193
        radr[3] = ch3i.adr[HIBIT:LOBIT];
194
        radr[4] = ch4i.adr[HIBIT:LOBIT];
195
        radr[5] = ch5i.adr[HIBIT:LOBIT];
196
        radr[6] = ch6i.adr[HIBIT:LOBIT];
197
        radr[7] = ch7i.adr[HIBIT:LOBIT];
198
        radr[8] = ld.cyc ? ld.adr[HIBIT:LOBIT] : wchi.adr[HIBIT:LOBIT];
199
end
200
 
201
   // xpm_memory_sdpram: Simple Dual Port RAM
202
   // Xilinx Parameterized Macro, version 2020.2
203
 
204
genvar gway,gport;
205
 
206
generate begin : gCacheRAM
207
        for (gport = 0; gport < 9; gport = gport + 1) begin
208
        xpm_memory_sdpram #(
209
                .ADDR_WIDTH_A($clog2(DEP)),
210
                .ADDR_WIDTH_B($clog2(DEP)),
211
                .AUTO_SLEEP_TIME(0),
212
                .BYTE_WRITE_WIDTH_A($bits(mpmc10_quad_cache_line_t)),
213
                .CASCADE_HEIGHT(0),
214
                .CLOCKING_MODE("independent_clock"), // String
215
                .ECC_MODE("no_ecc"),            // String
216
                .MEMORY_INIT_FILE("none"),      // String
217
                .MEMORY_INIT_PARAM("0"),        // String
218
                .MEMORY_OPTIMIZATION("true"),   // String
219
                .MEMORY_PRIMITIVE("block"),      // String
220
                .MEMORY_SIZE($bits(mpmc10_quad_cache_line_t)*DEP),         // DECIMAL
221
                .MESSAGE_CONTROL(0),            // DECIMAL
222
                .READ_DATA_WIDTH_B($bits(mpmc10_quad_cache_line_t)),         // DECIMAL
223
                .READ_LATENCY_B(1),
224
                .READ_RESET_VALUE_B("0"),       // String
225
                .RST_MODE_A("SYNC"),            // String
226
                .RST_MODE_B("SYNC"),            // String
227
                .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
228
                .USE_EMBEDDED_CONSTRAINT(0),
229
                .USE_MEM_INIT(1),
230
                .WAKEUP_TIME("disable_sleep"),  // String
231
                .WRITE_DATA_WIDTH_A($bits(mpmc10_quad_cache_line_t)),        // DECIMAL
232
                .WRITE_MODE_B("no_change")      // String
233
        )
234
                xpm_memory_sdpram_inst1 (
235
                .dbiterrb(),             // 1-bit output: Status signal to indicate double bit error occurrence
236
                                                 // on the data output of port B.
237
 
238
                .doutb(doutb[gport]),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
239
                .sbiterrb(),             // 1-bit output: Status signal to indicate single bit error occurrence
240
                                                 // on the data output of port B.
241
 
242
                .addra(wadr2[HIBIT:LOBIT]),                                     // ADDR_WIDTH_A-bit input: Address for port A write operations.
243
                .addrb(radr[gport]),             // ADDR_WIDTH_B-bit input: Address for port B read operations.
244
                .clka(wclk),                 // 1-bit input: Clock signal for port A. Also clocks port B when
245
                                                 // parameter CLOCKING_MODE is "common_clock".
246
 
247
                .clkb(rclkp[gport]),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
248
                                                 // "independent_clock". Unused when parameter CLOCKING_MODE is
249
                                                 // "common_clock".
250
 
251
                .dina(wdata),                // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
252
                .ena(wstrb),                            // 1-bit input: Memory enable signal for port A. Must be high on clock
253
                                                 // cycles when write operations are initiated. Pipelined internally.
254
 
255
                .enb(rstb[gport]),                // 1-bit input: Memory enable signal for port B. Must be high on clock
256
                                                 // cycles when read operations are initiated. Pipelined internally.
257
 
258
                .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
259
                                                 // ECC enabled (Error injection capability is not available in
260
                                                 // "decode_only" mode).
261
 
262
                .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
263
                                                 // ECC enabled (Error injection capability is not available in
264
                                                 // "decode_only" mode).
265
 
266
                .regceb(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output
267
                                                 // data path.
268
 
269
                .rstb(rst),                     // 1-bit input: Reset signal for the final port B output register stage.
270
                                                 // Synchronously resets output port doutb to the value specified by
271
                                                 // parameter READ_RESET_VALUE_B.
272
 
273
                .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.
274
                .wea(wstrb)                     // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
275
                                                 // for port A input data port dina. 1 bit wide when word-wide writes are
276
                                                 // used. In byte-wide write configurations, each bit controls the
277
                                                 // writing one byte of dina to address addra. For example, to
278
                                                 // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
279
                                                 // is 32, wea would be 4'b0010.
280
 
281
        );
282
        end
283
end
284
endgenerate
285
 
286
genvar g;
287
generate begin : gReaddat
288
        for (g = 0; g < CACHE_ASSOC; g = g + 1) begin
289
                always_comb vbito0a[g] <= vbit[g][radrr[0][HIBIT:LOBIT]];
290
                always_comb vbito1a[g] <= vbit[g][radrr[1][HIBIT:LOBIT]];
291
                always_comb vbito2a[g] <= vbit[g][radrr[2][HIBIT:LOBIT]];
292
                always_comb vbito3a[g] <= vbit[g][radrr[3][HIBIT:LOBIT]];
293
                always_comb vbito4a[g] <= vbit[g][radrr[4][HIBIT:LOBIT]];
294
                always_comb vbito5a[g] <= vbit[g][radrr[5][HIBIT:LOBIT]];
295
                always_comb vbito6a[g] <= vbit[g][radrr[6][HIBIT:LOBIT]];
296
                always_comb vbito7a[g] <= vbit[g][radrr[7][HIBIT:LOBIT]];
297
                always_comb vbito8a[g] <= vbit[g][radrr[8][HIBIT:LOBIT]];
298
 
299
                always_ff @(posedge ch0clk)     hit0a[g] = (doutb[0].lines[g].tag==radrr[0][31:HIBIT+1]) && (vbito0a[g]==1'b1);
300
                always_ff @(posedge ch1clk)     hit1a[g] = (doutb[1].lines[g].tag==radrr[1][31:HIBIT+1]) && (vbito1a[g]==1'b1);
301
                always_ff @(posedge ch2clk)     hit2a[g] = (doutb[2].lines[g].tag==radrr[2][31:HIBIT+1]) && (vbito2a[g]==1'b1);
302
                always_ff @(posedge ch3clk)     hit3a[g] = (doutb[3].lines[g].tag==radrr[3][31:HIBIT+1]) && (vbito3a[g]==1'b1);
303
                always_ff @(posedge ch4clk)     hit4a[g] = (doutb[4].lines[g].tag==radrr[4][31:HIBIT+1]) && (vbito4a[g]==1'b1);
304
                always_ff @(posedge ch5clk)     hit5a[g] = (doutb[5].lines[g].tag==radrr[5][31:HIBIT+1]) && (vbito5a[g]==1'b1);
305
                always_ff @(posedge ch6clk)     hit6a[g] = (doutb[6].lines[g].tag==radrr[6][31:HIBIT+1]) && (vbito6a[g]==1'b1);
306
                always_ff @(posedge ch7clk)     hit7a[g] = (doutb[7].lines[g].tag==radrr[7][31:HIBIT+1]) && (vbito7a[g]==1'b1);
307
                always_ff @(posedge wclk)       hit8a[g] = (doutb[8].lines[g].tag==radrr[8][31:HIBIT+1]) && (vbito8a[g]==1'b1);
308
        end
309
        always_comb ch0o.ack = (|hit0a & stb0) | (ch0wack & stb0);
310
        always_comb ch1o.ack = (|hit1a & stb1) | (ch1wack & stb1);
311
        always_comb ch2o.ack = (|hit2a & stb2) | (ch2wack & stb2);
312
        always_comb ch3o.ack = (|hit3a & stb3) | (ch3wack & stb3);
313
        always_comb ch4o.ack = (|hit4a & stb4) | (ch4wack & stb4);
314
        always_comb ch5o.ack = (|hit5a & stb5) | (ch5wack & stb5);
315
        always_comb ch6o.ack = (|hit6a & stb6) | (ch6wack & stb6);
316
        always_comb ch7o.ack = (|hit7a & stb7) | (ch7wack & stb7);
317
        always_comb ch0o.err = 1'b0;
318
        always_comb ch1o.err = 1'b0;
319
        always_comb ch2o.err = 1'b0;
320
        always_comb ch3o.err = 1'b0;
321
        always_comb ch4o.err = 1'b0;
322
        always_comb ch5o.err = 1'b0;
323
        always_comb ch6o.err = 1'b0;
324
        always_comb ch7o.err = 1'b0;
325
        always_comb ch0o.rty = 1'b0;
326
        always_comb ch1o.rty = 1'b0;
327
        always_comb ch2o.rty = 1'b0;
328
        always_comb ch3o.rty = 1'b0;
329
        always_comb ch4o.rty = 1'b0;
330
        always_comb ch5o.rty = 1'b0;
331
        always_comb ch6o.rty = 1'b0;
332
        always_comb ch7o.rty = 1'b0;
333
        always_comb ch0o.cid = ch0i.cid;
334
        always_comb ch1o.cid = ch1i.cid;
335
        always_comb ch2o.cid = ch2i.cid;
336
        always_comb ch3o.cid = ch3i.cid;
337
        always_comb ch4o.cid = ch4i.cid;
338
        always_comb ch5o.cid = ch5i.cid;
339
        always_comb ch6o.cid = ch6i.cid;
340
        always_comb ch7o.cid = ch7i.cid;
341
end
342
endgenerate
343
 
344
always_comb wway = hit8a[0] ? 2'd0 : hit8a[1] ? 2'd1 : hit8a[2] ? 2'd2 : hit8a[3] ? 2'd3 : 2'd0;
345
 
346
always_comb
347
begin
348
        ch0o.dat <= 'd0;
349
        ch1o.dat <= 'd0;
350
        ch2o.dat <= 'd0;
351
        ch3o.dat <= 'd0;
352
        ch4o.dat <= 'd0;
353
        ch5o.dat <= 'd0;
354
        ch6o.dat <= 'd0;
355
        ch7o.dat <= 'd0;
356
        wrdata <= 'd0;
357
        for (n2 = 0; n2 < CACHE_ASSOC; n2 = n2 + 1) begin
358
                if (hit0a[n2]) ch0o.dat <= doutb[0].lines[n2];
359
                if (hit1a[n2]) ch1o.dat <= doutb[1].lines[n2];
360
                if (hit2a[n2]) ch2o.dat <= doutb[2].lines[n2];
361
                if (hit3a[n2]) ch3o.dat <= doutb[3].lines[n2];
362
                if (hit4a[n2]) ch4o.dat <= doutb[4].lines[n2];
363
                if (hit5a[n2]) ch5o.dat <= doutb[5].lines[n2];
364
                if (hit6a[n2]) ch6o.dat <= doutb[6].lines[n2];
365
                if (hit7a[n2]) ch7o.dat <= doutb[7].lines[n2];
366
        end
367
//      if (|hit8a)
368
                wrdata <= doutb[8];
369
end
370
 
371
reg b0,b1,b2;
372
reg ldcycd1,ldcycd2;
373
always_ff @(posedge wclk)
374
        ldcycd1 <= ld.cyc;
375
always_ff @(posedge wclk)
376
        ldcycd2 <= ldcycd1;
377
always_ff @(posedge wclk)
378
if (rst) begin
379
        for (n = 0; n < 4; n = n + 1)
380
                vbit[n] <= 'b0;
381
end
382
else begin
383
        if (ldcycd2) begin
384
                vbit[0][wadr2[HIBIT:LOBIT]] <= 1'b1;
385
                vbit[1][wadr2[HIBIT:LOBIT]] <= b0;
386
                vbit[2][wadr2[HIBIT:LOBIT]] <= b1;
387
                vbit[3][wadr2[HIBIT:LOBIT]] <= b2;
388
        end
389
        if (ldcycd1) begin
390
                b0 <= vbit[0][wadr[HIBIT:LOBIT]];
391
                b1 <= vbit[1][wadr[HIBIT:LOBIT]];
392
                b2 <= vbit[2][wadr[HIBIT:LOBIT]];
393
        end
394 7 robfinch
        if (|hit8a & |wchi_sel & wchi_stb & wchi.we & ~(ld.cyc|ldcycd1|ldcycd2))
395 5 robfinch
                vbit[wway][wadr[HIBIT:LOBIT]] <= 1'b1;
396
        else if (inv)
397
                vbit[wway][wadr[HIBIT:LOBIT]] <= 1'b0;
398
end
399
 
400
// Update the cache only if there was a write hit or if loading the cache line
401
// due to a read miss. For a read miss the entire line is updated, otherwise
402
// just the part of the line relevant to the write is updated.
403
always_ff @(posedge wclk)
404
begin
405
        if (ld.cyc)
406
                wadr <= ld.adr;
407
        else if (wchi_stb)
408
                wadr <= wchi_adr;
409 7 robfinch
        wstrb <= ldcycd2 | (wchi_stb & |hit8a & wchi.we);
410 5 robfinch
end
411
always_ff @(posedge wclk)
412
        wadr2 <= wadr;
413
always_ff @(posedge wclk)
414
        lddat1 <= ld.dat;
415
always_ff @(posedge wclk)
416
        lddat2 <= lddat1;
417
 
418
// Merge write data into cache line.
419
// For a load due to a read miss the entire line is updated.
420
// For a write hit, just the portion of the line corresponding to the hit is
421
// updated.
422
reg [18:0] t0,t1,t2;
423
reg m0,m1,m2;
424
generate begin : gWrData
425
        // LRU update
426
        always_ff @(posedge wclk)
427
        begin
428
                if (ldcycd2) begin
429
                        wdata.lines[0].tag <= {5'd0,wadr2[31:HIBIT+1]};                 // set tag
430
                        wdata.lines[1].tag <= t0;
431
                        wdata.lines[2].tag <= t1;
432
                        wdata.lines[3].tag <= t2;
433
                        wdata.lines[0].modified <= 1'b0;                                                                                        // clear modified flags
434
                        wdata.lines[1].modified <= m0;
435
                        wdata.lines[2].modified <= m1;
436
                        wdata.lines[3].modified <= m2;
437
                end
438
                if (ldcycd1) begin
439
                        t0 <= wrdata.lines[0].tag;
440
                        t1 <= wrdata.lines[1].tag;
441
                        t2 <= wrdata.lines[2].tag;
442
                        m0 <= wrdata.lines[0].modified;
443
                        m1 <= wrdata.lines[1].modified;
444
                        m2 <= wrdata.lines[2].modified;
445
                end
446
                if (!(ld.cyc|ldcycd1|ldcycd2)) begin
447 7 robfinch
                        if (wchi_stb & hit8a[0] & wchi.we)
448 5 robfinch
                                wdata.lines[0].modified <= 1'b1;
449
                        else
450
                                wdata.lines[0].modified <= wrdata.lines[0].modified;
451 7 robfinch
                        if (wchi_stb & hit8a[1] & wchi.we)
452 5 robfinch
                                wdata.lines[1].modified <= 1'b1;
453
                        else
454 7 robfinch
                                wdata.lines[1].modified <= wrdata.lines[1].modified;
455
                        if (wchi_stb & hit8a[2] & wchi.we)
456 5 robfinch
                                wdata.lines[2].modified <= 1'b1;
457
                        else
458 7 robfinch
                                wdata.lines[2].modified <= wrdata.lines[2].modified;
459
                        if (wchi_stb & hit8a[3] & wchi.we)
460 5 robfinch
                                wdata.lines[3].modified <= 1'b1;
461
                        else
462 7 robfinch
                                wdata.lines[3].modified <= wrdata.lines[3].modified;
463 5 robfinch
                        // Tag stays the same, it was hit
464
                        wdata.lines[0].tag <= wrdata.lines[0].tag;
465
                        wdata.lines[1].tag <= wrdata.lines[1].tag;
466
                        wdata.lines[2].tag <= wrdata.lines[2].tag;
467
                        wdata.lines[3].tag <= wrdata.lines[3].tag;
468
                end
469
        end
470
        for (g = 0; g < 16; g = g + 1)
471
        always_ff @(posedge wclk)
472
                begin
473
                        if (ldcycd2) begin
474
        //                      wdata <= wrdata << $bits(mpmc10_cache_line_t);
475
                                wdata.lines[0].data[g*8+7:g*8] <= lddat2[g*8+7:g*8];            // set data
476
                                wdata.lines[1].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
477
                                wdata.lines[2].data[g*8+7:g*8] <= wrdata.lines[1].data[g*8+7:g*8];
478
                                wdata.lines[3].data[g*8+7:g*8] <= wrdata.lines[2].data[g*8+7:g*8];
479
                        end
480
                        if (!(ld.cyc|ldcycd1|ldcycd2)) begin
481 7 robfinch
                                if (wchi_stb & hit8a[0] & wchi.we)
482 5 robfinch
                                        wdata.lines[0].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[0].data[g*8+7:g*8];
483
                                else
484
                                        wdata.lines[0].data[g*8+7:g*8] <= wrdata.lines[0].data[g*8+7:g*8];
485 7 robfinch
                                if (wchi_stb & hit8a[1] & wchi.we)
486 5 robfinch
                                        wdata.lines[1].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[1].data[g*8+7:g*8];
487
                                else
488 7 robfinch
                                        wdata.lines[1].data[g*8+7:g*8] <= wrdata.lines[1].data[g*8+7:g*8];
489
                                if (wchi_stb & hit8a[2] & wchi.we)
490 5 robfinch
                                        wdata.lines[2].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[2].data[g*8+7:g*8];
491
                                else
492 7 robfinch
                                        wdata.lines[2].data[g*8+7:g*8] <= wrdata.lines[2].data[g*8+7:g*8];
493
                                if (wchi_stb & hit8a[3] & wchi.we)
494 5 robfinch
                                        wdata.lines[3].data[g*8+7:g*8] <= wchi_sel[g] ? wchi_dat[g*8+7:g*8] : wrdata.lines[3].data[g*8+7:g*8];
495
                                else
496 7 robfinch
                                        wdata.lines[3].data[g*8+7:g*8] <= wrdata.lines[3].data[g*8+7:g*8];
497 5 robfinch
                        end
498
                end
499
end
500
endgenerate
501
 
502
// Writes take two clock cycles, 1 to read the RAM and find out if it is a
503
// write hit and a second clock to write the data. The write cycle may be
504
// delayed by a cycle due to a load.
505
reg wack;
506
always_ff @(posedge wclk)
507
if (rst)
508
        wack <= 1'b0;
509
else begin
510
        wack <= 1'b0;
511 7 robfinch
        if (wchi.stb & ~ld.stb & wchi.we)
512 5 robfinch
                wack <= 1'b1;
513
end
514
assign wcho.ack = wack & wchi.stb;
515
 
516
endmodule

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