OpenCores
URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

Subversion Repositories mpmc8

[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_addr_resv_man.sv] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch@finitron.ca
7
//       ||
8
//
9
// BSD 3-Clause License
10
// Redistribution and use in source and binary forms, with or without
11
// modification, are permitted provided that the following conditions are met:
12
//
13
// 1. Redistributions of source code must retain the above copyright notice, this
14
//    list of conditions and the following disclaimer.
15
//
16
// 2. Redistributions in binary form must reproduce the above copyright notice,
17
//    this list of conditions and the following disclaimer in the documentation
18
//    and/or other materials provided with the distribution.
19
//
20
// 3. Neither the name of the copyright holder nor the names of its
21
//    contributors may be used to endorse or promote products derived from
22
//    this software without specific prior written permission.
23
//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
//
35
// ============================================================================
36
//
37
import mpmc10_pkg::*;
38
 
39
module mpmc10_addr_resv_man(rst, clk, state,
40
        adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7,
41
        sr0, sr1, sr2, sr3, sr4, sr5, sr6, sr7,
42
        wch, we, wadr, cr, ch1_taghit,
43
        resv_ch, resv_adr, rack);
44
parameter NAR = 2;
45
input rst;
46
input clk;
47
input [3:0] state;
48
input [31:0] adr0;
49
input [31:0] adr1;
50
input [31:0] adr2;
51
input [31:0] adr3;
52
input [31:0] adr4;
53
input [31:0] adr5;
54
input [31:0] adr6;
55
input [31:0] adr7;
56
input sr0;
57
input sr1;
58
input sr2;
59
input sr3;
60
input sr4;
61
input sr5;
62
input sr6;
63
input sr7;
64
input [3:0] wch;
65
input cr;
66
input we;
67
input [31:0] wadr;
68
input ch1_taghit;
69
output reg [3:0] resv_ch [0:NAR-1];
70
output reg [31:0] resv_adr [0:NAR-1];
71
output reg [7:0] rack;  // reservation acknowledged
72
 
73
reg [19:0] resv_to_cnt;
74
wire [2:0] enc;
75
wire [7:0] srr = {sr7,sr6,sr5,sr4,sr3,sr2,sr1,sr0};
76
wire [31:0] adr [0:7];
77
 
78
assign adr[0] = adr0;
79
assign adr[1] = adr1;
80
assign adr[2] = adr2;
81
assign adr[3] = adr3;
82
assign adr[4] = adr4;
83
assign adr[5] = adr5;
84
assign adr[6] = adr6;
85
assign adr[7] = adr7;
86
 
87
roundRobin urr1
88
(
89
        .rst(rst),
90
        .clk(clk),
91
        .ce(1'b1),
92
        .req(srr),
93
        .lock(8'h00),
94
        .sel(),
95
        .sel_enc(enc)
96
);
97
 
98
// For address reservation below
99
reg [7:0] match;
100
always @(posedge clk)
101
if (rst)
102
        match <= 8'h00;
103
else begin
104
        if (match >= NAR)
105
                match <= 8'h00;
106
        else
107
                match <= match + 8'd1;
108
end
109
 
110
always_comb
111
        rack = ~srr | srr[enc];
112
 
113
// Managing address reservations
114
integer n7;
115
always_ff @(posedge clk)
116
if (rst) begin
117
        resv_to_cnt <= 20'd0;
118
        for (n7 = 0; n7 < NAR; n7 = n7 + 1)
119
                resv_ch[n7] <= 4'hF;
120
end
121
else begin
122
        resv_to_cnt <= resv_to_cnt + 20'd1;
123
 
124
        for (n7 = 0; n7 < 8; n7 = n7 + 1)
125
                if (enc==n7 && |srr)
126
                        reserve_adr({1'b0,n7[2:0]},adr[n7]);
127
 
128
        if (state==mpmc10_pkg::IDLE) begin
129
                if (we) begin
130
            if (cr) begin
131
                for (n7 = 0; n7 < NAR; n7 = n7 + 1)
132
                if ((resv_ch[n7]==wch) && (resv_adr[n7][31:4]==wadr[31:4]))
133
            resv_ch[n7] <= 4'hF;
134
            end
135
                end
136
        end
137
end
138
 
139
integer empty_resv;
140
function resv_held;
141
input [3:0] ch;
142
input [31:0] adr;
143
integer n8;
144
begin
145
        resv_held = mpmc10_pkg::FALSE;
146
        for (n8 = 0; n8 < NAR; n8 = n8 + 1)
147
                if (resv_ch[n8]==ch && resv_adr[n8][31:5]==adr[31:5])
148
                        resv_held = mpmc10_pkg::TRUE;
149
end
150
endfunction
151
 
152
// Find an empty reservation bucket
153
integer n9;
154
always_comb
155
begin
156
        empty_resv <= -1;
157
        for (n9 = 0; n9 < NAR; n9 = n9 + 1)
158
                if (resv_ch[n9]==4'hF)
159
                        empty_resv <= n9;
160
end
161
 
162
// Two reservation buckets are allowed for. There are two (or more) CPU's in the
163
// system and as long as they are not trying to control the same resource (the
164
// same semaphore) then they should be able to set a reservation. Ideally there
165
// could be more reservation buckets available, but it starts to be a lot of
166
// hardware.
167
task reserve_adr;
168
input [3:0] ch;
169
input [31:0] adr;
170
begin
171
        // Ignore an attempt to reserve an address that's already reserved. The LWAR
172
        // instruction is usually called in a loop and we don't want it to use up
173
        // all address reservations.
174
        if (!resv_held(ch,adr)) begin
175
                if (empty_resv >= 0) begin
176
                        resv_ch[empty_resv] <= ch;
177
                        resv_adr[empty_resv] <= adr;
178
                end
179
                // Here there were no free reservation buckets, so toss one of the
180
                // old reservations out.
181
                else begin
182
                        resv_ch[match] <= ch;
183
                        resv_adr[match] <= adr;
184
                end
185
        end
186
end
187
endtask
188
 
189
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.