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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_fifo.sv] - Blame information for rev 5

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1 5 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc10_pkg::*;
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module mpmc10_fifo(rst, clk, rd_fifo, wr_fifo, req_fifoi, req_fifoo, v,
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        full, empty, almost_full, rd_rst_busy, wr_rst_busy, cnt);
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input rst;
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input clk;
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input rd_fifo;
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input wr_fifo;
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input wb_write_request128_t req_fifoi;
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output wb_write_request128_t req_fifoo;
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output v;
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output full;
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output empty;
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output almost_full;
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output rd_rst_busy;
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output wr_rst_busy;
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output [4:0] cnt;
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xpm_fifo_sync #(
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  .DOUT_RESET_VALUE("0"),    // String
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  .ECC_MODE("no_ecc"),       // String
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  .FIFO_MEMORY_TYPE("distributed"), // String
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  .FIFO_READ_LATENCY(1),     // DECIMAL
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  .FIFO_WRITE_DEPTH(32),   // DECIMAL
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  .FULL_RESET_VALUE(0),      // DECIMAL
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  .PROG_EMPTY_THRESH(3),    // DECIMAL
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  .PROG_FULL_THRESH(27),     // DECIMAL
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  .RD_DATA_COUNT_WIDTH(5),   // DECIMAL
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  .READ_DATA_WIDTH($bits(wb_write_request128_t)),      // DECIMAL
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  .READ_MODE("std"),         // String
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  .SIM_ASSERT_CHK(0),        // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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  .USE_ADV_FEATURES("070F"), // String
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  .WAKEUP_TIME(0),           // DECIMAL
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  .WRITE_DATA_WIDTH($bits(wb_write_request128_t)),     // DECIMAL
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  .WR_DATA_COUNT_WIDTH(5)    // DECIMAL
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)
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xpm_fifo_sync_inst (
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  .almost_empty(),   // 1-bit output: Almost Empty : When asserted, this signal indicates that
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                                 // only one more read can be performed before the FIFO goes to empty.
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  .almost_full(almost_full),     // 1-bit output: Almost Full: When asserted, this signal indicates that
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                                 // only one more write can be performed before the FIFO is full.
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  .data_valid(v),       // 1-bit output: Read Data Valid: When asserted, this signal indicates
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                                 // that valid data is available on the output bus (dout).
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  .dbiterr(),             // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected
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                                 // a double-bit error and data in the FIFO core is corrupted.
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  .dout(req_fifoo),                   // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven
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                                 // when reading the FIFO.
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  .empty(empty),                 // 1-bit output: Empty Flag: When asserted, this signal indicates that the
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                                 // FIFO is empty. Read requests are ignored when the FIFO is empty,
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                                 // initiating a read while empty is not destructive to the FIFO.
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  .full(full),                   // 1-bit output: Full Flag: When asserted, this signal indicates that the
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                                 // FIFO is full. Write requests are ignored when the FIFO is full,
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                                 // initiating a write when the FIFO is full is not destructive to the
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                                 // contents of the FIFO.
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  .overflow(),           // 1-bit output: Overflow: This signal indicates that a write request
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                                 // (wren) during the prior clock cycle was rejected, because the FIFO is
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                                 // full. Overflowing the FIFO is not destructive to the contents of the
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                                 // FIFO.
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  .prog_empty(),       // 1-bit output: Programmable Empty: This signal is asserted when the
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                                 // number of words in the FIFO is less than or equal to the programmable
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                                 // empty threshold value. It is de-asserted when the number of words in
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                                 // the FIFO exceeds the programmable empty threshold value.
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  .prog_full(),         // 1-bit output: Programmable Full: This signal is asserted when the
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                                 // number of words in the FIFO is greater than or equal to the
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                                 // programmable full threshold value. It is de-asserted when the number of
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                                 // words in the FIFO is less than the programmable full threshold value.
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  .rd_data_count(), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the
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                                 // number of words read from the FIFO.
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  .rd_rst_busy(rd_rst_busy),     // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read
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                                 // domain is currently in a reset state.
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  .sbiterr(),             // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected
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                                 // and fixed a single-bit error.
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  .underflow(),         // 1-bit output: Underflow: Indicates that the read request (rd_en) during
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                                 // the previous clock cycle was rejected because the FIFO is empty. Under
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                                 // flowing the FIFO is not destructive to the FIFO.
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  .wr_ack(),               // 1-bit output: Write Acknowledge: This signal indicates that a write
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                                 // request (wr_en) during the prior clock cycle is succeeded.
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  .wr_data_count(cnt),                                  // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates
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                                 // the number of words written into the FIFO.
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  .wr_rst_busy(wr_rst_busy),                                            // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO
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                                 // write domain is currently in a reset state.
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  .din(req_fifoi),           // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when
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                                 // writing the FIFO.
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  .injectdbiterr(1'b0), // 1-bit input: Double Bit Error Injection: Injects a double bit error if
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                                 // the ECC feature is used on block RAMs or UltraRAM macros.
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  .injectsbiterr(1'b0), // 1-bit input: Single Bit Error Injection: Injects a single bit error if
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                                 // the ECC feature is used on block RAMs or UltraRAM macros.
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  .rd_en(rd_fifo & ~rd_rst_busy), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this
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                                 // signal causes data (on dout) to be read from the FIFO. Must be held
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                                 // active-low when rd_rst_busy is active high.
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  .rst(rst),                     // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be
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                                 // unstable at the time of applying reset, but reset must be released only
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                                 // after the clock(s) is/are stable.
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  .sleep(1'b0),                  // 1-bit input: Dynamic power saving- If sleep is High, the memory/fifo
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                                 // block is in power saving mode.
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  .wr_clk(clk),                                          // 1-bit input: Write clock: Used for write operation. wr_clk must be a
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                                 // free running clock.
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  .wr_en(wr_fifo & ~wr_rst_busy) // 1-bit input: Write Enable: If the FIFO is not full, asserting this
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                                 // signal causes data (on din) to be written to the FIFO Must be held
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                                 // active-low when rst or wr_rst_busy or rd_rst_busy is active high
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);
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endmodule

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