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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_state_machine.sv] - Blame information for rev 7

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1 5 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc10_pkg::*;
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module mpmc10_state_machine(rst, clk, to, rdy, wdf_rdy, fifo_empty, rd_fifo, fifo_out, state,
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        num_strips, req_strip_cnt, resp_strip_cnt, rd_data_valid, wway);
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input rst;
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input clk;
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input to;                                                       // state machine time-out
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input rdy;
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input wdf_rdy;
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input fifo_empty;
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output reg rd_fifo;
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input axi_request_readwrite256_t fifo_out;
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output reg [3:0] state;
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input [5:0] num_strips;
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input [5:0] req_strip_cnt;
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input [5:0] resp_strip_cnt;
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input rd_data_valid;
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output reg [1:0] wway;
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reg [3:0] next_state;
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reg next_rd_fifo;
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always_ff @(posedge clk)
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        state <= next_state;
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always_ff @(posedge clk)
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        rd_fifo <= next_rd_fifo;
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always_ff @(posedge clk)
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if (rst)
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        wway <= 2'd0;
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else begin
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        if (state==PRESET1)
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                wway <= wway + 2'd1;
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end
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always_comb
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if (rst) begin
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        next_state <= IDLE;
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        next_rd_fifo <= 1'b0;
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end
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else begin
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        next_rd_fifo <= 1'b0;
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        case(state)
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        IDLE:
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                begin
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                        if (!fifo_empty) begin
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                                next_rd_fifo <= 1'b1;
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                                next_state <= PRESET1;
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                        end
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                end
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        PRESET1:
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                next_state <= PRESET2;
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        PRESET2:
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                next_state <= PRESET3;
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        PRESET3:
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                if (fifo_out.write.WVALID)
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                        next_state <= WRITE_DATA0;
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                else
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                        next_state <= READ_DATA0;
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        // Write data to the data fifo
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        // Write occurs when app_wdf_wren is true and app_wdf_rdy is true
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        WRITE_DATA0:
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                // Issue a write command if the fifo is full.
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        //      if (!app_wdf_rdy)
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        //              next_state <= WRITE_DATA1;
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        //      else
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                if (wdf_rdy)// && req_strip_cnt==num_strips)
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                        next_state <= WRITE_DATA1;
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                else
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                        next_state <= WRITE_DATA0;
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        WRITE_DATA1:
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                next_state <= WRITE_DATA2;
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        WRITE_DATA2:
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                if (rdy)
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                        next_state <= WRITE_DATA3;
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                else
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                        next_state <= WRITE_DATA2;
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        WRITE_DATA3:
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                next_state <= IDLE;
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        // There could be multiple read requests submitted before any response occurs.
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        // Stay in the SET_CMD_RD until all requested strips have been processed.
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        READ_DATA0:
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                next_state <= READ_DATA1;
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        // Could it take so long to do the request that we start getting responses
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        // back?
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        READ_DATA1:
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                if (rdy && req_strip_cnt==num_strips)
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                        next_state <= READ_DATA2;
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                else
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                        next_state <= READ_DATA1;
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        // Wait for incoming responses, but only for so long to prevent a hang.
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        READ_DATA2:
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                if (rd_data_valid && resp_strip_cnt==num_strips)
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                        next_state <= WAIT_NACK;
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                else
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                        next_state <= READ_DATA2;
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        WAIT_NACK:
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                // If we're not seeing a nack and there is a channel selected, then the
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                // cache tag must not have updated correctly.
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                // For writes, assume a nack by now.
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                next_state <= IDLE;
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        default:        next_state <= IDLE;
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        endcase
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        // Is the state machine hung?
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        if (to)
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                next_state <= IDLE;
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end
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endmodule

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