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[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_wb.sv] - Blame information for rev 5

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Line No. Rev Author Line
1 5 robfinch
`timescale 1ns / 1ps
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// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
6
//     \/_//     robfinch@finitron.ca
7
//       ||
8
//
9
// BSD 3-Clause License
10
// Redistribution and use in source and binary forms, with or without
11
// modification, are permitted provided that the following conditions are met:
12
//
13
// 1. Redistributions of source code must retain the above copyright notice, this
14
//    list of conditions and the following disclaimer.
15
//
16
// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
19
//
20
// 3. Neither the name of the copyright holder nor the names of its
21
//    contributors may be used to endorse or promote products derived from
22
//    this software without specific prior written permission.
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//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
//
35
// 16000 LUTs, 130 BRAM (64kB cache)
36
//
37
// Read channels always wait until there is valid data in the cache.
38
// ============================================================================
39
//
40
//`define RED_SCREEN    1'b1
41
 
42
import wishbone_pkg::*;
43
import mpmc10_pkg::*;
44
 
45
module mpmc10_wb(
46
input rst,
47
input clk100MHz,
48
input mem_ui_rst,
49
input mem_ui_clk,
50
output reg rstn,
51
output [31:0] app_waddr,
52
input app_rdy,
53
output app_en,
54
output [2:0] app_cmd,
55
output [28:0] app_addr,
56
input app_rd_data_valid,
57
output [15:0] app_wdf_mask,
58
output reg [127:0] app_wdf_data,
59
input app_wdf_rdy,
60
output app_wdf_wren,
61
output app_wdf_end,
62
input [127:0] app_rd_data,
63
input app_rd_data_end,
64
input ch0clk, ch1clk, ch2clk, ch3clk, ch4clk, ch5clk, ch6clk, ch7clk,
65
input wb_write_request128_t ch0i,
66
output wb_read_response128_t ch0o,
67
input wb_write_request128_t ch1i,
68
output wb_read_response128_t ch1o,
69
input wb_write_request128_t ch2i,
70
output wb_read_response128_t ch2o,
71
input wb_write_request128_t ch3i,
72
output wb_read_response128_t ch3o,
73
input wb_write_request128_t ch4i,
74
output wb_read_response128_t ch4o,
75
input wb_write_request128_t ch5i,
76
output wb_read_response128_t ch5o,
77
input wb_write_request128_t ch6i,
78
output wb_read_response128_t ch6o,
79
input wb_write_request128_t ch7i,
80
output wb_read_response128_t ch7o,
81
output [3:0] state
82
);
83
parameter NAR = 2;                      // Number of address reservations
84
parameter CL = 3'd4;            // Cache read latency
85
parameter STREAM0 = TRUE;
86
parameter STREAM1 = FALSE;
87
parameter STREAM2 = FALSE;
88
parameter STREAM3 = FALSE;
89
parameter STREAM4 = FALSE;
90
parameter STREAM5 = TRUE;
91
parameter STREAM6 = FALSE;
92
parameter STREAM7 = FALSE;
93
 
94
wb_write_request128_t ch0is;
95
wb_write_request128_t ch0is2;
96
wb_write_request128_t ch1is;
97
wb_write_request128_t ch1is2;
98
wb_write_request128_t ch2is;
99
wb_write_request128_t ch2is2;
100
wb_write_request128_t ch3is;
101
wb_write_request128_t ch3is2;
102
wb_write_request128_t ch4is;
103
wb_write_request128_t ch4is2;
104
wb_write_request128_t ch5is;
105
wb_write_request128_t ch5is2;
106
wb_write_request128_t ch6is;
107
wb_write_request128_t ch6is2;
108
wb_write_request128_t ch7is;
109
wb_write_request128_t ch7is2;
110
 
111
wb_read_response128_t ch0oa, ch0ob;
112
wb_read_response128_t ch1oa, ch1ob;
113
wb_read_response128_t ch2oa, ch2ob;
114
wb_read_response128_t ch3oa, ch3ob;
115
wb_read_response128_t ch4oa, ch4ob;
116
wb_read_response128_t ch5oa, ch5ob;
117
wb_read_response128_t ch6oa, ch6ob;
118
wb_read_response128_t ch7oa, ch7ob;
119
 
120
assign ch0o = STREAM0 ? ch0ob : ch0oa;
121
assign ch1o = STREAM1 ? ch1ob : ch1oa;
122
assign ch2o = STREAM2 ? ch2ob : ch2oa;
123
assign ch3o = STREAM3 ? ch3ob : ch3oa;
124
assign ch4o = STREAM4 ? ch4ob : ch4oa;
125
assign ch5o = STREAM5 ? ch5ob : ch5oa;
126
assign ch6o = STREAM6 ? ch6ob : ch6oa;
127
assign ch7o = STREAM7 ? ch7ob : ch7oa;
128
 
129
wb_write_request128_t req_fifoi;
130
wb_write_request128_t req_fifoo;
131
wb_write_request128_t ld;
132
 
133
genvar g;
134
integer n1,n2;
135
wire almost_full;
136
wire [4:0] cnt;
137
reg wr_fifo;
138
wire [3:0] prev_state;
139
wire [3:0] state;
140
wire rd_fifo;   // from state machine
141
reg [5:0] num_strips;   // from fifo
142
wire [5:0] req_strip_cnt;
143
wire [5:0] resp_strip_cnt;
144
wire [15:0] tocnt;
145
wire [31:0] app_waddr;
146
reg [31:0] adr;
147
reg [3:0] uch;          // update channel
148
wire [15:0] wmask;
149
wire [15:0] mem_wdf_mask2;
150
reg [127:0] dat128;
151
wire [255:0] dat256;
152
wire [3:0] resv_ch [0:NAR-1];
153
wire [31:0] resv_adr [0:NAR-1];
154
wire rb1;
155
reg [7:0] req;
156
wire [1:0] wway;
157
reg [127:0] rd_data_r;
158
reg rd_data_valid_r;
159
 
160
wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
161
wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
162
wire ch0_hit_ne, ch5_hit_ne;
163
 
164
always_ff @(posedge mem_ui_clk)
165
        rd_data_r <= app_rd_data;
166
always_ff @(posedge mem_ui_clk)
167
        rd_data_valid_r <= app_rd_data_valid;
168
 
169
reg [19:0] rst_ctr;
170
always @(posedge clk100MHz)
171
if (rst)
172
        rst_ctr <= 24'd0;
173
else begin
174
        if (!rst_ctr[15])
175
                rst_ctr <= rst_ctr + 2'd1;
176
        rstn <= rst_ctr[15];
177
end
178
 
179
reg [7:0] stb [0:7];
180
always_comb stb[0] = ch0is.stb;
181
always_comb stb[1] = ch1is.stb;
182
always_comb stb[2] = ch2is.stb;
183
always_comb stb[3] = ch3is.stb;
184
always_comb stb[4] = ch4is.stb;
185
always_comb stb[5] = ch5is.stb;
186
always_comb stb[6] = ch6is.stb;
187
always_comb stb[7] = ch7is.stb;
188
 
189
reg [2:0] chcnt [0:7];
190
always_ff @(posedge mem_ui_clk)
191
if (rst) begin
192
        for (n2 = 0; n2 < 8; n2 = n2 + 1)
193
                chcnt[n2] <= 'd0;
194
end
195
else begin
196
        for (n2 = 0; n2 < 8; n2 = n2 + 1)
197
                if (stb[n2]) begin
198
                        if (chcnt[n2] < CL)
199
                                chcnt[n2] <= chcnt[n2] + 2'd1;
200
                end
201
                else
202
                        chcnt[n2] <= 'd0;
203
end
204
 
205
reg [7:0] pe_req;
206
reg [7:0] chack;
207
always_comb chack[0] = ch0o.ack;
208
always_comb chack[1] = ch1o.ack;
209
always_comb chack[2] = ch2o.ack;
210
always_comb chack[3] = ch3o.ack;
211
always_comb chack[4] = ch4o.ack;
212
always_comb chack[5] = ch5o.ack;
213
always_comb chack[6] = ch6o.ack;
214
always_comb chack[7] = ch7o.ack;
215
 
216
edge_det edch0 (
217
        .rst(mem_ui_rst),
218
        .clk(mem_ui_clk),
219
        .ce(1'b1),
220
        .i((!ch0o.ack && ch0is.stb && !ch0is.we && chcnt[0]==CL) || (ch0is.we && ch0is.stb)),
221
        .pe(pe_req[0]),
222
        .ne(),
223
        .ee()
224
);
225
edge_det edch1 (
226
        .rst(mem_ui_rst),
227
        .clk(mem_ui_clk),
228
        .ce(1'b1),
229
        .i((!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb)),
230
        .pe(pe_req[1]),
231
        .ne(),
232
        .ee()
233
);
234
edge_det edch2 (
235
        .rst(mem_ui_rst),
236
        .clk(mem_ui_clk),
237
        .ce(1'b1),
238
        .i((!ch2o.ack && ch2is.stb && !ch2is.we && chcnt[2]==CL) || (ch2is.we && ch2is.stb)),
239
        .pe(pe_req[2]),
240
        .ne(),
241
        .ee()
242
);
243
edge_det edch3 (
244
        .rst(mem_ui_rst),
245
        .clk(mem_ui_clk),
246
        .ce(1'b1),
247
        .i((!ch3o.ack && ch3is.stb && !ch3is.we && chcnt[3]==CL) || (ch3is.we && ch3is.stb)),
248
        .pe(pe_req[3]),
249
        .ne(),
250
        .ee()
251
);
252
edge_det edch4 (
253
        .rst(mem_ui_rst),
254
        .clk(mem_ui_clk),
255
        .ce(1'b1),
256
        .i((!ch4o.ack && ch4is.stb && !ch4is.we && chcnt[4]==CL) || (ch4is.we && ch4is.stb)),
257
        .pe(pe_req[4]),
258
        .ne(),
259
        .ee()
260
);
261
edge_det edch5 (
262
        .rst(mem_ui_rst),
263
        .clk(mem_ui_clk),
264
        .ce(1'b1),
265
        .i((!ch5_hit_s && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb)),
266
        .pe(pe_req[5]),
267
        .ne(),
268
        .ee()
269
);
270
edge_det edch6 (
271
        .rst(mem_ui_rst),
272
        .clk(mem_ui_clk),
273
        .ce(1'b1),
274
        .i((!ch6o.ack && ch6is.stb && !ch6is.we && chcnt[6]==CL) || (ch6is.we && ch6is.stb)),
275
        .pe(pe_req[6]),
276
        .ne(),
277
        .ee()
278
);
279
edge_det edch7 (
280
        .rst(mem_ui_rst),
281
        .clk(mem_ui_clk),
282
        .ce(1'b1),
283
        .i((!ch7o.ack && ch7is.stb && !ch7is.we && chcnt[7]==CL) || (ch7is.we && ch7is.stb)),
284
        .pe(pe_req[7]),
285
        .ne(),
286
        .ee()
287
);
288
wire [3:0] req_sel;
289
generate begin : gReq
290
        for (g = 0; g < 8; g = g + 1)
291
                always_ff @(posedge mem_ui_clk)
292
                        if (pe_req[g])
293
                                req[g] <= 1'b1;
294
                        else if (req_sel==g[3:0] || chack[g])
295
                                req[g] <= 1'b0;
296
end
297
endgenerate
298
 
299
// Register signals onto mem_ui_clk domain
300
mpmc10_sync128_wb usyn0
301
(
302
        .clk(mem_ui_clk),
303
        .i(ch0i),
304
        .o(ch0is)
305
);
306
mpmc10_sync128_wb usyn1
307
(
308
        .clk(mem_ui_clk),
309
        .i(ch1i),
310
        .o(ch1is)
311
);
312
mpmc10_sync128_wb usyn2
313
(
314
        .clk(mem_ui_clk),
315
        .i(ch2i),
316
        .o(ch2is)
317
);
318
mpmc10_sync128_wb usyn3
319
(
320
        .clk(mem_ui_clk),
321
        .i(ch3i),
322
        .o(ch3is)
323
);
324
mpmc10_sync128_wb usyn4
325
(
326
        .clk(mem_ui_clk),
327
        .i(ch4i),
328
        .o(ch4is)
329
);
330
mpmc10_sync128_wb usyn5
331
(
332
        .clk(mem_ui_clk),
333
        .i(ch5i),
334
        .o(ch5is)
335
);
336
mpmc10_sync128_wb usyn6
337
(
338
        .clk(mem_ui_clk),
339
        .i(ch6i),
340
        .o(ch6is)
341
);
342
mpmc10_sync128_wb usyn7
343
(
344
        .clk(mem_ui_clk),
345
        .i(ch7i),
346
        .o(ch7is)
347
);
348
 
349
// Streaming channels have a burst length of 64. Round the address to the burst
350
// length.
351
always_comb
352
begin
353
        ch0is2 <= ch0is;
354
        ch0is2.adr <= {ch0is.adr[31:10],10'b0};
355
end
356
always_comb
357
begin
358
        ch1is2 <= ch1is;
359
        ch1is2.adr <= {ch1is.adr[31:10],10'b0};
360
end
361
always_comb
362
begin
363
        ch2is2 <= ch2is;
364
        ch2is2.adr <= {ch2is.adr[31:10],10'b0};
365
end
366
always_comb
367
begin
368
        ch3is2 <= ch3is;
369
        ch3is2.adr <= {ch3is.adr[31:10],10'b0};
370
end
371
always_comb
372
begin
373
        ch4is2 <= ch4is;
374
        ch4is2.adr <= {ch4is.adr[31:10],10'b0};
375
end
376
always_comb
377
begin
378
        ch5is2 <= ch5is;
379
        ch5is2.adr <= {ch5is.adr[31:10],10'b0};
380
end
381
always_comb
382
begin
383
        ch6is2 <= ch6is;
384
        ch6is2.adr <= {ch6is.adr[31:10],10'b0};
385
end
386
always_comb
387
begin
388
        ch7is2 <= ch7is;
389
        ch7is2.adr <= {ch7is.adr[31:10],10'b0};
390
end
391
 
392
always_comb
393
begin
394
        ld.bte <= wishbone_pkg::LINEAR;
395
        ld.cti <= wishbone_pkg::CLASSIC;
396
        ld.blen <= 'd0;
397
        ld.cyc <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
398
        ld.stb <= req_fifoo.stb && !req_fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5);
399
        ld.we <= 1'b0;
400
        ld.adr <= {app_waddr[31:4],4'h0};
401
        ld.dat <= {app_waddr[31:14],8'h00,rd_data_r};   // modified=false,tag = high order address bits
402
        ld.sel <= {36{1'b1}};           // update all bytes
403
end
404
 
405
reg ch0wack;
406
reg ch1wack;
407
reg ch2wack;
408
reg ch3wack;
409
reg ch4wack;
410
reg ch5wack;
411
reg ch6wack;
412
reg ch7wack;
413
 
414
always_ff @(posedge mem_ui_clk)
415
begin
416
        if (!ch0i.stb)  ch0wack <= 1'b0;
417
        if (!ch1i.stb)  ch1wack <= 1'b0;
418
        if (!ch2i.stb)  ch2wack <= 1'b0;
419
        if (!ch3i.stb)  ch3wack <= 1'b0;
420
        if (!ch4i.stb)  ch4wack <= 1'b0;
421
        if (!ch5i.stb)  ch5wack <= 1'b0;
422
        if (!ch6i.stb)  ch6wack <= 1'b0;
423
        if (!ch7i.stb)  ch7wack <= 1'b0;
424
        if (state==WRITE_DATA3)
425
                case(uch)
426
                4'd0:   ch0wack <= 1'b1;
427
                4'd1: ch1wack <= 1'b1;
428
                4'd2: ch2wack <= 1'b1;
429
                4'd3:   ch3wack <= 1'b1;
430
                4'd4:   ch4wack <= 1'b1;
431
                4'd5:   ch5wack <= 1'b1;
432
                4'd6:   ch6wack <= 1'b1;
433
                4'd7:   ch7wack <= 1'b1;
434
                default:        ;
435
                endcase
436
end
437
 
438
mpmc10_cache_wb ucache1
439
(
440
        .rst(mem_ui_rst),
441
        .wclk(mem_ui_clk),
442
        .inv(),
443
        .wchi(req_fifoo),
444
        .wcho(),
445
        .ld(ld),
446
        .ch0clk(STREAM0 ? 1'b0 : ch0clk),
447
        .ch1clk(STREAM1 ? 1'b0 : ch1clk),
448
        .ch2clk(STREAM2 ? 1'b0 : ch2clk),
449
        .ch3clk(STREAM3 ? 1'b0 : ch3clk),
450
        .ch4clk(STREAM4 ? 1'b0 : ch4clk),
451
        .ch5clk(STREAM5 ? 1'b0 : ch5clk),
452
        .ch6clk(STREAM6 ? 1'b0 : ch6clk),
453
        .ch7clk(STREAM7 ? 1'b0 : ch7clk),
454
        .ch0i(STREAM0 ? 'd0 : ch0is),
455
        .ch1i(STREAM1 ? 'd0 : ch1is),
456
        .ch2i(STREAM2 ? 'd0 : ch2is),
457
        .ch3i(STREAM3 ? 'd0 : ch3is),
458
        .ch4i(STREAM4 ? 'd0 : ch4is),
459
        .ch5i(STREAM5 ? 'd0 : ch5is),
460
        .ch6i(STREAM6 ? 'd0 : ch6is),
461
        .ch7i(STREAM7 ? 'd0 : ch7is),
462
        .ch0wack(ch0wack),
463
        .ch1wack(ch1wack),
464
        .ch2wack(ch2wack),
465
        .ch3wack(ch3wack),
466
        .ch4wack(ch4wack),
467
        .ch5wack(ch5wack),
468
        .ch6wack(ch6wack),
469
        .ch7wack(ch7wack),
470
        .ch0o(ch0oa),
471
        .ch1o(ch1oa),
472
        .ch2o(ch2oa),
473
        .ch3o(ch3oa),
474
        .ch4o(ch4oa),
475
        .ch5o(ch5oa),
476
        .ch6o(ch6oa),
477
        .ch7o(ch7oa)
478
);
479
 
480
mpmc10_strm_read_cache ustrm0
481
(
482
        .rst(rst),
483
        .wclk(mem_ui_clk),
484
        .wr(uch==4'd0 && rd_data_valid_r),
485
        .wadr({app_waddr[31:4],4'h0}),
486
        .wdat(rd_data_r),
487
//      .inv(1'b0),
488
        .rclk(mem_ui_clk),
489
        .rd(ch0is.stb & ~ch0is.we),
490
        .radr({ch0is.adr[31:4],4'h0}),
491
        .rdat(ch0ob.dat),
492
        .hit(ch0_hit_s)
493
);
494
 
495
mpmc10_strm_read_cache ustrm1
496
(
497
        .rst(rst),
498
        .wclk(mem_ui_clk),
499
        .wr(uch==4'd1 && rd_data_valid_r),
500
        .wadr({app_waddr[31:4],4'h0}),
501
        .wdat(rd_data_r),
502
//      .inv(1'b0),
503
        .rclk(mem_ui_clk),
504
        .rd(ch1is.stb & ~ch1is.we),
505
        .radr({ch1is.adr[31:4],4'h0}),
506
        .rdat(ch1ob.dat),
507
        .hit(ch1_hit_s)
508
);
509
 
510
mpmc10_strm_read_cache ustrm2
511
(
512
        .rst(rst),
513
        .wclk(mem_ui_clk),
514
        .wr(uch==4'd2 && rd_data_valid_r),
515
        .wadr({app_waddr[31:4],4'h0}),
516
        .wdat(rd_data_r),
517
//      .inv(1'b0),
518
        .rclk(mem_ui_clk),
519
        .rd(ch2is.stb & ~ch2is.we),
520
        .radr({ch2is.adr[31:4],4'h0}),
521
        .rdat(ch2ob.dat),
522
        .hit(ch2_hit_s)
523
);
524
 
525
mpmc10_strm_read_cache ustrm3
526
(
527
        .rst(rst),
528
        .wclk(mem_ui_clk),
529
        .wr(uch==4'd3 && rd_data_valid_r),
530
        .wadr({app_waddr[31:4],4'h0}),
531
        .wdat(rd_data_r),
532
//      .inv(1'b0),
533
        .rclk(mem_ui_clk),
534
        .rd(ch3is.stb & ~ch3is.we),
535
        .radr({ch3is.adr[31:4],4'h0}),
536
        .rdat(ch3ob.dat),
537
        .hit(ch3_hit_s)
538
);
539
 
540
mpmc10_strm_read_cache ustrm4
541
(
542
        .rst(rst),
543
        .wclk(mem_ui_clk),
544
        .wr(uch==4'd4 && rd_data_valid_r),
545
        .wadr({app_waddr[31:4],4'h0}),
546
        .wdat(rd_data_r),
547
//      .inv(1'b0),
548
        .rclk(mem_ui_clk),
549
        .rd(ch4is.stb & ~ch4is.we),
550
        .radr({ch4is.adr[31:4],4'h0}),
551
        .rdat(ch4ob.dat),
552
        .hit(ch4_hit_s)
553
);
554
 
555
mpmc10_strm_read_cache ustrm5
556
(
557
        .rst(rst),
558
        .wclk(mem_ui_clk),
559
        .wr(uch==4'd5 && rd_data_valid_r),
560
        .wadr({app_waddr[31:4],4'h0}),
561
        .wdat(rd_data_r),
562
//      .inv(1'b0),
563
        .rclk(mem_ui_clk),
564
        .rd(ch5is.stb & ~ch5is.we),
565
        .radr({ch5is.adr[31:4],4'h0}),
566
        .rdat(ch5ob.dat),
567
        .hit(ch5_hit_s)
568
);
569
 
570
mpmc10_strm_read_cache ustrm6
571
(
572
        .rst(rst),
573
        .wclk(mem_ui_clk),
574
        .wr(uch==4'd6 && rd_data_valid_r),
575
        .wadr({app_waddr[31:4],4'h0}),
576
        .wdat(rd_data_r),
577
//      .inv(1'b0),
578
        .rclk(mem_ui_clk),
579
        .rd(ch6is.stb & ~ch6is.we),
580
        .radr({ch6is.adr[31:4],4'h0}),
581
        .rdat(ch6ob.dat),
582
        .hit(ch6_hit_s)
583
);
584
 
585
mpmc10_strm_read_cache ustrm7
586
(
587
        .rst(rst),
588
        .wclk(mem_ui_clk),
589
        .wr(uch==4'd7 && rd_data_valid_r),
590
        .wadr({app_waddr[31:4],4'h0}),
591
        .wdat(rd_data_r),
592
//      .inv(1'b0),
593
        .rclk(mem_ui_clk),
594
        .rd(ch7is.stb & ~ch7is.we),
595
        .radr({ch7is.adr[31:4],4'h0}),
596
        .rdat(ch7ob.dat),
597
        .hit(ch7_hit_s)
598
);
599
 
600
always_comb     ch0ob.ack = ch0_hit_s & ch0i.stb;
601
always_comb     ch1ob.ack = ch1_hit_s & ch1i.stb;
602
always_comb     ch2ob.ack = ch2_hit_s & ch2i.stb;
603
always_comb     ch3ob.ack = ch3_hit_s & ch3i.stb;
604
always_comb     ch4ob.ack = ch4_hit_s & ch4i.stb;
605
always_comb     ch5ob.ack = ch5_hit_s & ch5i.stb;
606
always_comb     ch6ob.ack = ch6_hit_s & ch6i.stb;
607
always_comb     ch7ob.ack = ch7_hit_s & ch7i.stb;
608
 
609
wire [7:0] sel;
610
wire rd_rst_busy;
611
wire wr_rst_busy;
612
wire cd_sel;
613
change_det #(.WID(8)) ucdsel (.rst(rst), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
614
 
615
always_comb     //ff @(posedge mem_ui_clk)
616
        wr_fifo = |sel & ~almost_full & ~wr_rst_busy & cd_sel;
617
 
618
roundRobin rr1
619
(
620
        .rst(rst),
621
        .clk(mem_ui_clk),
622
        .ce(1'b1),//~|req || chack[req_sel]),
623
        .req(req),
624
        .lock(8'h00),
625
        .sel(sel),
626
        .sel_enc(req_sel)
627
);
628
 
629
always_comb
630
        case(req_sel)
631
        4'd0:   req_fifoi <= STREAM0 ? ch0is2 : ch0is;
632
        4'd1:   req_fifoi <= STREAM1 ? ch1is2 : ch1is;
633
        4'd2:   req_fifoi <= STREAM2 ? ch2is2 : ch2is;
634
        4'd3:   req_fifoi <= STREAM3 ? ch3is2 : ch3is;
635
        4'd4:   req_fifoi <= STREAM4 ? ch4is2 : ch4is;
636
        4'd5:   req_fifoi <= STREAM5 ? ch5is2 : ch5is;
637
        4'd6:   req_fifoi <= STREAM6 ? ch6is2 : ch6is;
638
        4'd7:   req_fifoi <= STREAM7 ? ch7is2 : ch7is;
639
        default:        req_fifoi <= 'd0;
640
        endcase
641
 
642
mpmc10_fifo ufifo1
643
(
644
        .rst(rst),
645
        .clk(mem_ui_clk),
646
        .rd_fifo(rd_fifo),
647
        .wr_fifo(wr_fifo),
648
        .req_fifoi(req_fifoi),
649
        .req_fifoo(req_fifoo),
650
        .v(v),
651
        .full(full),
652
        .empty(empty),
653
        .almost_full(almost_full),
654
        .rd_rst_busy(rd_rst_busy),
655
        .wr_rst_busy(wr_rst_busy),
656
        .cnt(cnt)
657
);
658
 
659
always_comb
660
        uch <= req_fifoo.cid;
661
always_comb
662
        num_strips <= req_fifoo.blen;
663
always_comb
664
        adr <= req_fifoo.adr;
665
 
666
wire [2:0] app_addr3;   // dummy to make up 32-bits
667
 
668
mpmc10_addr_gen uag1
669
(
670
        .rst(mem_ui_rst),
671
        .clk(mem_ui_clk),
672
        .state(state),
673
        .rdy(app_rdy),
674
        .num_strips(num_strips),
675
        .strip_cnt(req_strip_cnt),
676
        .addr_base(adr),
677
        .addr({app_addr3,app_addr})
678
);
679
 
680
mpmc10_waddr_gen uwag1
681
(
682
        .rst(mem_ui_rst),
683
        .clk(mem_ui_clk),
684
        .state(state),
685
        .valid(rd_data_valid_r),
686
        .num_strips(num_strips),
687
        .strip_cnt(resp_strip_cnt),
688
        .addr_base(adr),
689
        .addr(app_waddr)
690
);
691
 
692
mpmc10_set_write_mask_wb uswm1
693
(
694
        .clk(mem_ui_clk),
695
        .state(state),
696
        .we(req_fifoo.we),
697
        .sel(req_fifoo.sel[15:0]),
698
        .adr(adr|{req_strip_cnt[0],4'h0}),
699
        .mask(wmask)
700
);
701
 
702
mpmc10_mask_select unsks1
703
(
704
        .rst(mem_ui_rst),
705
        .clk(mem_ui_clk),
706
        .state(state),
707
        .wmask(wmask),
708
        .mask(app_wdf_mask),
709
        .mask2(mem_wdf_mask2)
710
);
711
 
712
mpmc10_data_select #(.WID(128)) uds1
713
(
714
        .clk(mem_ui_clk),
715
        .state(state),
716
        .dati(req_fifoo.dat),
717
        .dato(dat256)
718
);
719
 
720
always_comb
721
        dat128 <= dat256;//req_strip_cnt[0] ? dat256[255:128] : dat256[127:0];
722
 
723
// Setting the data value. Unlike reads there is only a single strip involved.
724
// Force unselected byte lanes to $FF
725
reg [127:0] dat128x;
726
generate begin
727
        for (g = 0; g < 16; g = g + 1)
728
                always_comb
729
                        if (mem_wdf_mask2[g])
730
                                dat128x[g*8+7:g*8] = 8'hFF;
731
                        else
732
                                dat128x[g*8+7:g*8] = dat128[g*8+7:g*8];
733
end
734
endgenerate
735
 
736
always_ff @(posedge mem_ui_clk)
737
if (mem_ui_rst)
738
  app_wdf_data <= 128'd0;
739
else begin
740
        if (state==PRESET2)
741
                app_wdf_data <= dat128x;
742
//      else if (state==WRITE_TRAMP1)
743
//              app_wdf_data <= rmw_data;
744
end
745
 
746
 
747
mpmc10_state_machine_wb usm1
748
(
749
        .rst(rst|mem_ui_rst),
750
        .clk(mem_ui_clk),
751
        .to(tocnt[9]),
752
        .rdy(app_rdy),
753
        .wdf_rdy(app_wdf_rdy),
754
        .fifo_empty(empty),
755
        .rd_rst_busy(rd_rst_busy),
756
        .rd_fifo(rd_fifo),
757
        .fifo_out(req_fifoo),
758
        .state(state),
759
        .num_strips(num_strips),
760
        .req_strip_cnt(req_strip_cnt),
761
        .resp_strip_cnt(resp_strip_cnt),
762
        .rd_data_valid(rd_data_valid_r)
763
);
764
 
765
mpmc10_to_cnt utoc1
766
(
767
        .clk(mem_ui_clk),
768
        .state(state),
769
        .prev_state(prev_state),
770
        .to_cnt(tocnt)
771
);
772
 
773
mpmc10_prev_state upst1
774
(
775
        .clk(mem_ui_clk),
776
        .state(state),
777
        .prev_state(prev_state)
778
);
779
 
780
mpmc10_app_en_gen ueng1
781
(
782
        .clk(mem_ui_clk),
783
        .state(state),
784
        .rdy(app_rdy),
785
        .strip_cnt(req_strip_cnt),
786
        .num_strips(num_strips),
787
        .en(app_en)
788
);
789
 
790
mpmc10_app_cmd_gen ucg1
791
(
792
        .clk(mem_ui_clk),
793
        .state(state),
794
        .cmd(app_cmd)
795
);
796
 
797
mpmc10_app_wdf_wren_gen uwreng1
798
(
799
        .clk(mem_ui_clk),
800
        .state(state),
801
        .rdy(app_wdf_rdy),
802
        .wren(app_wdf_wren)
803
);
804
 
805
mpmc10_app_wdf_end_gen uwendg1
806
(
807
        .clk(mem_ui_clk),
808
        .state(state),
809
        .rdy(app_wdf_rdy),
810
        .strip_cnt(req_strip_cnt),
811
        .num_strips(num_strips),
812
        .wend(app_wdf_end)
813
);
814
 
815
mpmc10_req_strip_cnt ursc1
816
(
817
        .clk(mem_ui_clk),
818
        .state(state),
819
        .wdf_rdy(app_wdf_rdy),
820
        .rdy(app_rdy),
821
        .num_strips(num_strips),
822
        .strip_cnt(req_strip_cnt)
823
);
824
 
825
mpmc10_resp_strip_cnt urespsc1
826
(
827
        .clk(mem_ui_clk),
828
        .state(state),
829
        .valid(rd_data_valid_r),
830
        .num_strips(num_strips),
831
        .strip_cnt(resp_strip_cnt)
832
);
833
 
834
// Reservation status bit
835
mpmc10_resv_bit ursb1
836
(
837
        .clk(mem_ui_clk),
838
        .state(state),
839
        .wch(req_fifoo.cid),
840
        .we(req_fifoo.stb & req_fifoo.we),
841
        .cr(req_fifoo.csr & req_fifoo.we),
842
        .adr(req_fifoo.adr),
843
        .resv_ch(resv_ch),
844
        .resv_adr(resv_adr),
845
        .rb(rb1)
846
);
847
 
848
mpmc10_addr_resv_man #(.NAR(NAR)) ursvm1
849
(
850
        .rst(mem_ui_rst),
851
        .clk(mem_ui_clk),
852
        .state(state),
853
        .adr0(32'h0),
854
        .adr1(ch1is.adr),
855
        .adr2(ch2is.adr),
856
        .adr3(ch3is.adr),
857
        .adr4(ch4is.adr),
858
        .adr5(32'h0),
859
        .adr6(ch6is.adr),
860
        .adr7(ch7is.adr),
861
        .sr0(1'b0),
862
        .sr1(ch1is.csr & ch1is.stb & ~ch1is.we),
863
        .sr2(ch2is.csr & ch2is.stb & ~ch2is.we),
864
        .sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
865
        .sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
866
        .sr5(1'b0),
867
        .sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
868
        .sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
869
        .wch(req_fifoo.stb ? req_fifoo.cid : 4'd15),
870
        .we(req_fifoo.stb & req_fifoo.we),
871
        .wadr(req_fifoo.adr),
872
        .cr(req_fifoo.csr & req_fifoo.stb & req_fifoo.we),
873
        .resv_ch(resv_ch),
874
        .resv_adr(resv_adr)
875
);
876
 
877
endmodule

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