OpenCores
URL https://opencores.org/ocsvn/mpmc8/mpmc8/trunk

Subversion Repositories mpmc8

[/] [mpmc8/] [trunk/] [rtl/] [mpmc10/] [mpmc10_wb.sv] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch@finitron.ca
7
//       ||
8
//
9
// BSD 3-Clause License
10
// Redistribution and use in source and binary forms, with or without
11
// modification, are permitted provided that the following conditions are met:
12
//
13
// 1. Redistributions of source code must retain the above copyright notice, this
14
//    list of conditions and the following disclaimer.
15
//
16
// 2. Redistributions in binary form must reproduce the above copyright notice,
17
//    this list of conditions and the following disclaimer in the documentation
18
//    and/or other materials provided with the distribution.
19
//
20
// 3. Neither the name of the copyright holder nor the names of its
21
//    contributors may be used to endorse or promote products derived from
22
//    this software without specific prior written permission.
23
//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
//
35
// 16000 LUTs, 130 BRAM (64kB cache)
36
//
37
// Read channels always wait until there is valid data in the cache.
38
// ============================================================================
39
//
40
//`define RED_SCREEN    1'b1
41
 
42
import wishbone_pkg::*;
43
import mpmc10_pkg::*;
44
 
45
module mpmc10_wb(
46
input rst,
47
input clk100MHz,
48
input mem_ui_rst,
49
input mem_ui_clk,
50 7 robfinch
input calib_complete,
51 5 robfinch
output reg rstn,
52
output [31:0] app_waddr,
53
input app_rdy,
54
output app_en,
55
output [2:0] app_cmd,
56
output [28:0] app_addr,
57
input app_rd_data_valid,
58
output [15:0] app_wdf_mask,
59
output reg [127:0] app_wdf_data,
60
input app_wdf_rdy,
61
output app_wdf_wren,
62
output app_wdf_end,
63
input [127:0] app_rd_data,
64
input app_rd_data_end,
65
input ch0clk, ch1clk, ch2clk, ch3clk, ch4clk, ch5clk, ch6clk, ch7clk,
66
input wb_write_request128_t ch0i,
67
output wb_read_response128_t ch0o,
68
input wb_write_request128_t ch1i,
69
output wb_read_response128_t ch1o,
70
input wb_write_request128_t ch2i,
71
output wb_read_response128_t ch2o,
72
input wb_write_request128_t ch3i,
73
output wb_read_response128_t ch3o,
74
input wb_write_request128_t ch4i,
75
output wb_read_response128_t ch4o,
76
input wb_write_request128_t ch5i,
77
output wb_read_response128_t ch5o,
78
input wb_write_request128_t ch6i,
79
output wb_read_response128_t ch6o,
80
input wb_write_request128_t ch7i,
81
output wb_read_response128_t ch7o,
82 7 robfinch
output mpmc10_state_t state
83 5 robfinch
);
84
parameter NAR = 2;                      // Number of address reservations
85
parameter CL = 3'd4;            // Cache read latency
86
parameter STREAM0 = TRUE;
87
parameter STREAM1 = FALSE;
88
parameter STREAM2 = FALSE;
89
parameter STREAM3 = FALSE;
90
parameter STREAM4 = FALSE;
91
parameter STREAM5 = TRUE;
92
parameter STREAM6 = FALSE;
93
parameter STREAM7 = FALSE;
94
 
95
wb_write_request128_t ch0is;
96
wb_write_request128_t ch0is2;
97
wb_write_request128_t ch1is;
98
wb_write_request128_t ch1is2;
99
wb_write_request128_t ch2is;
100
wb_write_request128_t ch2is2;
101
wb_write_request128_t ch3is;
102
wb_write_request128_t ch3is2;
103
wb_write_request128_t ch4is;
104
wb_write_request128_t ch4is2;
105
wb_write_request128_t ch5is;
106
wb_write_request128_t ch5is2;
107
wb_write_request128_t ch6is;
108
wb_write_request128_t ch6is2;
109
wb_write_request128_t ch7is;
110
wb_write_request128_t ch7is2;
111
 
112
wb_read_response128_t ch0oa, ch0ob;
113
wb_read_response128_t ch1oa, ch1ob;
114
wb_read_response128_t ch2oa, ch2ob;
115
wb_read_response128_t ch3oa, ch3ob;
116
wb_read_response128_t ch4oa, ch4ob;
117
wb_read_response128_t ch5oa, ch5ob;
118
wb_read_response128_t ch6oa, ch6ob;
119
wb_read_response128_t ch7oa, ch7ob;
120
 
121
assign ch0o = STREAM0 ? ch0ob : ch0oa;
122
assign ch1o = STREAM1 ? ch1ob : ch1oa;
123
assign ch2o = STREAM2 ? ch2ob : ch2oa;
124
assign ch3o = STREAM3 ? ch3ob : ch3oa;
125
assign ch4o = STREAM4 ? ch4ob : ch4oa;
126
assign ch5o = STREAM5 ? ch5ob : ch5oa;
127
assign ch6o = STREAM6 ? ch6ob : ch6oa;
128
assign ch7o = STREAM7 ? ch7ob : ch7oa;
129
 
130
wb_write_request128_t req_fifoi;
131
wb_write_request128_t req_fifoo;
132
wb_write_request128_t ld;
133 7 robfinch
wb_write_request128_t fifo_mask;
134
wb_write_request128_t fifoo = req_fifoo & fifo_mask;
135 5 robfinch
 
136
genvar g;
137 7 robfinch
integer n1,n2,n3;
138 5 robfinch
wire almost_full;
139
wire [4:0] cnt;
140
reg wr_fifo;
141 7 robfinch
mpmc10_state_t prev_state;
142 5 robfinch
wire rd_fifo;   // from state machine
143
reg [5:0] num_strips;   // from fifo
144
wire [5:0] req_strip_cnt;
145
wire [5:0] resp_strip_cnt;
146
wire [15:0] tocnt;
147
wire [31:0] app_waddr;
148
reg [31:0] adr;
149
reg [3:0] uch;          // update channel
150
wire [15:0] wmask;
151
wire [15:0] mem_wdf_mask2;
152
reg [127:0] dat128;
153 7 robfinch
wire [127:0] dat256;
154 5 robfinch
wire [3:0] resv_ch [0:NAR-1];
155
wire [31:0] resv_adr [0:NAR-1];
156
wire rb1;
157
reg [7:0] req;
158
reg [127:0] rd_data_r;
159
reg rd_data_valid_r;
160
 
161
wire ch0_hit_s, ch1_hit_s, ch2_hit_s, ch3_hit_s;
162
wire ch4_hit_s, ch5_hit_s, ch6_hit_s, ch7_hit_s;
163
wire ch0_hit_ne, ch5_hit_ne;
164
 
165
always_ff @(posedge mem_ui_clk)
166
        rd_data_r <= app_rd_data;
167
always_ff @(posedge mem_ui_clk)
168
        rd_data_valid_r <= app_rd_data_valid;
169
 
170
reg [19:0] rst_ctr;
171
always @(posedge clk100MHz)
172
if (rst)
173
        rst_ctr <= 24'd0;
174
else begin
175
        if (!rst_ctr[15])
176
                rst_ctr <= rst_ctr + 2'd1;
177
        rstn <= rst_ctr[15];
178
end
179
 
180
reg [7:0] stb [0:7];
181
always_comb stb[0] = ch0is.stb;
182
always_comb stb[1] = ch1is.stb;
183
always_comb stb[2] = ch2is.stb;
184
always_comb stb[3] = ch3is.stb;
185
always_comb stb[4] = ch4is.stb;
186
always_comb stb[5] = ch5is.stb;
187
always_comb stb[6] = ch6is.stb;
188
always_comb stb[7] = ch7is.stb;
189
 
190
reg [2:0] chcnt [0:7];
191
always_ff @(posedge mem_ui_clk)
192
if (rst) begin
193
        for (n2 = 0; n2 < 8; n2 = n2 + 1)
194
                chcnt[n2] <= 'd0;
195
end
196
else begin
197
        for (n2 = 0; n2 < 8; n2 = n2 + 1)
198
                if (stb[n2]) begin
199
                        if (chcnt[n2] < CL)
200
                                chcnt[n2] <= chcnt[n2] + 2'd1;
201
                end
202
                else
203
                        chcnt[n2] <= 'd0;
204
end
205
 
206 7 robfinch
wire [7:0] pe_req;
207 5 robfinch
reg [7:0] chack;
208
always_comb chack[0] = ch0o.ack;
209
always_comb chack[1] = ch1o.ack;
210
always_comb chack[2] = ch2o.ack;
211
always_comb chack[3] = ch3o.ack;
212
always_comb chack[4] = ch4o.ack;
213
always_comb chack[5] = ch5o.ack;
214
always_comb chack[6] = ch6o.ack;
215
always_comb chack[7] = ch7o.ack;
216
 
217 7 robfinch
reg [7:0] reqa;
218
always_comb reqa[1] = (!ch1o.ack && ch1is.stb && !ch1is.we && chcnt[1]==CL) || (ch1is.we && ch1is.stb);
219
always_comb reqa[5] = (!ch5o.ack && ch5is.stb && !ch5is.we && chcnt[5]==CL) || (ch5is.we && ch5is.stb);
220
 
221
wire rste = mem_ui_rst||rst||!calib_complete;
222
 
223 5 robfinch
edge_det edch0 (
224 7 robfinch
        .rst(rste),
225 5 robfinch
        .clk(mem_ui_clk),
226
        .ce(1'b1),
227
        .i((!ch0o.ack && ch0is.stb && !ch0is.we && chcnt[0]==CL) || (ch0is.we && ch0is.stb)),
228
        .pe(pe_req[0]),
229
        .ne(),
230
        .ee()
231
);
232
edge_det edch1 (
233 7 robfinch
        .rst(rste),
234 5 robfinch
        .clk(mem_ui_clk),
235
        .ce(1'b1),
236 7 robfinch
        .i(reqa[1]),
237 5 robfinch
        .pe(pe_req[1]),
238
        .ne(),
239
        .ee()
240
);
241
edge_det edch2 (
242 7 robfinch
        .rst(rste),
243 5 robfinch
        .clk(mem_ui_clk),
244
        .ce(1'b1),
245
        .i((!ch2o.ack && ch2is.stb && !ch2is.we && chcnt[2]==CL) || (ch2is.we && ch2is.stb)),
246
        .pe(pe_req[2]),
247
        .ne(),
248
        .ee()
249
);
250
edge_det edch3 (
251 7 robfinch
        .rst(rste),
252 5 robfinch
        .clk(mem_ui_clk),
253
        .ce(1'b1),
254
        .i((!ch3o.ack && ch3is.stb && !ch3is.we && chcnt[3]==CL) || (ch3is.we && ch3is.stb)),
255
        .pe(pe_req[3]),
256
        .ne(),
257
        .ee()
258
);
259
edge_det edch4 (
260 7 robfinch
        .rst(rste),
261 5 robfinch
        .clk(mem_ui_clk),
262
        .ce(1'b1),
263
        .i((!ch4o.ack && ch4is.stb && !ch4is.we && chcnt[4]==CL) || (ch4is.we && ch4is.stb)),
264
        .pe(pe_req[4]),
265
        .ne(),
266
        .ee()
267
);
268
edge_det edch5 (
269 7 robfinch
        .rst(rste),
270 5 robfinch
        .clk(mem_ui_clk),
271
        .ce(1'b1),
272 7 robfinch
        .i(reqa[5]),
273 5 robfinch
        .pe(pe_req[5]),
274
        .ne(),
275
        .ee()
276
);
277
edge_det edch6 (
278 7 robfinch
        .rst(rste),
279 5 robfinch
        .clk(mem_ui_clk),
280
        .ce(1'b1),
281
        .i((!ch6o.ack && ch6is.stb && !ch6is.we && chcnt[6]==CL) || (ch6is.we && ch6is.stb)),
282
        .pe(pe_req[6]),
283
        .ne(),
284
        .ee()
285
);
286
edge_det edch7 (
287 7 robfinch
        .rst(rste),
288 5 robfinch
        .clk(mem_ui_clk),
289
        .ce(1'b1),
290
        .i((!ch7o.ack && ch7is.stb && !ch7is.we && chcnt[7]==CL) || (ch7is.we && ch7is.stb)),
291
        .pe(pe_req[7]),
292
        .ne(),
293
        .ee()
294
);
295
wire [3:0] req_sel;
296 7 robfinch
always_ff @(posedge mem_ui_clk)
297
        for (n3 = 0; n3 < 8; n3 = n3 + 1)
298
                if (pe_req[n3])
299
                        req[n3] <= 1'b1;
300
                else if ((req_sel==n3[3:0]) || chack[n3])
301
                        req[n3] <= 1'b0;
302 5 robfinch
 
303
// Register signals onto mem_ui_clk domain
304
mpmc10_sync128_wb usyn0
305
(
306
        .clk(mem_ui_clk),
307
        .i(ch0i),
308
        .o(ch0is)
309
);
310
mpmc10_sync128_wb usyn1
311
(
312
        .clk(mem_ui_clk),
313
        .i(ch1i),
314
        .o(ch1is)
315
);
316
mpmc10_sync128_wb usyn2
317
(
318
        .clk(mem_ui_clk),
319
        .i(ch2i),
320
        .o(ch2is)
321
);
322
mpmc10_sync128_wb usyn3
323
(
324
        .clk(mem_ui_clk),
325
        .i(ch3i),
326
        .o(ch3is)
327
);
328
mpmc10_sync128_wb usyn4
329
(
330
        .clk(mem_ui_clk),
331
        .i(ch4i),
332
        .o(ch4is)
333
);
334
mpmc10_sync128_wb usyn5
335
(
336
        .clk(mem_ui_clk),
337
        .i(ch5i),
338
        .o(ch5is)
339
);
340
mpmc10_sync128_wb usyn6
341
(
342
        .clk(mem_ui_clk),
343
        .i(ch6i),
344
        .o(ch6is)
345
);
346
mpmc10_sync128_wb usyn7
347
(
348
        .clk(mem_ui_clk),
349
        .i(ch7i),
350
        .o(ch7is)
351
);
352
 
353
// Streaming channels have a burst length of 64. Round the address to the burst
354
// length.
355
always_comb
356
begin
357
        ch0is2 <= ch0is;
358
        ch0is2.adr <= {ch0is.adr[31:10],10'b0};
359
end
360
always_comb
361
begin
362
        ch1is2 <= ch1is;
363
        ch1is2.adr <= {ch1is.adr[31:10],10'b0};
364
end
365
always_comb
366
begin
367
        ch2is2 <= ch2is;
368
        ch2is2.adr <= {ch2is.adr[31:10],10'b0};
369
end
370
always_comb
371
begin
372
        ch3is2 <= ch3is;
373
        ch3is2.adr <= {ch3is.adr[31:10],10'b0};
374
end
375
always_comb
376
begin
377
        ch4is2 <= ch4is;
378
        ch4is2.adr <= {ch4is.adr[31:10],10'b0};
379
end
380
always_comb
381
begin
382
        ch5is2 <= ch5is;
383
        ch5is2.adr <= {ch5is.adr[31:10],10'b0};
384
end
385
always_comb
386
begin
387
        ch6is2 <= ch6is;
388
        ch6is2.adr <= {ch6is.adr[31:10],10'b0};
389
end
390
always_comb
391
begin
392
        ch7is2 <= ch7is;
393
        ch7is2.adr <= {ch7is.adr[31:10],10'b0};
394
end
395
 
396
always_comb
397
begin
398
        ld.bte <= wishbone_pkg::LINEAR;
399
        ld.cti <= wishbone_pkg::CLASSIC;
400
        ld.blen <= 'd0;
401 7 robfinch
        ld.cyc <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
402
        ld.stb <= fifoo.stb && !fifoo.we && rd_data_valid_r && (uch!=4'd0 && uch!=4'd5 && uch!=4'd15);
403 5 robfinch
        ld.we <= 1'b0;
404
        ld.adr <= {app_waddr[31:4],4'h0};
405
        ld.dat <= {app_waddr[31:14],8'h00,rd_data_r};   // modified=false,tag = high order address bits
406
        ld.sel <= {36{1'b1}};           // update all bytes
407
end
408
 
409
reg ch0wack;
410
reg ch1wack;
411
reg ch2wack;
412
reg ch3wack;
413
reg ch4wack;
414
reg ch5wack;
415
reg ch6wack;
416
reg ch7wack;
417
 
418
always_ff @(posedge mem_ui_clk)
419
begin
420
        if (!ch0i.stb)  ch0wack <= 1'b0;
421
        if (!ch1i.stb)  ch1wack <= 1'b0;
422
        if (!ch2i.stb)  ch2wack <= 1'b0;
423
        if (!ch3i.stb)  ch3wack <= 1'b0;
424
        if (!ch4i.stb)  ch4wack <= 1'b0;
425
        if (!ch5i.stb)  ch5wack <= 1'b0;
426
        if (!ch6i.stb)  ch6wack <= 1'b0;
427
        if (!ch7i.stb)  ch7wack <= 1'b0;
428
        if (state==WRITE_DATA3)
429
                case(uch)
430
                4'd0:   ch0wack <= 1'b1;
431
                4'd1: ch1wack <= 1'b1;
432
                4'd2: ch2wack <= 1'b1;
433
                4'd3:   ch3wack <= 1'b1;
434
                4'd4:   ch4wack <= 1'b1;
435
                4'd5:   ch5wack <= 1'b1;
436
                4'd6:   ch6wack <= 1'b1;
437
                4'd7:   ch7wack <= 1'b1;
438
                default:        ;
439
                endcase
440
end
441
 
442
mpmc10_cache_wb ucache1
443
(
444
        .rst(mem_ui_rst),
445
        .wclk(mem_ui_clk),
446 7 robfinch
        .inv(1'b0),
447
        .wchi(fifoo),
448 5 robfinch
        .wcho(),
449
        .ld(ld),
450
        .ch0clk(STREAM0 ? 1'b0 : ch0clk),
451
        .ch1clk(STREAM1 ? 1'b0 : ch1clk),
452
        .ch2clk(STREAM2 ? 1'b0 : ch2clk),
453
        .ch3clk(STREAM3 ? 1'b0 : ch3clk),
454
        .ch4clk(STREAM4 ? 1'b0 : ch4clk),
455
        .ch5clk(STREAM5 ? 1'b0 : ch5clk),
456
        .ch6clk(STREAM6 ? 1'b0 : ch6clk),
457
        .ch7clk(STREAM7 ? 1'b0 : ch7clk),
458
        .ch0i(STREAM0 ? 'd0 : ch0is),
459
        .ch1i(STREAM1 ? 'd0 : ch1is),
460
        .ch2i(STREAM2 ? 'd0 : ch2is),
461
        .ch3i(STREAM3 ? 'd0 : ch3is),
462
        .ch4i(STREAM4 ? 'd0 : ch4is),
463
        .ch5i(STREAM5 ? 'd0 : ch5is),
464
        .ch6i(STREAM6 ? 'd0 : ch6is),
465
        .ch7i(STREAM7 ? 'd0 : ch7is),
466
        .ch0wack(ch0wack),
467
        .ch1wack(ch1wack),
468
        .ch2wack(ch2wack),
469
        .ch3wack(ch3wack),
470
        .ch4wack(ch4wack),
471
        .ch5wack(ch5wack),
472
        .ch6wack(ch6wack),
473
        .ch7wack(ch7wack),
474
        .ch0o(ch0oa),
475
        .ch1o(ch1oa),
476
        .ch2o(ch2oa),
477
        .ch3o(ch3oa),
478
        .ch4o(ch4oa),
479
        .ch5o(ch5oa),
480
        .ch6o(ch6oa),
481
        .ch7o(ch7oa)
482
);
483
 
484
mpmc10_strm_read_cache ustrm0
485
(
486
        .rst(rst),
487
        .wclk(mem_ui_clk),
488
        .wr(uch==4'd0 && rd_data_valid_r),
489
        .wadr({app_waddr[31:4],4'h0}),
490
        .wdat(rd_data_r),
491
//      .inv(1'b0),
492
        .rclk(mem_ui_clk),
493
        .rd(ch0is.stb & ~ch0is.we),
494
        .radr({ch0is.adr[31:4],4'h0}),
495
        .rdat(ch0ob.dat),
496
        .hit(ch0_hit_s)
497
);
498
 
499
mpmc10_strm_read_cache ustrm1
500
(
501
        .rst(rst),
502
        .wclk(mem_ui_clk),
503
        .wr(uch==4'd1 && rd_data_valid_r),
504
        .wadr({app_waddr[31:4],4'h0}),
505
        .wdat(rd_data_r),
506
//      .inv(1'b0),
507
        .rclk(mem_ui_clk),
508
        .rd(ch1is.stb & ~ch1is.we),
509
        .radr({ch1is.adr[31:4],4'h0}),
510
        .rdat(ch1ob.dat),
511
        .hit(ch1_hit_s)
512
);
513
 
514
mpmc10_strm_read_cache ustrm2
515
(
516
        .rst(rst),
517
        .wclk(mem_ui_clk),
518
        .wr(uch==4'd2 && rd_data_valid_r),
519
        .wadr({app_waddr[31:4],4'h0}),
520
        .wdat(rd_data_r),
521
//      .inv(1'b0),
522
        .rclk(mem_ui_clk),
523
        .rd(ch2is.stb & ~ch2is.we),
524
        .radr({ch2is.adr[31:4],4'h0}),
525
        .rdat(ch2ob.dat),
526
        .hit(ch2_hit_s)
527
);
528
 
529
mpmc10_strm_read_cache ustrm3
530
(
531
        .rst(rst),
532
        .wclk(mem_ui_clk),
533
        .wr(uch==4'd3 && rd_data_valid_r),
534
        .wadr({app_waddr[31:4],4'h0}),
535
        .wdat(rd_data_r),
536
//      .inv(1'b0),
537
        .rclk(mem_ui_clk),
538
        .rd(ch3is.stb & ~ch3is.we),
539
        .radr({ch3is.adr[31:4],4'h0}),
540
        .rdat(ch3ob.dat),
541
        .hit(ch3_hit_s)
542
);
543
 
544
mpmc10_strm_read_cache ustrm4
545
(
546
        .rst(rst),
547
        .wclk(mem_ui_clk),
548
        .wr(uch==4'd4 && rd_data_valid_r),
549
        .wadr({app_waddr[31:4],4'h0}),
550
        .wdat(rd_data_r),
551
//      .inv(1'b0),
552
        .rclk(mem_ui_clk),
553
        .rd(ch4is.stb & ~ch4is.we),
554
        .radr({ch4is.adr[31:4],4'h0}),
555
        .rdat(ch4ob.dat),
556
        .hit(ch4_hit_s)
557
);
558
 
559
mpmc10_strm_read_cache ustrm5
560
(
561
        .rst(rst),
562
        .wclk(mem_ui_clk),
563
        .wr(uch==4'd5 && rd_data_valid_r),
564
        .wadr({app_waddr[31:4],4'h0}),
565
        .wdat(rd_data_r),
566
//      .inv(1'b0),
567
        .rclk(mem_ui_clk),
568
        .rd(ch5is.stb & ~ch5is.we),
569
        .radr({ch5is.adr[31:4],4'h0}),
570
        .rdat(ch5ob.dat),
571
        .hit(ch5_hit_s)
572
);
573
 
574
mpmc10_strm_read_cache ustrm6
575
(
576
        .rst(rst),
577
        .wclk(mem_ui_clk),
578
        .wr(uch==4'd6 && rd_data_valid_r),
579
        .wadr({app_waddr[31:4],4'h0}),
580
        .wdat(rd_data_r),
581
//      .inv(1'b0),
582
        .rclk(mem_ui_clk),
583
        .rd(ch6is.stb & ~ch6is.we),
584
        .radr({ch6is.adr[31:4],4'h0}),
585
        .rdat(ch6ob.dat),
586
        .hit(ch6_hit_s)
587
);
588
 
589
mpmc10_strm_read_cache ustrm7
590
(
591
        .rst(rst),
592
        .wclk(mem_ui_clk),
593
        .wr(uch==4'd7 && rd_data_valid_r),
594
        .wadr({app_waddr[31:4],4'h0}),
595
        .wdat(rd_data_r),
596
//      .inv(1'b0),
597
        .rclk(mem_ui_clk),
598
        .rd(ch7is.stb & ~ch7is.we),
599
        .radr({ch7is.adr[31:4],4'h0}),
600
        .rdat(ch7ob.dat),
601
        .hit(ch7_hit_s)
602
);
603
 
604
always_comb     ch0ob.ack = ch0_hit_s & ch0i.stb;
605
always_comb     ch1ob.ack = ch1_hit_s & ch1i.stb;
606
always_comb     ch2ob.ack = ch2_hit_s & ch2i.stb;
607
always_comb     ch3ob.ack = ch3_hit_s & ch3i.stb;
608
always_comb     ch4ob.ack = ch4_hit_s & ch4i.stb;
609
always_comb     ch5ob.ack = ch5_hit_s & ch5i.stb;
610
always_comb     ch6ob.ack = ch6_hit_s & ch6i.stb;
611
always_comb     ch7ob.ack = ch7_hit_s & ch7i.stb;
612
 
613
wire [7:0] sel;
614
wire rd_rst_busy;
615
wire wr_rst_busy;
616
wire cd_sel;
617 7 robfinch
change_det #(.WID(8)) ucdsel (.rst(rst), .ce(1'b1), .clk(mem_ui_clk), .i(sel), .cd(cd_sel));
618 5 robfinch
 
619
always_comb     //ff @(posedge mem_ui_clk)
620
        wr_fifo = |sel & ~almost_full & ~wr_rst_busy & cd_sel;
621
 
622
roundRobin rr1
623
(
624
        .rst(rst),
625
        .clk(mem_ui_clk),
626
        .ce(1'b1),//~|req || chack[req_sel]),
627
        .req(req),
628
        .lock(8'h00),
629
        .sel(sel),
630
        .sel_enc(req_sel)
631
);
632
 
633
always_comb
634
        case(req_sel)
635
        4'd0:   req_fifoi <= STREAM0 ? ch0is2 : ch0is;
636
        4'd1:   req_fifoi <= STREAM1 ? ch1is2 : ch1is;
637
        4'd2:   req_fifoi <= STREAM2 ? ch2is2 : ch2is;
638
        4'd3:   req_fifoi <= STREAM3 ? ch3is2 : ch3is;
639
        4'd4:   req_fifoi <= STREAM4 ? ch4is2 : ch4is;
640
        4'd5:   req_fifoi <= STREAM5 ? ch5is2 : ch5is;
641
        4'd6:   req_fifoi <= STREAM6 ? ch6is2 : ch6is;
642
        4'd7:   req_fifoi <= STREAM7 ? ch7is2 : ch7is;
643 7 robfinch
        default:
644
                begin
645
                        req_fifoi <= 'd0;
646
                        req_fifoi.cid <= 4'd15;
647
                end
648 5 robfinch
        endcase
649
 
650
mpmc10_fifo ufifo1
651
(
652
        .rst(rst),
653
        .clk(mem_ui_clk),
654
        .rd_fifo(rd_fifo),
655
        .wr_fifo(wr_fifo),
656
        .req_fifoi(req_fifoi),
657
        .req_fifoo(req_fifoo),
658
        .v(v),
659
        .full(full),
660
        .empty(empty),
661
        .almost_full(almost_full),
662
        .rd_rst_busy(rd_rst_busy),
663
        .wr_rst_busy(wr_rst_busy),
664
        .cnt(cnt)
665
);
666
 
667
always_comb
668 7 robfinch
        uch <= fifoo.cid;
669 5 robfinch
always_comb
670 7 robfinch
        num_strips <= fifoo.blen;
671 5 robfinch
always_comb
672 7 robfinch
        adr <= fifoo.adr;
673 5 robfinch
 
674
wire [2:0] app_addr3;   // dummy to make up 32-bits
675
 
676
mpmc10_addr_gen uag1
677
(
678
        .rst(mem_ui_rst),
679
        .clk(mem_ui_clk),
680
        .state(state),
681
        .rdy(app_rdy),
682
        .num_strips(num_strips),
683
        .strip_cnt(req_strip_cnt),
684
        .addr_base(adr),
685
        .addr({app_addr3,app_addr})
686
);
687
 
688
mpmc10_waddr_gen uwag1
689
(
690
        .rst(mem_ui_rst),
691
        .clk(mem_ui_clk),
692
        .state(state),
693
        .valid(rd_data_valid_r),
694
        .num_strips(num_strips),
695
        .strip_cnt(resp_strip_cnt),
696
        .addr_base(adr),
697
        .addr(app_waddr)
698
);
699
 
700
mpmc10_set_write_mask_wb uswm1
701
(
702
        .clk(mem_ui_clk),
703
        .state(state),
704 7 robfinch
        .we(fifoo.we),
705 5 robfinch
        .sel(req_fifoo.sel[15:0]),
706
        .adr(adr|{req_strip_cnt[0],4'h0}),
707
        .mask(wmask)
708
);
709
 
710
mpmc10_mask_select unsks1
711
(
712
        .rst(mem_ui_rst),
713
        .clk(mem_ui_clk),
714
        .state(state),
715
        .wmask(wmask),
716
        .mask(app_wdf_mask),
717
        .mask2(mem_wdf_mask2)
718
);
719
 
720
mpmc10_data_select #(.WID(128)) uds1
721
(
722
        .clk(mem_ui_clk),
723
        .state(state),
724
        .dati(req_fifoo.dat),
725
        .dato(dat256)
726
);
727
 
728
always_comb
729
        dat128 <= dat256;//req_strip_cnt[0] ? dat256[255:128] : dat256[127:0];
730
 
731
// Setting the data value. Unlike reads there is only a single strip involved.
732
// Force unselected byte lanes to $FF
733
reg [127:0] dat128x;
734
generate begin
735
        for (g = 0; g < 16; g = g + 1)
736
                always_comb
737
                        if (mem_wdf_mask2[g])
738
                                dat128x[g*8+7:g*8] = 8'hFF;
739
                        else
740
                                dat128x[g*8+7:g*8] = dat128[g*8+7:g*8];
741
end
742
endgenerate
743
 
744
always_ff @(posedge mem_ui_clk)
745
if (mem_ui_rst)
746
  app_wdf_data <= 128'd0;
747
else begin
748 7 robfinch
        if (state==PRESET3)
749 5 robfinch
                app_wdf_data <= dat128x;
750
//      else if (state==WRITE_TRAMP1)
751
//              app_wdf_data <= rmw_data;
752
end
753
 
754 7 robfinch
mpmc10_rd_fifo_gen urdf1
755
(
756
        .rst(rst|mem_ui_rst),
757
        .clk(mem_ui_clk),
758
        .state(state),
759
        .empty(empty),
760
        .rd_rst_busy(rd_rst_busy),
761
        .calib_complete(calib_complete),
762
        .rd(rd_fifo)
763
);
764 5 robfinch
 
765 7 robfinch
always_ff @(posedge mem_ui_clk)
766
if (rst)
767
        fifo_mask <= 'd0;
768
else begin
769
        if (rd_fifo)
770
                fifo_mask <= {$bits(fifo_mask){1'b1}};
771
        else if (state==IDLE)
772
                fifo_mask <= 'd0;
773
end
774
 
775 5 robfinch
mpmc10_state_machine_wb usm1
776
(
777
        .rst(rst|mem_ui_rst),
778
        .clk(mem_ui_clk),
779 7 robfinch
        .calib_complete(calib_complete),
780 5 robfinch
        .to(tocnt[9]),
781
        .rdy(app_rdy),
782
        .wdf_rdy(app_wdf_rdy),
783
        .fifo_empty(empty),
784
        .rd_rst_busy(rd_rst_busy),
785
        .fifo_out(req_fifoo),
786
        .state(state),
787
        .num_strips(num_strips),
788
        .req_strip_cnt(req_strip_cnt),
789
        .resp_strip_cnt(resp_strip_cnt),
790
        .rd_data_valid(rd_data_valid_r)
791
);
792
 
793
mpmc10_to_cnt utoc1
794
(
795
        .clk(mem_ui_clk),
796
        .state(state),
797
        .prev_state(prev_state),
798
        .to_cnt(tocnt)
799
);
800
 
801
mpmc10_prev_state upst1
802
(
803
        .clk(mem_ui_clk),
804
        .state(state),
805
        .prev_state(prev_state)
806
);
807
 
808
mpmc10_app_en_gen ueng1
809
(
810
        .clk(mem_ui_clk),
811
        .state(state),
812
        .rdy(app_rdy),
813
        .strip_cnt(req_strip_cnt),
814
        .num_strips(num_strips),
815
        .en(app_en)
816
);
817
 
818
mpmc10_app_cmd_gen ucg1
819
(
820
        .clk(mem_ui_clk),
821
        .state(state),
822
        .cmd(app_cmd)
823
);
824
 
825
mpmc10_app_wdf_wren_gen uwreng1
826
(
827
        .clk(mem_ui_clk),
828
        .state(state),
829
        .rdy(app_wdf_rdy),
830
        .wren(app_wdf_wren)
831
);
832
 
833
mpmc10_app_wdf_end_gen uwendg1
834
(
835
        .clk(mem_ui_clk),
836
        .state(state),
837
        .rdy(app_wdf_rdy),
838
        .strip_cnt(req_strip_cnt),
839
        .num_strips(num_strips),
840
        .wend(app_wdf_end)
841
);
842
 
843
mpmc10_req_strip_cnt ursc1
844
(
845
        .clk(mem_ui_clk),
846
        .state(state),
847
        .wdf_rdy(app_wdf_rdy),
848
        .rdy(app_rdy),
849
        .num_strips(num_strips),
850
        .strip_cnt(req_strip_cnt)
851
);
852
 
853
mpmc10_resp_strip_cnt urespsc1
854
(
855
        .clk(mem_ui_clk),
856
        .state(state),
857
        .valid(rd_data_valid_r),
858
        .num_strips(num_strips),
859
        .strip_cnt(resp_strip_cnt)
860
);
861
 
862
// Reservation status bit
863
mpmc10_resv_bit ursb1
864
(
865
        .clk(mem_ui_clk),
866
        .state(state),
867 7 robfinch
        .wch(fifoo.cid),
868
        .we(fifoo.stb & fifoo.we),
869
        .cr(fifoo.csr & fifoo.we),
870
        .adr(fifoo.adr),
871 5 robfinch
        .resv_ch(resv_ch),
872
        .resv_adr(resv_adr),
873
        .rb(rb1)
874
);
875
 
876
mpmc10_addr_resv_man #(.NAR(NAR)) ursvm1
877
(
878
        .rst(mem_ui_rst),
879
        .clk(mem_ui_clk),
880
        .state(state),
881
        .adr0(32'h0),
882
        .adr1(ch1is.adr),
883
        .adr2(ch2is.adr),
884
        .adr3(ch3is.adr),
885
        .adr4(ch4is.adr),
886
        .adr5(32'h0),
887
        .adr6(ch6is.adr),
888
        .adr7(ch7is.adr),
889
        .sr0(1'b0),
890
        .sr1(ch1is.csr & ch1is.stb & ~ch1is.we),
891
        .sr2(ch2is.csr & ch2is.stb & ~ch2is.we),
892
        .sr3(ch3is.csr & ch3is.stb & ~ch3is.we),
893
        .sr4(ch4is.csr & ch4is.stb & ~ch4is.we),
894
        .sr5(1'b0),
895
        .sr6(ch6is.csr & ch6is.stb & ~ch6is.we),
896
        .sr7(ch7is.csr & ch7is.stb & ~ch7is.we),
897 7 robfinch
        .wch(fifoo.stb ? fifoo.cid : 4'd15),
898
        .we(fifoo.stb & fifoo.we),
899
        .wadr(fifoo.adr),
900
        .cr(fifoo.csr & fifoo.stb & fifoo.we),
901 5 robfinch
        .resv_ch(resv_ch),
902
        .resv_adr(resv_adr)
903
);
904
 
905
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.