| 1 |
2 |
robfinch |
`timescale 1ns / 1ps
|
| 2 |
|
|
// ============================================================================
|
| 3 |
|
|
// __
|
| 4 |
|
|
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
|
| 5 |
|
|
// \ __ / All rights reserved.
|
| 6 |
|
|
// \/_// robfinch@finitron.ca
|
| 7 |
|
|
// ||
|
| 8 |
|
|
//
|
| 9 |
|
|
// BSD 3-Clause License
|
| 10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
| 11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
| 12 |
|
|
//
|
| 13 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
| 14 |
|
|
// list of conditions and the following disclaimer.
|
| 15 |
|
|
//
|
| 16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
| 17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
| 18 |
|
|
// and/or other materials provided with the distribution.
|
| 19 |
|
|
//
|
| 20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
| 21 |
|
|
// contributors may be used to endorse or promote products derived from
|
| 22 |
|
|
// this software without specific prior written permission.
|
| 23 |
|
|
//
|
| 24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
| 25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
| 26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
| 27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
| 28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
| 29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
| 30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
| 31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
| 32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
| 33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 34 |
|
|
//
|
| 35 |
|
|
// ============================================================================
|
| 36 |
|
|
//
|
| 37 |
|
|
import mpmc8_pkg::*;
|
| 38 |
|
|
|
| 39 |
|
|
module mpmc8_ack_gen(rst, clk, state, ch, cs, adr, cr, wr, to, taghit,
|
| 40 |
|
|
resv_ch, resv_adr, ack, pre_ack);
|
| 41 |
|
|
parameter N = 0;
|
| 42 |
|
|
input rst;
|
| 43 |
|
|
input clk;
|
| 44 |
|
|
input [3:0] state;
|
| 45 |
|
|
input [3:0] ch;
|
| 46 |
|
|
input cs;
|
| 47 |
|
|
input [31:0] adr;
|
| 48 |
|
|
input cr;
|
| 49 |
|
|
input wr;
|
| 50 |
|
|
input to;
|
| 51 |
|
|
input taghit;
|
| 52 |
|
|
input [3:0] resv_ch [0:NAR-1];
|
| 53 |
|
|
input [31:0] resv_adr [0:NAR-1];
|
| 54 |
|
|
output reg ack;
|
| 55 |
|
|
output reg pre_ack;
|
| 56 |
|
|
|
| 57 |
|
|
integer n;
|
| 58 |
|
|
reg [7:0] ack_pipe;
|
| 59 |
|
|
|
| 60 |
|
|
// Setting ack output
|
| 61 |
|
|
// Ack takes place outside of a state so that reads from different read caches
|
| 62 |
|
|
// may occur at the same time.
|
| 63 |
|
|
always_ff @(posedge clk)
|
| 64 |
|
|
if (rst)
|
| 65 |
|
|
ack_pipe <= 'd0;
|
| 66 |
|
|
else begin
|
| 67 |
|
|
ack_pipe <= {ack_pipe[6:0],ack_pipe[0]};
|
| 68 |
|
|
|
| 69 |
|
|
// Reads: the ack doesn't happen until the data's been cached. If there is
|
| 70 |
|
|
// cached data we give an ack right away.
|
| 71 |
|
|
if (taghit)
|
| 72 |
|
|
ack_pipe[0] <= 8'd1;
|
| 73 |
|
|
|
| 74 |
|
|
if (state==IDLE) begin
|
| 75 |
|
|
if (cr) begin
|
| 76 |
|
|
ack_pipe <= 8'hFF;
|
| 77 |
|
|
for (n = 0; n < NAR; n = n + 1)
|
| 78 |
|
|
if ((resv_ch[n]==N) && (resv_adr[n][31:4]==adr[31:4])) begin
|
| 79 |
|
|
ack_pipe <= 'd0;
|
| 80 |
|
|
end
|
| 81 |
|
|
end
|
| 82 |
|
|
end
|
| 83 |
|
|
|
| 84 |
|
|
// Write: an ack can be sent back as soon as the write state is reached..
|
| 85 |
|
|
if ((state==PRESET1 && wr) || to)
|
| 86 |
|
|
if (ch==N)
|
| 87 |
|
|
ack_pipe <= 8'hFF;
|
| 88 |
|
|
|
| 89 |
|
|
// Clear the ack when the circuit is de-selected.
|
| 90 |
|
|
if (!cs)
|
| 91 |
|
|
ack_pipe <= 'd0;
|
| 92 |
|
|
|
| 93 |
|
|
ack <= ack_pipe[7];
|
| 94 |
|
|
pre_ack <= ack_pipe[0];
|
| 95 |
|
|
|
| 96 |
|
|
end
|
| 97 |
|
|
|
| 98 |
|
|
endmodule
|
