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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_addr_resv_man(rst, clk, state,
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cs1, ack1, we1, adr1, sr1, cr1, ch1_taghit,
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cs7, ack7, we7, adr7, sr7, cr7, ch7_taghit,
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resv_ch, resv_adr);
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input rst;
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input clk;
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input [3:0] state;
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input cs1;
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input ack1;
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input we1;
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input [31:0] adr1;
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input sr1;
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input cr1;
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input ch1_taghit;
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input cs7;
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input ack7;
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input we7;
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input [31:0] adr7;
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input sr7;
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input cr7;
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input ch7_taghit;
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output reg [3:0] resv_ch [0:NAR-1];
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output reg [31:0] resv_adr [0:NAR-1];
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reg [19:0] resv_to_cnt;
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reg toggle, toggle_sr;
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// For address reservation below
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reg [7:0] match;
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always @(posedge clk)
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if (rst)
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match <= 8'h00;
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else begin
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if (match >= NAR)
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match <= 8'h00;
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else
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match <= match + 8'd1;
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end
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// Managing address reservations
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integer n7;
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always_ff @(posedge clk)
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if (rst) begin
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resv_to_cnt <= 20'd0;
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toggle <= FALSE;
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toggle_sr <= FALSE;
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for (n7 = 0; n7 < NAR; n7 = n7 + 1)
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resv_ch[n7] <= 4'hF;
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end
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else begin
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resv_to_cnt <= resv_to_cnt + 20'd1;
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if (sr1 & sr7) begin
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if (toggle_sr) begin
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reserve_adr(4'h1,adr1);
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toggle_sr <= 1'b0;
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end
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else begin
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reserve_adr(4'h7,adr7);
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toggle_sr <= 1'b1;
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end
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end
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else begin
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if (sr1)
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reserve_adr(4'h1,adr1);
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if (sr7)
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reserve_adr(4'h7,adr7);
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end
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if (state==IDLE) begin
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if (cs1 & we1 & ~ack1) begin
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toggle <= 1'b1;
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if (cr1) begin
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for (n7 = 0; n7 < NAR; n7 = n7 + 1)
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if ((resv_ch[n7]==4'd1) && (resv_adr[n7][31:4]==adr1[31:4]))
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resv_ch[n7] <= 4'hF;
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end
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end
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else if (cs7 & we7 & ~ack7) begin
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toggle <= 1'b1;
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if (cr7) begin
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for (n7 = 0; n7 < NAR; n7 = n7 + 1)
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if ((resv_ch[n7]==4'd7) && (resv_adr[n7][31:4]==adr7[31:4]))
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resv_ch[n7] <= 4'hF;
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end
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end
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else if (!we1 & cs1 & ~ch1_taghit & (cs7 ? toggle : 1'b1))
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toggle <= 1'b0;
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else if (!we7 & cs7 & ~ch7_taghit)
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toggle <= 1'b1;
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end
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end
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integer empty_resv;
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function resv_held;
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input [3:0] ch;
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input [31:0] adr;
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integer n8;
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begin
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resv_held = FALSE;
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for (n8 = 0; n8 < NAR; n8 = n8 + 1)
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if (resv_ch[n8]==ch && resv_adr[n8]==adr)
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resv_held = TRUE;
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end
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endfunction
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// Find an empty reservation bucket
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integer n9;
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always_comb
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begin
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empty_resv <= -1;
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for (n9 = 0; n9 < NAR; n9 = n9 + 1)
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if (resv_ch[n9]==4'hF)
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empty_resv <= n9;
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end
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// Two reservation buckets are allowed for. There are two (or more) CPU's in the
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// system and as long as they are not trying to control the same resource (the
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// same semaphore) then they should be able to set a reservation. Ideally there
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// could be more reservation buckets available, but it starts to be a lot of
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// hardware.
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task reserve_adr;
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input [3:0] ch;
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input [31:0] adr;
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begin
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// Ignore an attempt to reserve an address that's already reserved. The LWAR
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// instruction is usually called in a loop and we don't want it to use up
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// all address reservations.
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if (!resv_held(ch,adr)) begin
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if (empty_resv >= 0) begin
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resv_ch[empty_resv] <= ch;
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resv_adr[empty_resv] <= adr;
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end
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// Here there were no free reservation buckets, so toss one of the
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// old reservations out.
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else begin
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resv_ch[match] <= ch;
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resv_adr[match] <= adr;
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end
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end
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end
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endtask
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endmodule
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