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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_addr_select(rst, clk, state, ch,
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we0, we1, we2, we3, we4, we5, we6, we7,
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adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7,
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adr);
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parameter S0 = 3'd7;
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parameter S1 = 3'd1;
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parameter S2 = 3'd0;
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parameter S3 = 3'd0;
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parameter S4 = 3'd0;
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parameter S5 = 3'd3;
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parameter S6 = 3'd0;
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parameter S7 = 3'd3;
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input rst;
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input clk;
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input [3:0] state;
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input [3:0] ch;
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input we0;
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input we1;
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input we2;
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input we3;
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input we4;
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input we5;
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input we6;
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input we7;
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input [31:0] adr0;
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input [31:0] adr1;
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input [31:0] adr2;
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input [31:0] adr3;
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input [31:0] adr4;
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input [31:0] adr5;
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input [31:0] adr6;
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input [31:0] adr7;
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output reg [31:0] adr;
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// Select the address input
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reg [31:0] adrx;
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always_ff @(posedge clk)
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if (state==IDLE) begin
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case(ch)
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3'd0: if (we0)
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adrx <= {adr0[AMSB:4],4'h0};
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else
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case(S0)
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3'd0: adrx <= {adr0[AMSB:4],4'h0};
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3'd1: adrx <= {adr0[AMSB:5],5'h0};
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3'd3: adrx <= {adr0[AMSB:6],6'h0};
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3'd7: adrx <= {adr0[AMSB:7],7'h0};
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default: adrx <= {adr0[AMSB:7],7'h0};
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endcase
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3'd1: if (we1)
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adrx <= {adr1[AMSB:4],4'h0};
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else
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case(S1)
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3'd0: adrx <= {adr1[AMSB:4],4'h0};
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3'd1: adrx <= {adr1[AMSB:5],5'h0};
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3'd3: adrx <= {adr1[AMSB:6],6'h0};
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3'd7: adrx <= {adr1[AMSB:7],7'h0};
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default: adrx <= {adr1[AMSB:5],5'h0};
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endcase
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3'd2: if (we2)
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adrx <= {adr2[AMSB:4],4'h0};
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else
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case(S2)
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3'd0: adrx <= {adr2[AMSB:4],4'h0};
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3'd1: adrx <= {adr2[AMSB:5],5'h0};
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3'd3: adrx <= {adr2[AMSB:6],6'h0};
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3'd7: adrx <= {adr2[AMSB:7],7'h0};
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default: adrx <= {adr2[AMSB:4],4'h0};
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endcase
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3'd3: if (we3)
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adrx <= {adr3[AMSB:4],4'h0};
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else
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case(S3)
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3'd0: adrx <= {adr3[AMSB:4],4'h0};
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3'd1: adrx <= {adr3[AMSB:5],5'h0};
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3'd3: adrx <= {adr3[AMSB:6],6'h0};
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3'd7: adrx <= {adr3[AMSB:7],7'h0};
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default: adrx <= {adr3[AMSB:4],4'h0};
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endcase
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3'd4: if (we4)
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adrx <= {adr4[AMSB:4],4'h0};
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else
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case(S4)
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3'd0: adrx <= {adr4[AMSB:4],4'h0};
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3'd1: adrx <= {adr4[AMSB:5],5'h0};
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3'd3: adrx <= {adr4[AMSB:6],6'h0};
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3'd7: adrx <= {adr4[AMSB:7],7'h0};
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default: adrx <= {adr4[AMSB:4],4'h0};
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endcase
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3'd5: if (we5)
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adrx <= {adr5[AMSB:6],6'h0};
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else
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case(S5)
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3'd0: adrx <= {adr5[AMSB:4],4'h0};
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3'd1: adrx <= {adr5[AMSB:5],5'h0};
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3'd3: adrx <= {adr5[AMSB:6],6'h0};
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3'd7: adrx <= {adr5[AMSB:7],7'h0};
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default: adrx <= {adr5[AMSB:6],6'h0};
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endcase
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3'd6: if (we6)
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adrx <= {adr6[AMSB:4],4'h0};
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else
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case(S6)
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3'd0: adrx <= {adr6[AMSB:4],4'h0};
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3'd1: adrx <= {adr6[AMSB:5],5'h0};
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3'd3: adrx <= {adr6[AMSB:6],6'h0};
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3'd7: adrx <= {adr6[AMSB:7],7'h0};
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default: adrx <= {adr6[AMSB:4],4'h0};
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endcase
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3'd7: if (we7)
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adrx <= {adr7[AMSB:4],4'h0};
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else
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case(S7)
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3'd0: adrx <= {adr7[AMSB:4],4'h0};
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3'd1: adrx <= {adr7[AMSB:5],5'h0};
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3'd3: adrx <= {adr7[AMSB:6],6'h0};
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3'd7: adrx <= {adr7[AMSB:7],7'h0};
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default: adrx <= {adr7[AMSB:6],6'h0};
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endcase
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default: adrx <= 29'h1FFFFFF0;
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endcase
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end
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always_ff @(posedge clk)
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if (rst)
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adr <= 32'h1FFFFFF0;
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else if (state==PRESET1)
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adr <= adrx;
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endmodule
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