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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_ch_prioritize(clk, state,
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cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7,
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we0, we1, we2, we3, we4, we5, we6, we7,
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ch0_taghit, ch1_taghit, ch2_taghit, ch3_taghit,
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ch4_taghit, ch5_taghit, ch6_taghit, ch7_taghit,
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ch);
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input clk;
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input [3:0] state;
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input cs0;
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input cs1;
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input cs2;
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input cs3;
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input cs4;
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input cs5;
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input cs6;
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input cs7;
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input we0;
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input we1;
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input we2;
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input we3;
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input we4;
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input we5;
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input we6;
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input we7;
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input ch0_taghit;
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input ch1_taghit;
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input ch2_taghit;
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input ch3_taghit;
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input ch4_taghit;
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input ch5_taghit;
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input ch6_taghit;
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input ch7_taghit;
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output reg [3:0] ch;
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// This counter used to periodically reverse channel priorities to help ensure
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// that a particular channel isn't permanently blocked by other higher priority
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// ones.
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reg [5:0] elevate_cnt = 'd0;
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reg elevate = 1'b0;
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always_ff @(posedge clk)
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if (state==PRESET1) begin
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elevate_cnt <= elevate_cnt + 6'd1;
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elevate <= elevate_cnt == 6'd63;
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end
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// Select the channel
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// This prioritizes the channel during the IDLE state.
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// During an elevate cycle the channel priorities are reversed.
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always_ff @(posedge clk)
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begin
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if (elevate) begin
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if (cs7 & we7)
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ch <= 4'd7;
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else if (cs6 & we6)
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ch <= 4'd6;
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else if (cs5 & we5)
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ch <= 4'd5;
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else if (cs4 & we4)
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ch <= 4'd4;
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else if (cs3 & we3)
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ch <= 4'd3;
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else if (cs2 & we2)
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ch <= 4'd2;
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else if (cs1 & we1)
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ch <= 4'd1;
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else if (cs0 & we0)
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ch <= 4'd0;
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else if (cs7 & ~ch7_taghit)
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ch <= 4'd7;
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else if (cs6 & ~ch6_taghit)
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ch <= 4'd6;
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else if (cs5 & ~ch5_taghit)
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ch <= 4'd5;
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else if (cs4 & ~ch4_taghit)
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ch <= 4'd4;
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else if (cs3 & ~ch3_taghit)
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ch <= 4'd3;
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else if (cs2 & ~ch2_taghit)
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ch <= 4'd2;
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else if (cs1 & ~ch1_taghit)
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ch <= 4'd1;
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else if (cs0 & ~ch0_taghit)
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ch <= 4'd0;
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else
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ch <= 4'hF;
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end
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// Channel 0 read or write takes precedence
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else if (cs0 & we0)
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ch <= 4'd0;
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else if (cs0 & ~ch0_taghit)
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ch <= 4'd0;
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else if (cs1 & we1)
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ch <= 4'd1;
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else if (cs2 & we2)
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ch <= 4'd2;
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else if (cs3 & we3)
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ch <= 4'd3;
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else if (cs4 & we4)
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ch <= 4'd4;
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else if (cs6 & we6)
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ch <= 4'd6;
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else if (cs7 & we7)
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ch <= 4'd7;
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// Reads, writes detected above
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else if (cs1 & ~ch1_taghit)
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ch <= 4'd1;
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else if (cs2 & ~ch2_taghit)
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ch <= 4'd2;
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else if (cs3 & ~ch3_taghit)
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ch <= 4'd3;
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else if (cs4 & ~ch4_taghit)
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ch <= 4'd4;
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else if (cs5 & ~ch5_taghit)
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ch <= 4'd5;
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else if (cs6 & ~ch6_taghit)
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ch <= 4'd6;
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else if (cs7 & ~ch7_taghit)
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ch <= 4'd7;
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// Nothing selected
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else
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ch <= 4'hF;
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end
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endmodule
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