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[/] [mpmc8/] [trunk/] [rtl/] [mpmc8_data_output.sv] - Blame information for rev 2

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1 2 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_data_output(
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        clk0, cs0, adr0, ch0_rdat, dato0,
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        clk1, cs1, adr1, ch1_rdat, dato1,
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        clk2, cs2, adr2, ch2_rdat, dato2,
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        clk3, cs3, adr3, ch3_rdat, dato3,
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        clk4, cs4, adr4, ch4_rdat, dato4,
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        clk5, cs5, adr5, ch5_rdat, dato5,
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        clk6, cs6, adr6, ch6_rdat, dato6,
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        clk7, cs7, adr7, ch7_rdat, dato7
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);
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parameter C0W = 128;
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parameter C1W = 128;
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parameter C2W = 32;
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parameter C3W = 16;
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parameter C4W = 128;
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parameter C5W = 64;
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parameter C6W = 128;
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parameter C7R = 16;
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input clk0;
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input clk1;
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input clk2;
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input clk3;
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input clk4;
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input clk5;
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input clk6;
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input clk7;
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input cs0;
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input cs1;
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input cs2;
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input cs3;
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input cs4;
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input cs5;
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input cs6;
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input cs7;
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input [31:0] adr0;
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input [31:0] adr1;
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input [31:0] adr2;
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input [31:0] adr3;
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input [31:0] adr4;
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input [31:0] adr5;
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input [31:0] adr6;
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input [31:0] adr7;
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input [127:0] ch0_rdat;
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input [127:0] ch1_rdat;
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input [127:0] ch2_rdat;
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input [127:0] ch3_rdat;
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input [127:0] ch4_rdat;
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input [127:0] ch5_rdat;
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input [127:0] ch6_rdat;
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input [127:0] ch7_rdat;
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output reg [127:0] dato0;
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output reg [127:0] dato1;
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output reg [127:0] dato2;
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output reg [127:0] dato3;
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output reg [127:0] dato4;
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output reg [127:0] dato5;
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output reg [127:0] dato6;
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output reg [127:0] dato7;
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reg [127:0] ch0_rdatr;
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reg [127:0] ch1_rdatr;
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reg [127:0] ch2_rdatr;
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reg [127:0] ch3_rdatr;
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reg [127:0] ch4_rdatr;
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reg [127:0] ch5_rdatr;
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reg [127:0] ch6_rdatr;
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reg [127:0] ch7_rdatr;
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// Setting output data. Force output data to zero when not selected to allow
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// wire-oring the data.
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always_ff @(posedge clk0)
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`ifdef RED_SCREEN
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if (cs0) begin
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        if (C0W==128)
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                dato0 <= 128'h7C007C007C007C007C007C007C007C00;
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        else if (C0W==64)
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                dato0 <= 64'h7C007C007C007C00;
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        else if (C0W==32)
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                dato0 <= 32'h7C007C00;
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        else if (C0W==16)
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                dato0 <= 16'h7C00;
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        else
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                dato0 <= 8'hE0;
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end
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else
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        dato0 <= {C0W{1'b0}};
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`else
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        tDato(C0W,cs0,adr0[3:0],ch0_rdatr,dato0);
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`endif
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// Register data outputs back onto their domain.
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always_ff @(posedge clk1)
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        ch1_rdatr <= ch1_rdat;
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always_ff @(posedge clk2)
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        ch2_rdatr <= ch2_rdat;
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always_ff @(posedge clk3)
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        ch3_rdatr <= ch3_rdat;
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always_ff @(posedge clk4)
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        ch4_rdatr <= ch4_rdat;
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always_ff @(posedge clk5)
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        ch5_rdatr <= ch5_rdat;
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always_ff @(posedge clk6)
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        ch6_rdatr <= ch6_rdat;
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always_ff @(posedge clk7)
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        ch7_rdatr <= ch7_rdat;
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always_ff @(posedge clk0)
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        ch0_rdatr <= ch0_rdat;
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always_ff @(posedge clk1)
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        tDato(C1W,cs1,adr1[3:0],ch1_rdatr,dato1);
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always_ff @(posedge clk2)
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        tDato(C2W,cs2,adr2[3:0],ch2_rdatr,dato2);
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always_ff @(posedge clk3)
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        tDato(C3W,cs3,adr3[3:0],ch3_rdatr,dato3);
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always_ff @(posedge clk4)
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        tDato(C4W,cs4,adr4[3:0],ch4_rdatr,dato4);
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always_ff @(posedge clk5)
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        tDato(C5W,cs5,adr5[3:0],ch5_rdatr,dato5);
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always_ff @(posedge clk6)
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        tDato(C6W,cs6,adr6[3:0],ch6_rdatr,dato6);
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always_ff @(posedge clk7)
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        tDato(C7R,cs7,adr7[3:0],ch7_rdatr,dato7);
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task tDato;
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input [7:0] widi;
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input csi;
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input [3:0] adri;
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input [127:0] dati;
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output [127:0] dato;
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begin
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if (csi) begin
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        if (widi==8'd128)
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                dato <= dati;
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        else if (widi==8'd64)
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                dato <= dati >> {adri[3],6'h0};
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        else if (widi==8'd32)
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                dato <= dati >> {adri[3:2],5'h0};
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        else if (widi==8'd16)
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                dato <= dati >> {adri[3:1],4'h0};
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        else
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                dato <= dati >> {adri[3:0],3'h0};
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end
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else
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        dato <= 'b0;
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end
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endtask
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endmodule

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