| 1 |
2 |
robfinch |
`timescale 1ns / 1ps
|
| 2 |
|
|
// ============================================================================
|
| 3 |
|
|
// __
|
| 4 |
|
|
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
|
| 5 |
|
|
// \ __ / All rights reserved.
|
| 6 |
|
|
// \/_// robfinch@finitron.ca
|
| 7 |
|
|
// ||
|
| 8 |
|
|
//
|
| 9 |
|
|
// BSD 3-Clause License
|
| 10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
| 11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
| 12 |
|
|
//
|
| 13 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
| 14 |
|
|
// list of conditions and the following disclaimer.
|
| 15 |
|
|
//
|
| 16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
| 17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
| 18 |
|
|
// and/or other materials provided with the distribution.
|
| 19 |
|
|
//
|
| 20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
| 21 |
|
|
// contributors may be used to endorse or promote products derived from
|
| 22 |
|
|
// this software without specific prior written permission.
|
| 23 |
|
|
//
|
| 24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
| 25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
| 26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
| 27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
| 28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
| 29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
| 30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
| 31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
| 32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
| 33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 34 |
|
|
//
|
| 35 |
|
|
// ============================================================================
|
| 36 |
|
|
//
|
| 37 |
|
|
import mpmc8_pkg::*;
|
| 38 |
|
|
|
| 39 |
|
|
module mpmc8_data_select(clk, state, ch,
|
| 40 |
|
|
dati0, dati1, dati2, dati3, dati4, dati5, dati6, dati7, dato
|
| 41 |
|
|
);
|
| 42 |
|
|
parameter C0W = 128;
|
| 43 |
|
|
parameter C1W = 128;
|
| 44 |
|
|
parameter C2W = 128;
|
| 45 |
|
|
parameter C3W = 128;
|
| 46 |
|
|
parameter C4W = 128;
|
| 47 |
|
|
parameter C5W = 128;
|
| 48 |
|
|
parameter C6W = 128;
|
| 49 |
|
|
parameter C7W = 128;
|
| 50 |
|
|
input clk;
|
| 51 |
|
|
input [3:0] state;
|
| 52 |
|
|
input [3:0] ch;
|
| 53 |
|
|
input [C0W-1:0] dati0;
|
| 54 |
|
|
input [C1W-1:0] dati1;
|
| 55 |
|
|
input [C2W-1:0] dati2;
|
| 56 |
|
|
input [C3W-1:0] dati3;
|
| 57 |
|
|
input [C4W-1:0] dati4;
|
| 58 |
|
|
input [C5W-1:0] dati5;
|
| 59 |
|
|
input [C6W-1:0] dati6;
|
| 60 |
|
|
input [C7W-1:0] dati7;
|
| 61 |
|
|
output reg [127:0] dato;
|
| 62 |
|
|
|
| 63 |
|
|
// Setting the write data
|
| 64 |
|
|
// Repeat the data across lanes when less than 128-bit.
|
| 65 |
|
|
always_ff @(posedge clk)
|
| 66 |
|
|
if (state==IDLE) begin
|
| 67 |
|
|
case(ch)
|
| 68 |
|
|
4'd0: dato <= {(128/C0W){dati0}};
|
| 69 |
|
|
4'd1: dato <= {(128/C1W){dati1}};
|
| 70 |
|
|
4'd2: dato <= {(128/C2W){dati2}};
|
| 71 |
|
|
4'd3: dato <= {(128/C3W){dati3}};
|
| 72 |
|
|
4'd4: dato <= {(128/C4W){dati4}};
|
| 73 |
|
|
4'd5: dato <= {(128/C4W){dati5}};
|
| 74 |
|
|
4'd6: dato <= {(128/C6W){dati6}};
|
| 75 |
|
|
4'd7: dato <= {(128/C7W){dati7}};
|
| 76 |
|
|
default: dato <= {2{dati7}};
|
| 77 |
|
|
endcase
|
| 78 |
|
|
end
|
| 79 |
|
|
|
| 80 |
|
|
endmodule
|
