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[/] [mpmc8/] [trunk/] [rtl/] [mpmc8_set_write_mask.sv] - Blame information for rev 2

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1 2 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_set_write_mask(clk, state,
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        we0, we1, we2, we3, we4, we5, we6, we7,
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        sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7,
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        adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7,
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        mask0, mask1, mask2, mask3, mask4, mask5, mask6, mask7
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);
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parameter C0W = 128;
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parameter C1W = 128;
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parameter C2W = 128;
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parameter C3W = 128;
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parameter C4W = 128;
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parameter C5W = 128;
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parameter C6W = 128;
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parameter C7W = 128;
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input clk;
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input [3:0] state;
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input we0;
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input we1;
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input we2;
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input we3;
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input we4;
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input we5;
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input we6;
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input we7;
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input [128/C0W-1:0] sel0;
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input [128/C1W-1:0] sel1;
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input [128/C2W-1:0] sel2;
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input [128/C3W-1:0] sel3;
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input [128/C4W-1:0] sel4;
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input [128/C5W-1:0] sel5;
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input [128/C6W-1:0] sel6;
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input [128/C7W-1:0] sel7;
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input [31:0] adr0;
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input [31:0] adr1;
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input [31:0] adr2;
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input [31:0] adr3;
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input [31:0] adr4;
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input [31:0] adr5;
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input [31:0] adr6;
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input [31:0] adr7;
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output reg [15:0] mask0;
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output reg [15:0] mask1;
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output reg [15:0] mask2;
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output reg [15:0] mask3;
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output reg [15:0] mask4;
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output reg [15:0] mask5;
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output reg [15:0] mask6;
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output reg [15:0] mask7;
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always_ff @(posedge clk)
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        tMask(C0W,we0,{15'd0,sel0},adr0[3:0],mask0);
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always_ff @(posedge clk)
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        tMask(C1W,we1,{15'd0,sel1},adr1[3:0],mask1);
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always_ff @(posedge clk)
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        tMask(C2W,we2,{15'd0,sel2},adr2[3:0],mask2);
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always_ff @(posedge clk)
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        tMask(C3W,we3,{15'd0,sel3},adr3[3:0],mask3);
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always_ff @(posedge clk)
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        tMask(C4W,we4,{15'd0,sel4},adr4[3:0],mask4);
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always_ff @(posedge clk)
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        tMask(C5W,we5,{15'd0,sel5},adr5[3:0],mask5);
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always_ff @(posedge clk)
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        tMask(C6W,we6,{15'd0,sel6},adr6[3:0],mask6);
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always_ff @(posedge clk)
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        tMask(C7W,we7,{15'd0,sel7},adr7[3:0],mask7);
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task tMask;
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input [7:0] widi;
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input wei;
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input [15:0] seli;
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input [3:0] adri;
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output [15:0] masko;
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begin
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if (state==IDLE)
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        if (wei) begin
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                if (widi==8'd128)
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                        masko <= ~seli;
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                else if (widi==8'd64)
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                        masko <= ~({8'd0,seli[7:0]} << {adri[3],3'b0});
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                else if (widi==8'd32)
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                        masko <= ~({12'd0,seli[3:0]} << {adri[3:2],2'b0});
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                else if (widi==8'd16)
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                        masko <= ~({14'd0,seli[1:0]} << {adri[3:1],1'b0});
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                else
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                        masko <= ~({15'd0,seli[0]} << adri[3:0]);
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        end
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        else
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                masko <= 16'h0000;      // read all bytes
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end
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endtask
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endmodule

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