1 |
2 |
robfinch |
`timescale 1ns / 1ps
|
2 |
|
|
// ============================================================================
|
3 |
|
|
// __
|
4 |
|
|
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
|
5 |
|
|
// \ __ / All rights reserved.
|
6 |
|
|
// \/_// robfinch@finitron.ca
|
7 |
|
|
// ||
|
8 |
|
|
//
|
9 |
|
|
// BSD 3-Clause License
|
10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
12 |
|
|
//
|
13 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
14 |
|
|
// list of conditions and the following disclaimer.
|
15 |
|
|
//
|
16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
18 |
|
|
// and/or other materials provided with the distribution.
|
19 |
|
|
//
|
20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
21 |
|
|
// contributors may be used to endorse or promote products derived from
|
22 |
|
|
// this software without specific prior written permission.
|
23 |
|
|
//
|
24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
34 |
|
|
//
|
35 |
|
|
// ============================================================================
|
36 |
|
|
//
|
37 |
|
|
import mpmc8_pkg::*;
|
38 |
|
|
|
39 |
|
|
module mpmc8_set_write_mask(clk, state,
|
40 |
|
|
we0, we1, we2, we3, we4, we5, we6, we7,
|
41 |
|
|
sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7,
|
42 |
|
|
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7,
|
43 |
|
|
mask0, mask1, mask2, mask3, mask4, mask5, mask6, mask7
|
44 |
|
|
);
|
45 |
|
|
parameter C0W = 128;
|
46 |
|
|
parameter C1W = 128;
|
47 |
|
|
parameter C2W = 128;
|
48 |
|
|
parameter C3W = 128;
|
49 |
|
|
parameter C4W = 128;
|
50 |
|
|
parameter C5W = 128;
|
51 |
|
|
parameter C6W = 128;
|
52 |
|
|
parameter C7W = 128;
|
53 |
|
|
input clk;
|
54 |
|
|
input [3:0] state;
|
55 |
|
|
input we0;
|
56 |
|
|
input we1;
|
57 |
|
|
input we2;
|
58 |
|
|
input we3;
|
59 |
|
|
input we4;
|
60 |
|
|
input we5;
|
61 |
|
|
input we6;
|
62 |
|
|
input we7;
|
63 |
|
|
input [128/C0W-1:0] sel0;
|
64 |
|
|
input [128/C1W-1:0] sel1;
|
65 |
|
|
input [128/C2W-1:0] sel2;
|
66 |
|
|
input [128/C3W-1:0] sel3;
|
67 |
|
|
input [128/C4W-1:0] sel4;
|
68 |
|
|
input [128/C5W-1:0] sel5;
|
69 |
|
|
input [128/C6W-1:0] sel6;
|
70 |
|
|
input [128/C7W-1:0] sel7;
|
71 |
|
|
input [31:0] adr0;
|
72 |
|
|
input [31:0] adr1;
|
73 |
|
|
input [31:0] adr2;
|
74 |
|
|
input [31:0] adr3;
|
75 |
|
|
input [31:0] adr4;
|
76 |
|
|
input [31:0] adr5;
|
77 |
|
|
input [31:0] adr6;
|
78 |
|
|
input [31:0] adr7;
|
79 |
|
|
output reg [15:0] mask0;
|
80 |
|
|
output reg [15:0] mask1;
|
81 |
|
|
output reg [15:0] mask2;
|
82 |
|
|
output reg [15:0] mask3;
|
83 |
|
|
output reg [15:0] mask4;
|
84 |
|
|
output reg [15:0] mask5;
|
85 |
|
|
output reg [15:0] mask6;
|
86 |
|
|
output reg [15:0] mask7;
|
87 |
|
|
|
88 |
|
|
always_ff @(posedge clk)
|
89 |
|
|
tMask(C0W,we0,{15'd0,sel0},adr0[3:0],mask0);
|
90 |
|
|
always_ff @(posedge clk)
|
91 |
|
|
tMask(C1W,we1,{15'd0,sel1},adr1[3:0],mask1);
|
92 |
|
|
always_ff @(posedge clk)
|
93 |
|
|
tMask(C2W,we2,{15'd0,sel2},adr2[3:0],mask2);
|
94 |
|
|
always_ff @(posedge clk)
|
95 |
|
|
tMask(C3W,we3,{15'd0,sel3},adr3[3:0],mask3);
|
96 |
|
|
always_ff @(posedge clk)
|
97 |
|
|
tMask(C4W,we4,{15'd0,sel4},adr4[3:0],mask4);
|
98 |
|
|
always_ff @(posedge clk)
|
99 |
|
|
tMask(C5W,we5,{15'd0,sel5},adr5[3:0],mask5);
|
100 |
|
|
always_ff @(posedge clk)
|
101 |
|
|
tMask(C6W,we6,{15'd0,sel6},adr6[3:0],mask6);
|
102 |
|
|
always_ff @(posedge clk)
|
103 |
|
|
tMask(C7W,we7,{15'd0,sel7},adr7[3:0],mask7);
|
104 |
|
|
|
105 |
|
|
task tMask;
|
106 |
|
|
input [7:0] widi;
|
107 |
|
|
input wei;
|
108 |
|
|
input [15:0] seli;
|
109 |
|
|
input [3:0] adri;
|
110 |
|
|
output [15:0] masko;
|
111 |
|
|
begin
|
112 |
|
|
if (state==IDLE)
|
113 |
|
|
if (wei) begin
|
114 |
|
|
if (widi==8'd128)
|
115 |
|
|
masko <= ~seli;
|
116 |
|
|
else if (widi==8'd64)
|
117 |
|
|
masko <= ~({8'd0,seli[7:0]} << {adri[3],3'b0});
|
118 |
|
|
else if (widi==8'd32)
|
119 |
|
|
masko <= ~({12'd0,seli[3:0]} << {adri[3:2],2'b0});
|
120 |
|
|
else if (widi==8'd16)
|
121 |
|
|
masko <= ~({14'd0,seli[1:0]} << {adri[3:1],1'b0});
|
122 |
|
|
else
|
123 |
|
|
masko <= ~({15'd0,seli[0]} << adri[3:0]);
|
124 |
|
|
end
|
125 |
|
|
else
|
126 |
|
|
masko <= 16'h0000; // read all bytes
|
127 |
|
|
end
|
128 |
|
|
endtask
|
129 |
|
|
|
130 |
|
|
endmodule
|