1 |
2 |
robfinch |
`timescale 1ns / 1ps
|
2 |
|
|
// ============================================================================
|
3 |
|
|
// __
|
4 |
|
|
// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
|
5 |
|
|
// \ __ / All rights reserved.
|
6 |
|
|
// \/_// robfinch@finitron.ca
|
7 |
|
|
// ||
|
8 |
|
|
//
|
9 |
|
|
// BSD 3-Clause License
|
10 |
|
|
// Redistribution and use in source and binary forms, with or without
|
11 |
|
|
// modification, are permitted provided that the following conditions are met:
|
12 |
|
|
//
|
13 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
14 |
|
|
// list of conditions and the following disclaimer.
|
15 |
|
|
//
|
16 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
17 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
18 |
|
|
// and/or other materials provided with the distribution.
|
19 |
|
|
//
|
20 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
21 |
|
|
// contributors may be used to endorse or promote products derived from
|
22 |
|
|
// this software without specific prior written permission.
|
23 |
|
|
//
|
24 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
25 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
26 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
27 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
28 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
29 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
30 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
31 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
32 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
33 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
34 |
|
|
//
|
35 |
|
|
// ============================================================================
|
36 |
|
|
//
|
37 |
|
|
import mpmc8_pkg::*;
|
38 |
|
|
|
39 |
|
|
module mpmc8_sync(clk, cs_i, we_i, sel_i, adr_i, dati_i, sr_i, cr_i,
|
40 |
|
|
cs_o, we_o, sel_o, adr_o, dati_o, sr_o, cr_o
|
41 |
|
|
);
|
42 |
|
|
parameter W=128;
|
43 |
|
|
input clk;
|
44 |
|
|
input cs_i;
|
45 |
|
|
input we_i;
|
46 |
|
|
input [W/8-1:0] sel_i;
|
47 |
|
|
input [31:0] adr_i;
|
48 |
|
|
input [W-1:0] dati_i;
|
49 |
|
|
input sr_i;
|
50 |
|
|
input cr_i;
|
51 |
|
|
output reg cs_o;
|
52 |
|
|
output reg we_o;
|
53 |
|
|
output reg [W/8-1:0] sel_o;
|
54 |
|
|
output reg [31:0] adr_o;
|
55 |
|
|
output reg [W-1:0] dati_o;
|
56 |
|
|
output reg sr_o;
|
57 |
|
|
output reg cr_o;
|
58 |
|
|
|
59 |
|
|
always_ff @(posedge clk)
|
60 |
|
|
begin
|
61 |
|
|
cs_o <= cs_i;
|
62 |
|
|
we_o <= we_i;
|
63 |
|
|
sel_o <= sel_i;
|
64 |
|
|
adr_o <= adr_i;
|
65 |
|
|
dati_o <= dati_i;
|
66 |
|
|
sr_o <= sr_i;
|
67 |
|
|
cr_o <= cr_i;
|
68 |
|
|
end
|
69 |
|
|
|
70 |
|
|
endmodule
|