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[/] [mpmc8/] [trunk/] [rtl/] [mpmc9.sv] - Blame information for rev 4

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1 4 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
9
// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
11
// modification, are permitted provided that the following conditions are met:
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//
13
// 1. Redistributions of source code must retain the above copyright notice, this
14
//    list of conditions and the following disclaimer.
15
//
16
// 2. Redistributions in binary form must reproduce the above copyright notice,
17
//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
19
//
20
// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
24
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
//
35
// 5000 LUTs, 28 BRAM
36
// ============================================================================
37
//
38
//`define RED_SCREEN    1'b1
39
import mpmc9_pkg::*;
40
 
41
module mpmc9(
42
rst_i, clk100MHz,
43
clk0, cyc0, stb0, ack0, we0, sel0, adr0, dati0, dato0,
44
clk1, cs1, cyc1, stb1, ack1, we1, sel1, adr1, dati1, dato1, sr1, cr1, rb1,
45
clk2, cyc2, stb2, ack2, we2, sel2, adr2, dati2, dato2,
46
clk3, cyc3, stb3, ack3, we3, sel3, adr3, dati3, dato3,
47
clk4, cyc4, stb4, ack4, we4, sel4, adr4, dati4, dato4,
48
clk5, cyc5, stb5, ack5, sel5, adr5, dato5, spriteno,
49
clk6, cyc6, stb6, ack6, we6, sel6, adr6, dati6, dato6,
50
clk7, cs7, cyc7, stb7, ack7, we7, sel7, adr7, dati7, dato7, sr7, cr7, rb7,
51
mem_ui_rst, mem_ui_clk, calib_complete,
52
rstn, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, app_wdf_mask, app_wdf_wren,
53
app_rd_data, app_rd_data_valid, app_rd_data_end, app_rdy, app_wdf_rdy,
54
ch, state
55
);
56
input rst_i;
57
input clk100MHz;
58
 
59
// Channel 0 is reserved for bitmapped graphics display.
60
//
61
parameter C0W = 128;    // Channel zero width
62
parameter STREAM0 = TRUE;
63
parameter STRIPS0 = 6'd63;
64
input clk0;
65
input cyc0;
66
input stb0;
67
output ack0;
68
input [C0W/8-1:0] sel0;
69
input we0;
70
input [31:0] adr0;
71
input [C0W-1:0] dati0;
72
output reg [C0W-1:0] dato0;
73
reg [C0W-1:0] dato0n;
74
 
75
// Channel 1 is reserved for cpu1
76
parameter C1W = 128;
77
parameter STREAM1 = FALSE;
78
parameter STRIPS1 = 6'd0;
79
input clk1;
80
input cs1;
81
input cyc1;
82
input stb1;
83
output ack1;
84
input we1;
85
input [C1W/8-1:0] sel1;
86
input [31:0] adr1;
87
input [C1W-1:0] dati1;
88
output reg [C1W-1:0] dato1;
89
input sr1;
90
input cr1;
91
output rb1;
92
 
93
// Channel 2 is reserved for the ethernet controller
94
parameter C2W = 32;
95
parameter STREAM2 = FALSE;
96
parameter STRIPS2 = 6'd31;
97
input clk2;
98
input cyc2;
99
input stb2;
100
output ack2;
101
input we2;
102
input [C2W/8-1:0] sel2;
103
input [31:0] adr2;
104
input [C2W-1:0] dati2;
105
output reg [C2W-1:0] dato2;
106
 
107
// Channel 3 is reserved for the audio controller
108
parameter C3W = 16;
109
parameter STREAM3 = TRUE;
110
parameter STRIPS3 = 6'd63;
111
input clk3;
112
input cyc3;
113
input stb3;
114
output ack3;
115
input we3;
116
input [C3W/8-1:0] sel3;
117
input [31:0] adr3;
118
input [C3W-1:0] dati3;
119
output reg [C3W-1:0] dato3;
120
 
121
// Channel 4 is reserved for the graphics controller
122
parameter C4W = 128;
123
parameter STREAM4 = FALSE;
124
parameter STRIPS4 = 6'd0;
125
input clk4;
126
input cyc4;
127
input stb4;
128
output ack4;
129
input we4;
130
input [C4W/8-1:0] sel4;
131
input [31:0] adr4;
132
input [C4W-1:0] dati4;
133
output reg [C4W-1:0] dato4;
134
 
135
// Channel 5 is reserved for sprite DMA, which is read-only
136
parameter C5W = 64;
137
parameter STREAM5 = TRUE;
138
parameter STRIPS5 = 6'd15;
139
input clk5;
140
input cyc5;
141
input stb5;
142
output ack5;
143
input [C5W/8-1:0] sel5;
144
input [5:0] spriteno;
145
input [31:0] adr5;
146
output reg [C5W-1:0] dato5;
147
 
148
// Channel 6 is reserved for the SD/MMC controller
149
parameter C6W = 128;
150
parameter STREAM6 = FALSE;
151
parameter STRIPS6 = 6'd63;
152
input clk6;
153
input cyc6;
154
input stb6;
155
output ack6;
156
input we6;
157
input [C6W/8-1:0] sel6;
158
input [31:0] adr6;
159
input [C6W-1:0] dati6;
160
output reg [C6W-1:0] dato6;
161
 
162
// Channel 7 is reserved for the cpu
163
parameter C7W = 16;
164
parameter C7R = 16;
165
parameter STREAM7 = FALSE;
166
parameter STRIPS7 = 6'd3;
167
input clk7;
168
input cs7;
169
input cyc7;
170
input stb7;
171
output ack7;
172
input we7;
173
input [C7W/8-1:0] sel7;
174
input [31:0] adr7;
175
input [C7W-1:0] dati7;
176
output reg [C7R-1:0] dato7;
177
input sr7;
178
input cr7;
179
output rb7;
180
 
181
// MIG interface signals
182
input mem_ui_rst;
183
input mem_ui_clk;
184
input calib_complete;
185
output rstn;
186
output [AMSB:0] app_addr;
187
output [2:0] app_cmd;
188
output reg app_en;
189
output reg [127:0] app_wdf_data;
190
output [15:0] app_wdf_mask;
191
output app_wdf_end;
192
output app_wdf_wren;
193
input [127:0] app_rd_data;
194
input app_rd_data_valid;
195
input app_rd_data_end;
196
input app_rdy;
197
input app_wdf_rdy;
198
 
199
// Debugging
200
output reg [3:0] ch;
201
output [3:0] state;
202
 
203
integer n;
204
integer n1;
205
integer n2;
206
 
207
wire [31:0] app_waddr;
208
wire [31:0] adr;
209
wire [127:0] dat128;
210
reg [15:0] wmask;
211
reg [127:0] rmw_data;
212
 
213
reg [3:0] nch;
214
reg [5:0] sreg;
215
reg rstn;
216
reg [5:0] nack_to = 6'd0;
217
reg [5:0] spriteno_r;
218
 
219
wire cs0 = cyc0 && stb0 && adr0[31:29]==3'h0;
220
wire ics1 = cyc1 & stb1 & cs1;
221
wire cs2 = cyc2 && stb2 && adr2[31:29]==3'h0;
222
wire cs3 = cyc3 && stb3 && adr3[31:29]==3'h0;
223
wire cs4 = cyc4 && stb4 && adr4[31:29]==3'h0;
224
wire cs5 = cyc5 && stb5 && adr5[31:29]==3'h0;
225
wire cs6 = cyc6 && stb6 && adr6[31:29]==3'h0;
226
wire ics7 = cyc7 & stb7 & cs7;
227
 
228
reg acki0,acki1,acki2,acki3,acki4,acki5,acki6,acki7;
229
wire do_wr;
230
wire do_wr0;
231
wire do_wr1;
232
wire do_wr2;
233
wire do_wr3;
234
wire do_wr4;
235
wire do_wr5;
236
wire do_wr6;
237
wire do_wr7;
238
 
239
reg [5:0] num_strips;
240
wire [5:0] req_strip_cnt;               // count of requested strips
241
wire [5:0] resp_strip_cnt;              // count of response strips
242
reg [AMSB:0] app_addr;
243
 
244
reg [15:0] refcnt;                              // refreshing not used, its automnatic
245
reg refreq;
246
wire refack;
247
wire [15:0] tocnt;                                      // memory access timeout counter
248
 
249
reg [3:0] resv_ch [0:NAR-1];
250
reg [31:0] resv_adr [0:NAR-1];
251
 
252
// Cross clock domain signals
253
wire cs0xx;
254
wire we0xx;
255
wire [C0W/8-1:0] sel0xx;
256
wire [31:0] adr0xx;
257
wire [C0W-1:0] dati0xx;
258
 
259
wire cs1xx;
260
wire we1xx;
261
wire [15:0] sel1xx;
262
wire [31:0] adr1xx;
263
wire [127:0] dati1xx;
264
wire sr1xx;
265
wire cr1xx;
266
 
267
wire cs2xx;
268
wire we2xx;
269
wire [C2W/8-1:0] sel2xx;
270
wire [31:0] adr2xx;
271
wire [C2W-1:0] dati2xx;
272
 
273
wire cs3xx;
274
wire we3xx;
275
wire [C3W/8-1:0] sel3xx;
276
wire [31:0] adr3xx;
277
wire [C3W-1:0] dati3xx;
278
 
279
wire cs4xx;
280
wire we4xx;
281
wire [C4W/8-1:0] sel4xx;
282
wire [31:0] adr4xx;
283
wire [C4W-1:0] dati4xx;
284
 
285
wire cs5xx;
286
wire we5xx;
287
wire [C5W/8-1:0] sel5xx;
288
wire [31:0] adr5xx;
289
wire [C5W-1:0] dati5xx;
290
wire [5:0] spritenoxx;
291
 
292
wire cs6xx;
293
wire we6xx;
294
wire [C6W/8-1:0] sel6xx;
295
wire [31:0] adr6xx;
296
wire [C6W-1:0] dati6xx;
297
 
298
wire cs7xx;
299
wire we7xx;
300
wire [C7W/8-1:0] sel7xx;
301
wire [31:0] adr7xx;
302
wire [C7W-1:0] dati7xx;
303
wire sr7xx;
304
wire cr7xx;
305
 
306
reg [7:0] to_cnt;
307
 
308
// Terminate the ack signal as soon as the circuit select goes away.
309
assign ack0 = acki0 & cs0;
310
assign ack1 = acki1 & ics1;
311
assign ack2 = acki2 & cs2;
312
assign ack3 = acki3 & cs3;
313
assign ack4 = acki4 & cs4;
314
assign ack5 = acki5 & cs5;
315
assign ack6 = acki6 & cs6;
316
assign ack7 = acki7 & ics7;
317
 
318
wire pre_ack0;
319
wire pre_ack1;
320
wire pre_ack2;
321
wire pre_ack3;
322
wire pre_ack4;
323
wire pre_ack5;
324
wire pre_ack6;
325
wire pre_ack7;
326
 
327
// Used to transition state to IDLE at end of access
328
// We dont transition to idle until a negative edge is seen on ack
329
wire ne_acki0;
330
wire ne_acki1;
331
wire ne_acki2;
332
wire ne_acki3;
333
wire ne_acki4;
334
wire ne_acki5;
335
wire ne_acki6;
336
wire ne_acki7;
337
wire pe_acki0;
338
wire pe_acki1;
339
wire pe_acki2;
340
wire pe_acki3;
341
wire pe_acki4;
342
wire pe_acki5;
343
wire pe_acki6;
344
wire pe_acki7;
345
edge_det ed_acki0 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki0), .pe(pe_acki0), .ne(ne_acki0), .ee());
346
edge_det ed_acki1 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki1), .pe(pe_acki1), .ne(ne_acki1), .ee());
347
edge_det ed_acki2 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki2), .pe(pe_acki2), .ne(ne_acki2), .ee());
348
edge_det ed_acki3 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki3), .pe(pe_acki3), .ne(ne_acki3), .ee());
349
edge_det ed_acki4 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki4), .pe(pe_acki4), .ne(ne_acki4), .ee());
350
edge_det ed_acki5 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki5), .pe(pe_acki5), .ne(ne_acki5), .ee());
351
edge_det ed_acki6 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki6), .pe(pe_acki6), .ne(ne_acki6), .ee());
352
edge_det ed_acki7 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(acki7), .pe(pe_acki7), .ne(ne_acki7), .ee());
353
 
354
wire [127:0] ch0_rdat_c, ch0_rdat_s, ch0_rdat;
355
wire [127:0] ch1_rdat, ch1_rdat_c, ch1_rdat_s;
356
wire [127:0] ch2_rdat, ch2_rdat_c, ch2_rdat_s;
357
wire [127:0] ch3_rdat, ch3_rdat_c, ch3_rdat_s;
358
wire [127:0] ch4_rdat, ch4_rdat_c, ch4_rdat_s;
359
wire [127:0] ch5_rdat, ch5_rdat_c, ch5_rdat_s;
360
wire [127:0] ch6_rdat, ch6_rdat_c, ch6_rdat_s;
361
wire [127:0] ch7_rdat, ch7_rdat_c, ch7_rdat_s;
362
reg [127:0] ch0_rdatr;
363
reg [127:0] ch1_rdatr;
364
reg [127:0] ch2_rdatr;
365
reg [127:0] ch3_rdatr;
366
reg [127:0] ch4_rdatr;
367
reg [127:0] ch5_rdatr;
368
reg [127:0] ch6_rdatr;
369
reg [127:0] ch7_rdatr;
370
wire ch0_hit_c, ch0_hit_s;
371
wire ch1_hit_c, ch1_hit_s;
372
wire ch2_hit_c, ch2_hit_s;
373
wire ch3_hit_c, ch3_hit_s;
374
wire ch4_hit_c, ch4_hit_s;
375
wire ch5_hit_c, ch5_hit_s;
376
wire ch6_hit_c, ch6_hit_s;
377
wire ch7_hit_c, ch7_hit_s;
378
wire ch0_hit, ch1_hit, ch2_hit, ch3_hit;
379
wire ch4_hit, ch5_hit, ch6_hit, ch7_hit;
380
 
381
mpmc9_read_cache rc0 (
382
        .rst(rst_i),
383
        .wclk(mem_ui_clk),
384
        .wr(app_rd_data_valid && !(
385
                (STREAM0 && ch==4'd0) ||
386
                (STREAM1 && ch==4'd1) ||
387
                (STREAM2 && ch==4'd2) ||
388
                (STREAM3 && ch==4'd3) ||
389
                (STREAM4 && ch==4'd4) ||
390
                (STREAM5 && ch==4'd5) ||
391
                (STREAM6 && ch==4'd6) ||
392
                (STREAM7 && ch==4'd7)
393
        )),
394
        .wadr({app_waddr[31:4],4'h0}),
395
        .wdat(app_rd_data),
396
        .inv(state==WRITE_DATA0),
397
        .rclk0(STREAM0 ? 1'b0 : clk0),
398
        .radr0(STREAM0 ? 32'h0 : {adr0xx[31:4],4'h0}),
399
        .rdat0(ch0_rdat_c),
400
        .hit0(ch0_hit_c),
401
        .rclk1(STREAM1 ? 1'b0 : mem_ui_clk),
402
        .radr1(STREAM1 ? 32'h0 : {adr1xx[31:4],4'h0}),
403
        .rdat1(ch1_rdat_c),
404
        .hit1(ch1_hit_c),
405
        .rclk2(STREAM2 ? 1'b0 : mem_ui_clk),
406
        .radr2(STREAM2 ? 32'h0 : {adr2xx[31:4],4'h0}),
407
        .rdat2(ch2_rdat_c),
408
        .hit2(ch2_hit_c),
409
        .rclk3(STREAM3 ? 1'b0 : mem_ui_clk),
410
        .radr3(STREAM3 ? 32'h0 : {adr3xx[31:4],4'h0}),
411
        .rdat3(ch3_rdat_c),
412
        .hit3(ch3_hit_c),
413
        .rclk4(STREAM4 ? 1'b0 : mem_ui_clk),
414
        .radr4(STREAM4 ? 32'h0 : {adr4xx[31:4],4'h0}),
415
        .rdat4(ch4_rdat_c),
416
        .hit4(ch4_hit_c),
417
        .rclk5(STREAM5 ? 1'b0 : mem_ui_clk),
418
        .radr5(STREAM5 ? 32'h0 : {adr5xx[31:4],4'h0}),
419
        .rdat5(ch5_rdat_c),
420
        .hit5(ch5_hit_c),
421
        .rclk6(STREAM6 ? 1'b0 : mem_ui_clk),
422
        .radr6(STREAM6 ? 32'h0 : {adr6xx[31:4],4'h0}),
423
        .rdat6(ch6_rdat_c),
424
        .hit6(ch6_hit_c),
425
        .rclk7(STREAM7 ? 1'b0 : mem_ui_clk),
426
        .radr7(STREAM7 ? 32'h0 : {adr7xx[31:4],4'h0}),
427
        .rdat7(ch7_rdat_c),
428
        .hit7(ch7_hit_c)
429
);
430
 
431
mpmc9_strm_read_cache ustrm0
432
(
433
        .rst(rst_i),
434
        .wclk(mem_ui_clk),
435
        .wr(ch==4'd0 && app_rd_data_valid),
436
        .wadr({app_waddr[31:4],4'h0}),
437
        .wdat(app_rd_data),
438
        .inv(1'b0),
439
        .rclk(mem_ui_clk),
440
        .radr({adr0xx[31:4],4'h0}),
441
        .rdat(ch0_rdat_s),
442
        .hit(ch0_hit_s)
443
);
444
 
445
mpmc9_strm_read_cache ustrm1
446
(
447
        .rst(rst_i),
448
        .wclk(mem_ui_clk),
449
        .wr(ch==4'd1 && app_rd_data_valid),
450
        .wadr({app_waddr[31:4],4'h0}),
451
        .wdat(app_rd_data),
452
        .inv(1'b0),
453
        .rclk(mem_ui_clk),
454
        .radr({adr1xx[31:4],4'h0}),
455
        .rdat(ch1_rdat_s),
456
        .hit(ch1_hit_s)
457
);
458
 
459
mpmc9_strm_read_cache ustrm2
460
(
461
        .rst(rst_i),
462
        .wclk(mem_ui_clk),
463
        .wr(ch==4'd2 && app_rd_data_valid),
464
        .wadr({app_waddr[31:4],4'h0}),
465
        .wdat(app_rd_data),
466
        .inv(1'b0),
467
        .rclk(mem_ui_clk),
468
        .radr({adr2xx[31:4],4'h0}),
469
        .rdat(ch2_rdat_s),
470
        .hit(ch2_hit_s)
471
);
472
 
473
mpmc9_strm_read_cache ustrm3
474
(
475
        .rst(rst_i),
476
        .wclk(mem_ui_clk),
477
        .wr(ch==4'd3 && app_rd_data_valid),
478
        .wadr({app_waddr[31:4],4'h0}),
479
        .wdat(app_rd_data),
480
        .inv(1'b0),
481
        .rclk(mem_ui_clk),
482
        .radr({adr3xx[31:4],4'h0}),
483
        .rdat(ch3_rdat_s),
484
        .hit(ch3_hit_s)
485
);
486
 
487
mpmc9_strm_read_cache ustrm4
488
(
489
        .rst(rst_i),
490
        .wclk(mem_ui_clk),
491
        .wr(ch==4'd4 && app_rd_data_valid),
492
        .wadr({app_waddr[31:4],4'h0}),
493
        .wdat(app_rd_data),
494
        .inv(1'b0),
495
        .rclk(mem_ui_clk),
496
        .radr({adr4xx[31:4],4'h0}),
497
        .rdat(ch4_rdat_s),
498
        .hit(ch4_hit_s)
499
);
500
 
501
mpmc9_spr_read_cache usprrc5
502
(
503
        .rst(rst_i),
504
        .wclk(mem_ui_clk),
505
        .spr_num(spriteno[4:0]),
506
        .wr(ch==4'd5 && app_rd_data_valid),
507
        .wadr({app_waddr[31:4],4'h0}),
508
        .wdat(app_rd_data),
509
        .inv(1'b0),
510
        .rclk(mem_ui_clk),
511
        .radr({adr5xx[31:4],4'h0}),
512
        .rdat(ch5_rdat_s),
513
        .hit(ch5_hit_s)
514
);
515
 
516
mpmc9_strm_read_cache ustrm6
517
(
518
        .rst(rst_i),
519
        .wclk(mem_ui_clk),
520
        .wr(ch==4'd6 && app_rd_data_valid),
521
        .wadr({app_waddr[31:4],4'h0}),
522
        .wdat(app_rd_data),
523
        .inv(1'b0),
524
        .rclk(mem_ui_clk),
525
        .radr({adr6xx[31:4],4'h0}),
526
        .rdat(ch6_rdat_s),
527
        .hit(ch6_hit_s)
528
);
529
 
530
mpmc9_strm_read_cache ustrm7
531
(
532
        .rst(rst_i),
533
        .wclk(mem_ui_clk),
534
        .wr(ch==4'd7 && app_rd_data_valid),
535
        .wadr({app_waddr[31:4],4'h0}),
536
        .wdat(app_rd_data),
537
        .inv(1'b0),
538
        .rclk(mem_ui_clk),
539
        .radr({adr7xx[31:4],4'h0}),
540
        .rdat(ch7_rdat_s),
541
        .hit(ch7_hit_s)
542
);
543
 
544
// These muxes will be reduced to wires.
545
assign ch0_hit = STREAM0 ? ch0_hit_s : ch0_hit_c;
546
assign ch0_rdat = STREAM0 ? ch0_rdat_s : ch0_rdat_c;
547
assign ch1_hit = STREAM1 ? ch1_hit_s : ch1_hit_c;
548
assign ch1_rdat = STREAM1 ? ch1_rdat_s : ch1_rdat_c;
549
assign ch2_hit = STREAM2 ? ch2_hit_s : ch2_hit_c;
550
assign ch2_rdat = STREAM2 ? ch2_rdat_s : ch2_rdat_c;
551
assign ch3_hit = STREAM3 ? ch3_hit_s : ch3_hit_c;
552
assign ch3_rdat = STREAM3 ? ch3_rdat_s : ch3_rdat_c;
553
assign ch4_hit = STREAM4 ? ch4_hit_s : ch4_hit_c;
554
assign ch4_rdat = STREAM4 ? ch4_rdat_s : ch4_rdat_c;
555
assign ch5_hit = STREAM5 ? ch5_hit_s : ch5_hit_c;
556
assign ch5_rdat = STREAM5 ? ch5_rdat_s : ch5_rdat_c;
557
assign ch6_hit = STREAM6 ? ch6_hit_s : ch6_hit_c;
558
assign ch6_rdat = STREAM6 ? ch6_rdat_s : ch6_rdat_c;
559
assign ch7_hit = STREAM7 ? ch7_hit_s : ch7_hit_c;
560
assign ch7_rdat = STREAM7 ? ch7_rdat_s : ch7_rdat_c;
561
 
562
// Register signals onto mem_ui_clk domain
563
mpmc9_sync #(.W(C0W)) usyn0
564
(
565
        .clk(mem_ui_clk),
566
        .cs_i(cs0),
567
        .we_i(we0),
568
        .sel_i(sel0),
569
        .adr_i(adr0),
570
        .dati_i(dati0),
571
        .sr_i(1'b0),
572
        .cr_i(1'b0),
573
        .cs_o(cs0xx),
574
        .we_o(we0xx),
575
        .sel_o(sel0xx),
576
        .adr_o(adr0xx),
577
        .dati_o(dati0xx),
578
        .sr_o(),
579
        .cr_o()
580
);
581
 
582
mpmc9_sync #(.W(C1W)) usyn1
583
(
584
        .clk(mem_ui_clk),
585
        .cs_i(ics1),
586
        .we_i(we1),
587
        .sel_i(sel1),
588
        .adr_i(adr1),
589
        .dati_i(dati1),
590
        .sr_i(sr1),
591
        .cr_i(cr1),
592
        .cs_o(cs1xx),
593
        .we_o(we1xx),
594
        .sel_o(sel1xx),
595
        .adr_o(adr1xx),
596
        .dati_o(dati1xx),
597
        .sr_o(sr1xx),
598
        .cr_o(cr1xx)
599
);
600
 
601
mpmc9_sync #(.W(C2W)) usyn2
602
(
603
        .clk(mem_ui_clk),
604
        .cs_i(cs2),
605
        .we_i(we2),
606
        .sel_i(sel2),
607
        .adr_i(adr2),
608
        .dati_i(dati2),
609
        .sr_i(1'b0),
610
        .cr_i(1'b0),
611
        .cs_o(cs2xx),
612
        .we_o(we2xx),
613
        .sel_o(sel2xx),
614
        .adr_o(adr2xx),
615
        .dati_o(dati2xx),
616
        .sr_o(),
617
        .cr_o()
618
);
619
 
620
mpmc9_sync #(.W(C3W)) usyn3
621
(
622
        .clk(mem_ui_clk),
623
        .cs_i(cs3),
624
        .we_i(we3),
625
        .sel_i(sel3),
626
        .adr_i(adr3),
627
        .dati_i(dati3),
628
        .sr_i(1'b0),
629
        .cr_i(1'b0),
630
        .cs_o(cs3xx),
631
        .we_o(we3xx),
632
        .sel_o(sel3xx),
633
        .adr_o(adr3xx),
634
        .dati_o(dati3xx),
635
        .sr_o(),
636
        .cr_o()
637
);
638
 
639
mpmc9_sync #(.W(C4W)) usyn4
640
(
641
        .clk(mem_ui_clk),
642
        .cs_i(cs4),
643
        .we_i(we4),
644
        .sel_i(sel4),
645
        .adr_i(adr4),
646
        .dati_i(dati4),
647
        .sr_i(1'b0),
648
        .cr_i(1'b0),
649
        .cs_o(cs4xx),
650
        .we_o(we4xx),
651
        .sel_o(sel4xx),
652
        .adr_o(adr4xx),
653
        .dati_o(dati4xx),
654
        .sr_o(),
655
        .cr_o()
656
);
657
 
658
mpmc9_sync #(.W(C5W)) usyn5
659
(
660
        .clk(mem_ui_clk),
661
        .cs_i(cs5),
662
        .we_i(1'b0),
663
        .sel_i(sel5),
664
        .adr_i(adr5),
665
        .dati_i(dati5),
666
        .sr_i(1'b0),
667
        .cr_i(1'b0),
668
        .cs_o(cs5xx),
669
        .we_o(),
670
        .sel_o(sel5xx),
671
        .adr_o(adr5xx),
672
        .dati_o(dati5xx),
673
        .sr_o(),
674
        .cr_o()
675
);
676
 
677
mpmc9_sync #(.W(C6W)) usyn6
678
(
679
        .clk(mem_ui_clk),
680
        .cs_i(cs6),
681
        .we_i(we6),
682
        .sel_i(sel6),
683
        .adr_i(adr6),
684
        .dati_i(dati6),
685
        .sr_i(1'b0),
686
        .cr_i(1'b0),
687
        .cs_o(cs6xx),
688
        .we_o(we6xx),
689
        .sel_o(sel6xx),
690
        .adr_o(adr6xx),
691
        .dati_o(dati6xx),
692
        .sr_o(),
693
        .cr_o()
694
);
695
 
696
mpmc9_sync #(.W(C7R)) usyn7
697
(
698
        .clk(mem_ui_clk),
699
        .cs_i(cs7),
700
        .we_i(we7),
701
        .sel_i(sel7),
702
        .adr_i(adr7),
703
        .dati_i(dati7),
704
        .sr_i(sr7),
705
        .cr_i(cr7),
706
        .cs_o(cs7xx),
707
        .we_o(we7xx),
708
        .sel_o(sel7xx),
709
        .adr_o(adr7xx),
710
        .dati_o(dati7xx),
711
        .sr_o(sr7xx),
712
        .cr_o(cr7xx)
713
);
714
 
715
reg [19:0] rst_ctr;
716
always @(posedge clk100MHz)
717
if (rst_i)
718
        rst_ctr <= 24'd0;
719
else begin
720
        if (!rst_ctr[15])
721
                rst_ctr <= rst_ctr + 2'd1;
722
        rstn <= rst_ctr[15];
723
end
724
 
725
reg toggle;     // CPU1 / CPU0 priority toggle
726
reg toggle_sr;
727
reg [19:0] resv_to_cnt;
728
reg sr1x,sr7x;
729
reg [127:0] dati128;
730
 
731
// Detect cache hits on read caches
732
// For the sprite channel, reading the 64-bits of a strip not beginning at
733
// a 64-byte aligned paragraph only checks for the 64 bit address adr[5:3].
734
// It's assumed that a 4x128-bit strips were read the by the previous access.
735
// It's also assumed that the strip address won't match because there's more
736
// than one sprite and sprite accesses are essentially random.
737
wire ch0_taghit = cs0xx && !we0xx && ch0_hit;
738
wire ch1_taghit = ics1 && !we1xx && cs1xx && ch1_hit;
739
wire ch2_taghit = !we2xx && cs2xx && ch2_hit;
740
wire ch3_taghit = !we3xx && cs3xx && ch3_hit;
741
wire ch4_taghit = !we4xx && cs4xx && ch4_hit;
742
wire ch5_taghit = cs5xx && ch5_hit;
743
wire ch6_taghit = !we6xx && cs6xx && ch6_hit;
744
wire ch7_taghit = cs7xx && !we7xx && ch7_hit;
745
 
746
always_comb
747
begin
748
        sr1x = FALSE;
749
  if (ch1_taghit)
750
    sr1x = sr1xx;
751
end
752
always_comb
753
begin
754
        sr7x = FALSE;
755
  if (ch7_taghit)
756
    sr7x = sr7xx;
757
end
758
 
759
// Select the channel
760
mpmc9_ch_prioritize uchp1
761
(
762
        .clk(mem_ui_clk),
763
        .state(state),
764
        .cs0(cs0xx),
765
        .cs1(cs1xx),
766
        .cs2(cs2xx),
767
        .cs3(cs3xx),
768
        .cs4(cs4xx),
769
        .cs5(cs5xx),
770
        .cs6(cs6xx),
771
        .cs7(cs7xx),
772
        .we0(we0xx),
773
        .we1(we1xx),
774
        .we2(we2xx),
775
        .we3(we3xx),
776
        .we4(we4xx),
777
        .we5(1'b0),
778
        .we6(we6xx),
779
        .we7(we7xx),
780
        .ch0_taghit(ch0_taghit),
781
        .ch1_taghit(ch1_taghit),
782
        .ch2_taghit(ch2_taghit),
783
        .ch3_taghit(ch3_taghit),
784
        .ch4_taghit(ch4_taghit),
785
        .ch5_taghit(ch5_taghit),
786
        .ch6_taghit(ch6_taghit),
787
        .ch7_taghit(ch7_taghit),
788
        .ch(nch)
789
);
790
 
791
 
792
always_ff @(posedge mem_ui_clk)
793
if (state==IDLE || (state==PRESET1 && do_wr))
794
        ch <= nch;
795
 
796
mpmc9_addr_select
797
uadrs1
798
(
799
        .rst(mem_ui_rst),
800
        .clk(mem_ui_clk),
801
        .state(state),
802
        .ch(nch),
803
        .adr0(adr0xx),
804
        .adr1(adr1xx),
805
        .adr2(adr2xx),
806
        .adr3(adr3xx),
807
        .adr4(adr4xx),
808
        .adr5(adr5xx),
809
        .adr6(adr6xx),
810
        .adr7(adr7xx),
811
        .adr(adr)
812
);
813
 
814
wire [2:0] app_addr3;
815
 
816
mpmc9_addr_gen uagen1
817
(
818
        .rst(mem_ui_rst),
819
        .clk(mem_ui_clk),
820
        .state(state),
821
        .rdy(app_rdy),
822
        .num_strips(num_strips),
823
        .strip_cnt(req_strip_cnt),
824
        .addr_base(adr),
825
        .addr({app_addr3,app_addr})
826
);
827
 
828
mpmc9_waddr_gen uwadgen1
829
(
830
        .rst(mem_ui_rst),
831
        .clk(mem_ui_clk),
832
        .state(state),
833
        .valid(app_rd_data_valid),
834
        .num_strips(num_strips),
835
        .strip_cnt(resp_strip_cnt),
836
        .addr_base(adr),
837
        .addr(app_waddr)
838
);
839
 
840
// Setting the write mask
841
reg [15:0] wmask0;
842
reg [15:0] wmask1;
843
reg [15:0] wmask2;
844
reg [15:0] wmask3;
845
reg [15:0] wmask4;
846
reg [15:0] wmask5;
847
reg [15:0] wmask6;
848
reg [15:0] wmask7;
849
 
850
mpmc9_set_write_mask
851
#(
852
        .C0W(C0W),
853
        .C1W(C1W),
854
        .C2W(C2W),
855
        .C3W(C3W),
856
        .C4W(C4W),
857
        .C5W(C5W),
858
        .C6W(C6W),
859
        .C7W(C7W)
860
)
861
uswm1
862
(
863
        .clk(mem_ui_clk),
864
        .state(state),
865
        .we0(we0xx),
866
        .we1(we1xx),
867
        .we2(we2xx),
868
        .we3(we3xx),
869
        .we4(we4xx),
870
        .we5(1'b0),
871
        .we6(we6xx),
872
        .we7(we7xx),
873
        .sel0(sel0xx),
874
        .sel1(sel1xx),
875
        .sel2(sel2xx),
876
        .sel3(sel3xx),
877
        .sel4(sel4xx),
878
        .sel5(sel5xx),
879
        .sel6(sel6xx),
880
        .sel7(sel7xx),
881
        .adr0(adr0xx),
882
        .adr1(adr1xx),
883
        .adr2(adr2xx),
884
        .adr3(adr3xx),
885
        .adr4(adr4xx),
886
        .adr5(adr5xx),
887
        .adr6(adr6xx),
888
        .adr7(adr7xx),
889
        .mask0(wmask0),
890
        .mask1(wmask1),
891
        .mask2(wmask2),
892
        .mask3(wmask3),
893
        .mask4(wmask4),
894
        .mask5(wmask5),
895
        .mask6(wmask6),
896
        .mask7(wmask7)
897
);
898
 
899
// Setting the write data
900
mpmc9_data_select
901
#(
902
        .C0W(C0W),
903
        .C1W(C1W),
904
        .C2W(C2W),
905
        .C3W(C3W),
906
        .C4W(C4W),
907
        .C5W(C5W),
908
        .C6W(C6W),
909
        .C7W(C7W)
910
)
911
uds1
912
(
913
        .clk(mem_ui_clk),
914
        .state(state),
915
        .ch(nch),
916
        .dati0(dati0xx),
917
        .dati1(dati1xx),
918
        .dati2(dati2xx),
919
        .dati3(dati3xx),
920
        .dati4(dati4xx),
921
        .dati5('d0),
922
        .dati6(dati6xx),
923
        .dati7(dati7xx),
924
        .dato(dat128)
925
);
926
 
927
// Setting the data value. Unlike reads there is only a single strip involved.
928
// Force unselected byte lanes to $FF
929
wire [15:0] mem_wdf_mask2;
930
reg [127:0] dat128x;
931
genvar g;
932
generate begin
933
        for (g = 0; g < 16; g = g + 1)
934
                always_comb
935
                        if (mem_wdf_mask2[g])
936
                                dat128x[g*8+7:g*8] = 8'hFF;
937
                        else
938
                                dat128x[g*8+7:g*8] = dat128[g*8+7:g*8];
939
end
940
endgenerate
941
 
942
always_ff @(posedge mem_ui_clk)
943
if (mem_ui_rst)
944
  app_wdf_data <= 128'd0;
945
else begin
946
        if (state==PRESET2)
947
                app_wdf_data <= dat128x;
948
        else if (state==WRITE_TRAMP1)
949
                app_wdf_data <= rmw_data;
950
end
951
 
952
generate begin
953
for (g = 0; g < 16; g = g + 1) begin
954
        always_ff @(posedge mem_ui_clk)
955
        begin
956
                if (state==WRITE_TRAMP) begin
957
                        if (app_wdf_mask[g])
958
                                rmw_data[g*8+7:g*8] <= app_wdf_data[g*8+7:g*8];
959
                        else
960
                                rmw_data[g*8+7:g*8] <= app_rd_data[g*8+7:g*8];
961
                end
962
        end
963
end
964
end
965
endgenerate
966
 
967
always_ff @(posedge mem_ui_clk)
968
if (state==IDLE)
969
        spriteno_r <= spritenoxx;
970
 
971
// Setting burst length
972
mpmc9_set_num_strips
973
#(
974
        .S0(STRIPS0),
975
        .S1(STRIPS1),
976
        .S2(STRIPS2),
977
        .S3(STRIPS3),
978
        .S4(STRIPS4),
979
        .S5(STRIPS5),
980
        .S6(STRIPS6),
981
        .S7(STRIPS7)
982
)
983
usns1
984
(
985
        .clk(mem_ui_clk),
986
        .state(state),
987
        .ch(nch),
988
        .we0(we0xx),
989
        .we1(we1xx),
990
        .we2(we2xx),
991
        .we3(we3xx),
992
        .we4(we4xx),
993
        .we5(we5xx),
994
        .we6(we6xx),
995
        .we7(we7xx),
996
        .num_strips(num_strips)
997
);
998
 
999
// Setting the data mask. Values are enabled when the data mask is zero.
1000
mpmc9_mask_select umsks1
1001
(
1002
        .rst(mem_ui_rst),
1003
        .clk(mem_ui_clk),
1004
        .state(state),
1005
        .ch(ch),
1006
        .wmask0(wmask0),
1007
        .wmask1(wmask1),
1008
        .wmask2(wmask2),
1009
        .wmask3(wmask3),
1010
        .wmask4(wmask4),
1011
        .wmask5(wmask5),
1012
        .wmask6(wmask6),
1013
        .wmask7(wmask7),
1014
        .mask(app_wdf_mask),
1015
        .mask2(mem_wdf_mask2)
1016
);
1017
 
1018
// Setting output data. Force output data to zero when not selected to allow
1019
// wire-oring the data.
1020
mpmc9_data_output udo1
1021
(
1022
        .clk0(clk0), .cs0(cs0), .adr0(adr0), .ch0_rdat(ch0_rdat), .dato0(dato0),
1023
        .clk1(clk1), .cs1(cs1), .adr1(adr1), .ch1_rdat(ch1_rdat), .dato1(dato1),
1024
        .clk2(clk2), .cs2(cs2), .adr2(adr2), .ch2_rdat(ch2_rdat), .dato2(dato2),
1025
        .clk3(clk3), .cs3(cs3), .adr3(adr3), .ch3_rdat(ch3_rdat), .dato3(dato3),
1026
        .clk4(clk4), .cs4(cs4), .adr4(adr4), .ch4_rdat(ch4_rdat), .dato4(dato4),
1027
        .clk5(clk5), .cs5(cs5), .adr5(adr5), .ch5_rdat(ch5_rdat), .dato5(dato5),
1028
        .clk6(clk6), .cs6(cs6), .adr6(adr6), .ch6_rdat(ch6_rdat), .dato6(dato6),
1029
        .clk7(clk7), .cs7(cs7), .adr7(adr7), .ch7_rdat(ch7_rdat), .dato7(dato7)
1030
);
1031
 
1032
mpmc9_ack_gen #(.N(0)) uackg0
1033
(
1034
        .rst(rst_i|mem_ui_rst),
1035
        .clk(mem_ui_clk),
1036
        .state(state),
1037
        .ch(ch),
1038
        .cs(cs0),
1039
        .adr(adr0xx),
1040
        .cr(1'b0),
1041
        .wr(do_wr),
1042
        .to(tocnt[9]),
1043
        .taghit(ch0_taghit),
1044
        .resv_ch(resv_ch),
1045
        .resv_adr(resv_adr),
1046
        .ack(acki0),
1047
        .pre_ack(pre_ack0)
1048
);
1049
 
1050
mpmc9_ack_gen #(.N(1)) uackg1
1051
(
1052
        .rst(rst_i|mem_ui_rst),
1053
        .clk(mem_ui_clk),
1054
        .state(state),
1055
        .ch(ch),
1056
        .cs(cs1&ics1),
1057
        .adr(adr1xx),
1058
        .cr(cr1xx),
1059
        .wr(do_wr),
1060
        .to(tocnt[9]),
1061
        .taghit(ch1_taghit),
1062
        .resv_ch(resv_ch),
1063
        .resv_adr(resv_adr),
1064
        .ack(acki1),
1065
        .pre_ack(pre_ack1)
1066
);
1067
 
1068
mpmc9_ack_gen #(.N(2)) uackg2
1069
(
1070
        .rst(rst_i|mem_ui_rst),
1071
        .clk(mem_ui_clk),
1072
        .state(state),
1073
        .ch(ch),
1074
        .cs(cs2),
1075
        .adr(adr2xx),
1076
        .cr(1'b0),
1077
        .wr(do_wr),
1078
        .to(tocnt[9]),
1079
        .taghit(ch2_taghit),
1080
        .resv_ch(resv_ch),
1081
        .resv_adr(resv_adr),
1082
        .ack(acki2),
1083
        .pre_ack(pre_ack2)
1084
);
1085
 
1086
mpmc9_ack_gen #(.N(3)) uackg3
1087
(
1088
        .rst(rst_i|mem_ui_rst),
1089
        .clk(mem_ui_clk),
1090
        .state(state),
1091
        .ch(ch),
1092
        .cs(cs3),
1093
        .adr(adr3xx),
1094
        .cr(1'b0),
1095
        .wr(do_wr),
1096
        .to(tocnt[9]),
1097
        .taghit(ch3_taghit),
1098
        .resv_ch(resv_ch),
1099
        .resv_adr(resv_adr),
1100
        .ack(acki3),
1101
        .pre_ack(pre_ack3)
1102
);
1103
 
1104
mpmc9_ack_gen #(.N(4)) uackg4
1105
(
1106
        .rst(rst_i|mem_ui_rst),
1107
        .clk(mem_ui_clk),
1108
        .state(state),
1109
        .ch(ch),
1110
        .cs(cs4),
1111
        .adr(adr4xx),
1112
        .cr(1'b0),
1113
        .wr(do_wr),
1114
        .to(tocnt[9]),
1115
        .taghit(ch4_taghit),
1116
        .resv_ch(resv_ch),
1117
        .resv_adr(resv_adr),
1118
        .ack(acki4),
1119
        .pre_ack(pre_ack4)
1120
);
1121
 
1122
mpmc9_ack_gen #(.N(5)) uackg5
1123
(
1124
        .rst(rst_i|mem_ui_rst),
1125
        .clk(mem_ui_clk),
1126
        .state(state),
1127
        .ch(ch),
1128
        .cs(cs5),
1129
        .adr(adr5xx),
1130
        .cr(1'b0),
1131
        .wr(do_wr),
1132
        .to(tocnt[9]),
1133
        .taghit(ch5_taghit),
1134
        .resv_ch(resv_ch),
1135
        .resv_adr(resv_adr),
1136
        .ack(acki5),
1137
        .pre_ack(pre_ack5)
1138
);
1139
 
1140
mpmc9_ack_gen #(.N(6)) uackg6
1141
(
1142
        .rst(rst_i|mem_ui_rst),
1143
        .clk(mem_ui_clk),
1144
        .state(state),
1145
        .ch(ch),
1146
        .cs(cs6),
1147
        .adr(adr6xx),
1148
        .cr(1'b0),
1149
        .wr(do_wr),
1150
        .to(tocnt[9]),
1151
        .taghit(ch6_taghit),
1152
        .resv_ch(resv_ch),
1153
        .resv_adr(resv_adr),
1154
        .ack(acki6),
1155
        .pre_ack(pre_ack6)
1156
);
1157
 
1158
mpmc9_ack_gen #(.N(7)) uackg7
1159
(
1160
        .rst(rst_i|mem_ui_rst),
1161
        .clk(mem_ui_clk),
1162
        .state(state),
1163
        .ch(ch),
1164
        .cs(ics7),
1165
        .adr(adr7xx),
1166
        .cr(cr7xx),
1167
        .wr(do_wr),
1168
        .to(tocnt[9]),
1169
        .taghit(ch7_taghit),
1170
        .resv_ch(resv_ch),
1171
        .resv_adr(resv_adr),
1172
        .ack(acki7),
1173
        .pre_ack(pre_ack7)
1174
);
1175
 
1176
wire ne_data_valid;
1177
edge_det ued1 (.rst(rst_i), .clk(mem_ui_clk), .ce(1'b1), .i(app_rd_data_valid), .pe(), .ne(ne_data_valid), .ee());
1178
 
1179
mpmc9_state_machine ustmac1
1180
(
1181
        .rst(rst_i|mem_ui_rst),
1182
        .clk(mem_ui_clk),
1183
        .ch(nch),
1184
        .acki0(acki0),
1185
        .acki1(acki1),
1186
        .acki2(acki2),
1187
        .acki3(acki3),
1188
        .acki4(acki4),
1189
        .acki5(acki5),
1190
        .acki6(acki6),
1191
        .acki7(acki7),
1192
        .ch0_taghit(ch0_taghit),
1193
        .ch1_taghit(ch1_taghit),
1194
        .ch2_taghit(ch2_taghit),
1195
        .ch3_taghit(ch3_taghit),
1196
        .ch4_taghit(ch4_taghit),
1197
        .ch5_taghit(ch5_taghit),
1198
        .ch6_taghit(ch6_taghit),
1199
        .ch7_taghit(ch7_taghit),
1200
        .wdf_rdy(app_wdf_rdy),
1201
        .rdy(app_rdy),
1202
        .do_wr(do_wr),
1203
        .rd_data_valid(app_rd_data_valid),
1204
        .num_strips(num_strips),
1205
        .req_strip_cnt(req_strip_cnt),
1206
        .resp_strip_cnt(resp_strip_cnt),
1207
        .to(tocnt[9]),
1208
        .cr1(cr1xx),
1209
        .cr7(cr7xx),
1210
        .adr1(adr1xx),
1211
        .adr7(adr7xx),
1212
        .resv_ch(resv_ch),
1213
        .resv_adr(resv_adr),
1214
        .state(state)
1215
);
1216
 
1217
 
1218
wire [3:0] prev_state;
1219
 
1220
mpmc9_to_cnt utoc1
1221
(
1222
        .clk(mem_ui_clk),
1223
        .state(state),
1224
        .prev_state(prev_state),
1225
        .to_cnt(tocnt)
1226
);
1227
 
1228
mpmc9_prev_state upst1
1229
(
1230
        .clk(mem_ui_clk),
1231
        .state(state),
1232
        .prev_state(prev_state)
1233
);
1234
 
1235
mpmc9_app_en_gen ueng1
1236
(
1237
        .clk(mem_ui_clk),
1238
        .state(state),
1239
        .rdy(app_rdy),
1240
        .strip_cnt(req_strip_cnt),
1241
        .num_strips(num_strips),
1242
        .en(app_en)
1243
);
1244
 
1245
mpmc9_app_cmd_gen ucg1
1246
(
1247
        .clk(mem_ui_clk),
1248
        .state(state),
1249
        .cmd(app_cmd)
1250
);
1251
 
1252
mpmc9_app_wdf_wren_gen uwreng1
1253
(
1254
        .clk(mem_ui_clk),
1255
        .state(state),
1256
        .rdy(app_wdf_rdy),
1257
        .wren(app_wdf_wren)
1258
);
1259
 
1260
mpmc9_app_wdf_end_gen uwendg1
1261
(
1262
        .clk(mem_ui_clk),
1263
        .state(state),
1264
        .rdy(app_wdf_rdy),
1265
        .wend(app_wdf_end)
1266
);
1267
 
1268
mpmc9_req_strip_cnt ursc1
1269
(
1270
        .clk(mem_ui_clk),
1271
        .state(state),
1272
        .wdf_rdy(app_wdf_rdy),
1273
        .rdy(app_rdy),
1274
        .num_strips(num_strips),
1275
        .strip_cnt(req_strip_cnt)
1276
);
1277
 
1278
mpmc9_resp_strip_cnt urespsc1
1279
(
1280
        .clk(mem_ui_clk),
1281
        .state(state),
1282
        .valid(app_rd_data_valid),
1283
        .num_strips(num_strips),
1284
        .strip_cnt(resp_strip_cnt)
1285
);
1286
 
1287
 
1288
mpmc9_do_wr udowr0
1289
(
1290
        .we(we0xx),
1291
        .cr(1'b0),
1292
        .adr(adr0xx),
1293
        .resv_ch(resv_ch),
1294
        .resv_adr(resv_adr),
1295
        .do_wr(do_wr0)
1296
);
1297
 
1298
mpmc9_do_wr udowr1
1299
(
1300
        .we(we1xx),
1301
        .cr(cr1xx),
1302
        .adr(adr1xx),
1303
        .resv_ch(resv_ch),
1304
        .resv_adr(resv_adr),
1305
        .do_wr(do_wr1)
1306
);
1307
 
1308
mpmc9_do_wr udowr2
1309
(
1310
        .we(we2xx),
1311
        .cr(1'b0),
1312
        .adr(adr2xx),
1313
        .resv_ch(resv_ch),
1314
        .resv_adr(resv_adr),
1315
        .do_wr(do_wr2)
1316
);
1317
 
1318
mpmc9_do_wr udowr3
1319
(
1320
        .we(we3xx),
1321
        .cr(1'b0),
1322
        .adr(adr3xx),
1323
        .resv_ch(resv_ch),
1324
        .resv_adr(resv_adr),
1325
        .do_wr(do_wr3)
1326
);
1327
 
1328
mpmc9_do_wr udowr4
1329
(
1330
        .we(we4xx),
1331
        .cr(1'b0),
1332
        .adr(adr4xx),
1333
        .resv_ch(resv_ch),
1334
        .resv_adr(resv_adr),
1335
        .do_wr(do_wr4)
1336
);
1337
 
1338
mpmc9_do_wr udowr5
1339
(
1340
        .we(1'b0),
1341
        .cr(1'b0),
1342
        .adr(adr5xx),
1343
        .resv_ch(resv_ch),
1344
        .resv_adr(resv_adr),
1345
        .do_wr(do_wr5)
1346
);
1347
 
1348
mpmc9_do_wr udowr6
1349
(
1350
        .we(we6xx),
1351
        .cr(1'b0),
1352
        .adr(adr6xx),
1353
        .resv_ch(resv_ch),
1354
        .resv_adr(resv_adr),
1355
        .do_wr(do_wr6)
1356
);
1357
 
1358
mpmc9_do_wr udowr7
1359
(
1360
        .we(we7xx),
1361
        .cr(cr7xx),
1362
        .adr(adr7xx),
1363
        .resv_ch(resv_ch),
1364
        .resv_adr(resv_adr),
1365
        .do_wr(do_wr7)
1366
);
1367
 
1368
mpmc9_do_wr_select udws1
1369
(
1370
        .clk(mem_ui_clk),
1371
        .state(state),
1372
        .ch(nch),
1373
        .wr0(do_wr0),
1374
        .wr1(do_wr1),
1375
        .wr2(do_wr2),
1376
        .wr3(do_wr3),
1377
        .wr4(do_wr4),
1378
        .wr5(do_wr5),
1379
        .wr6(do_wr6),
1380
        .wr7(do_wr7),
1381
        .wr(do_wr)
1382
);
1383
 
1384
// Reservation status bit
1385
mpmc9_resv_bit ursb1
1386
(
1387
        .clk(mem_ui_clk),
1388
        .state(state),
1389
        .cs(cs1xx),
1390
        .we(we1xx),
1391
        .ack(acki1),
1392
        .cr(cr1xx),
1393
        .adr(adr1xx),
1394
        .resv_ch(resv_ch),
1395
        .resv_adr(resv_adr),
1396
        .rb(rb1)
1397
);
1398
 
1399
mpmc9_resv_bit ursb7
1400
(
1401
        .clk(mem_ui_clk),
1402
        .state(state),
1403
        .cs(cs7xx),
1404
        .we(we7xx),
1405
        .ack(acki7),
1406
        .cr(cr7xx),
1407
        .adr(adr7xx),
1408
        .resv_ch(resv_ch),
1409
        .resv_adr(resv_adr),
1410
        .rb(rb7)
1411
);
1412
 
1413
// Managing address reservations
1414
mpmc9_addr_resv_man uarman1
1415
(
1416
        .rst(mem_ui_rst),
1417
        .clk(mem_ui_clk),
1418
        .state(state),
1419
        .cs1(cs1xx),
1420
        .ack1(acki1),
1421
        .we1(we1xx),
1422
        .adr1(adr1xx),
1423
        .sr1(sr1x),
1424
        .cr1(cr1xx),
1425
        .ch1_taghit(ch1_taghit),
1426
        .cs7(cs7xx),
1427
        .ack7(acki7),
1428
        .we7(we7xx),
1429
        .adr7(adr7xx),
1430
        .sr7(sr7x),
1431
        .cr7(cr7xx),
1432
        .ch7_taghit(ch7_taghit),
1433
        .resv_ch(resv_ch),
1434
        .resv_adr(resv_adr)
1435
);
1436
 
1437
endmodule

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