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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//       ||
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
//    contributors may be used to endorse or promote products derived from
//    this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
//
import mpmc9_pkg::*;
 
module mpmc9_state_machine(rst, clk, ch,
        acki0, acki1, acki2, acki3, acki4, acki5, acki6, acki7,
        ch0_taghit, ch1_taghit, ch2_taghit, ch3_taghit, ch4_taghit, ch5_taghit,
        ch6_taghit, ch7_taghit, wdf_rdy, rdy, do_wr, rd_data_valid,
        num_strips, req_strip_cnt, resp_strip_cnt, to,
        cr1, cr7, adr1, adr7,
        resv_ch, resv_adr,
        state
);
input rst;
input clk;
input [3:0] ch;
input acki0;
input acki1;
input acki2;
input acki3;
input acki4;
input acki5;
input acki6;
input acki7;
input ch0_taghit;
input ch1_taghit;
input ch2_taghit;
input ch3_taghit;
input ch4_taghit;
input ch5_taghit;
input ch6_taghit;
input ch7_taghit;
input wdf_rdy;
input rdy;
input do_wr;
input rd_data_valid;
input [5:0] num_strips;
input [5:0] req_strip_cnt;
input [5:0] resp_strip_cnt;
input to;
input cr1;
input cr7;
input [31:0] adr1;
input [31:0] adr7;
input [3:0] resv_ch [0:NAR-1];
input [31:0] resv_adr [0:NAR-1];
output reg [3:0] state;
 
reg [3:0] next_state;
 
// State machine
always_ff @(posedge clk)
        state <= next_state;
 
integer n3;
always_comb
if (rst)
        next_state <= IDLE;
else begin
case(state)
IDLE:
        begin
                next_state <= IDLE;
          // According to the docs there's no need to wait for calib complete.
          // Calib complete goes high in sim about 111 us.
          // Simulation setting must be set to FAST.
                //if (calib_complete)
                case(ch)
                3'd0:   if (!acki0) next_state <= PRESET1;
                3'd1:
                        if (!acki1) begin
                    if (cr1) begin
                next_state <= IDLE;
                        for (n3 = 0; n3 < NAR; n3 = n3 + 1)
                        if ((resv_ch[n3]==4'd1) && (resv_adr[n3][31:4]==adr1[31:4]))
                        next_state <= PRESET1;
                    end
                    else
                next_state <= PRESET1;
            end
                3'd2:   if (!acki2) next_state <= PRESET1;
                3'd3:   if (!acki3) next_state <= PRESET1;
                3'd4:   if (!acki4) next_state <= PRESET1;
                3'd5:   if (!acki5) next_state <= PRESET1;
                3'd6:   if (!acki6) next_state <= PRESET1;
                3'd7:
                        if (!acki7) begin
                    if (cr7) begin
                next_state <= IDLE;
                        for (n3 = 0; n3 < NAR; n3 = n3 + 1)
                        if ((resv_ch[n3]==4'd7) && (resv_adr[n3][31:4]==adr7[31:4]))
                    next_state <= PRESET1;
                    end
                    else
                next_state <= PRESET1;
            end
                default:        ;       // no channel selected -> stay in IDLE state
                endcase
        end
// If an ack is received during a preset cycle it is likely a read cycle that
// acked a cycle late. Abort the cycle.
PRESET1:
        if (do_wr)
                next_state <= PRESET2;
        else
                case(ch)
                4'd0:   if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd1:   if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd2:   if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd3:   if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd4:   if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd5:   if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd6:   if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET2;
                4'd7:   if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET2;
                default:        next_state <= PRESET2;
                endcase
// The valid data, data mask and address are placed in app_wdf_data, app_wdf_mask,
// and memm_addr ahead of time.
PRESET2:
        if (do_wr)
                next_state <= PRESET3;
        else
                case(ch)
                4'd0:   if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd1:   if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd2:   if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd3:   if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd4:   if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd5:   if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd6:   if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET3;
                4'd7:   if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET3;
                default:        next_state <= PRESET3;
                endcase
// PRESET3 determines the read or write command
PRESET3:
        if (do_wr && !RMW)
                next_state <= WRITE_DATA0;
        else begin
                next_state <= READ_DATA0;
                case(ch)
                4'd0:   if (ch0_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd1:   if (ch1_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd2:   if (ch2_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd3:   if (ch3_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd4:   if (ch4_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd5:   if (ch5_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd6:   if (ch6_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                4'd7:   if (ch7_taghit) next_state <= IDLE; else next_state <= READ_DATA0;
                default:        next_state <= READ_DATA0;
                endcase
        end
 
// Write data to the data fifo
// Write occurs when app_wdf_wren is true and app_wdf_rdy is true
WRITE_DATA0:
        // Issue a write command if the fifo is full.
//      if (!app_wdf_rdy)
//              next_state <= WRITE_DATA1;
//      else
        if (wdf_rdy)// && req_strip_cnt==num_strips)
                next_state <= WRITE_DATA1;
        else
                next_state <= WRITE_DATA0;
WRITE_DATA1:
        next_state <= WRITE_DATA2;
WRITE_DATA2:
        if (rdy)
                next_state <= WRITE_DATA3;
        else
                next_state <= WRITE_DATA2;
WRITE_DATA3:
        next_state <= IDLE;
        /*
        if (req_strip_cnt==num_strips)
                next_state <= IDLE;
        else
                next_state <= WRITE_DATA0;
        */
// There could be multiple read requests submitted before any response occurs.
// Stay in the SET_CMD_RD until all requested strips have been processed.
READ_DATA0:
        next_state <= READ_DATA1;
// Could it take so long to do the request that we start getting responses
// back?
READ_DATA1:
        if (rdy && req_strip_cnt==num_strips)
                next_state <= READ_DATA2;
        else
                next_state <= READ_DATA1;
// Wait for incoming responses, but only for so long to prevent a hang.
READ_DATA2:
        if (rd_data_valid && resp_strip_cnt==num_strips)
                next_state <= WAIT_NACK;
        else
                next_state <= READ_DATA2;
 
WAIT_NACK:
        // If we're not seeing a nack and there is a channel selected, then the
        // cache tag must not have updated correctly.
        // For writes, assume a nack by now.
        next_state <= IDLE;
        /*
        case(ch)
        3'd0:   if (ne_acki0) next_state <= IDLE;
        3'd1:   if (ne_acki1) next_state <= IDLE;
        3'd2:   if (ne_acki2) next_state <= IDLE;
        3'd3:   if (ne_acki3) next_state <= IDLE;
        3'd4:   if (ne_acki4) next_state <= IDLE;
        3'd5:   if (ne_acki5) next_state <= IDLE;
        3'd6:   if (ne_acki6) next_state <= IDLE;
        3'd7:   if (ne_acki7) next_state <= IDLE;
        default:        next_state <= IDLE;
        endcase
        */
default:        next_state <= IDLE;
endcase
 
// Is the state machine hung?
if (to)
        next_state <= IDLE;
end
 
endmodule

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[/] [mpmc8/] [trunk/] [rtl/] [mpmc9_state_machine.sv] - Blame information for rev 8

Line No.	Rev	Author	Line
1	4	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch@finitron.ca`
7			`// \|\|`
8			`//`
9			`// BSD 3-Clause License`
10			`// Redistribution and use in source and binary forms, with or without`
11			`// modification, are permitted provided that the following conditions are met:`
12			`//`
13			`// 1. Redistributions of source code must retain the above copyright notice, this`
14			`// list of conditions and the following disclaimer.`
15			`//`
16			`// 2. Redistributions in binary form must reproduce the above copyright notice,`
17			`// this list of conditions and the following disclaimer in the documentation`
18			`// and/or other materials provided with the distribution.`
19			`//`
20			`// 3. Neither the name of the copyright holder nor the names of its`
21			`// contributors may be used to endorse or promote products derived from`
22			`// this software without specific prior written permission.`
23			`//`
24			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
25			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
26			`// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
27			`// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
28			`// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
29			`// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
30			`// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
31			`// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
32			`// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
33			`// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
34			`//`
35			`// ============================================================================`
36			`//`
37			`import mpmc9_pkg::*;`
38
39			`module mpmc9_state_machine(rst, clk, ch,`
40			`acki0, acki1, acki2, acki3, acki4, acki5, acki6, acki7,`
41			`ch0_taghit, ch1_taghit, ch2_taghit, ch3_taghit, ch4_taghit, ch5_taghit,`
42			`ch6_taghit, ch7_taghit, wdf_rdy, rdy, do_wr, rd_data_valid,`
43			`num_strips, req_strip_cnt, resp_strip_cnt, to,`
44			`cr1, cr7, adr1, adr7,`
45			`resv_ch, resv_adr,`
46			`state`
47			`);`
48			`input rst;`
49			`input clk;`
50			`input [3:0] ch;`
51			`input acki0;`
52			`input acki1;`
53			`input acki2;`
54			`input acki3;`
55			`input acki4;`
56			`input acki5;`
57			`input acki6;`
58			`input acki7;`
59			`input ch0_taghit;`
60			`input ch1_taghit;`
61			`input ch2_taghit;`
62			`input ch3_taghit;`
63			`input ch4_taghit;`
64			`input ch5_taghit;`
65			`input ch6_taghit;`
66			`input ch7_taghit;`
67			`input wdf_rdy;`
68			`input rdy;`
69			`input do_wr;`
70			`input rd_data_valid;`
71			`input [5:0] num_strips;`
72			`input [5:0] req_strip_cnt;`
73			`input [5:0] resp_strip_cnt;`
74			`input to;`
75			`input cr1;`
76			`input cr7;`
77			`input [31:0] adr1;`
78			`input [31:0] adr7;`
79			`input [3:0] resv_ch [0:NAR-1];`
80			`input [31:0] resv_adr [0:NAR-1];`
81			`output reg [3:0] state;`
82
83			`reg [3:0] next_state;`
84
85			`// State machine`
86			`always_ff @(posedge clk)`
87			`state <= next_state;`
88
89			`integer n3;`
90			`always_comb`
91			`if (rst)`
92			`next_state <= IDLE;`
93			`else begin`
94			`case(state)`
95			`IDLE:`
96			`begin`
97			`next_state <= IDLE;`
98			`// According to the docs there's no need to wait for calib complete.`
99			`// Calib complete goes high in sim about 111 us.`
100			`// Simulation setting must be set to FAST.`
101			`//if (calib_complete)`
102			`case(ch)`
103			`3'd0: if (!acki0) next_state <= PRESET1;`
104			`3'd1:`
105			`if (!acki1) begin`
106			`if (cr1) begin`
107			`next_state <= IDLE;`
108			`for (n3 = 0; n3 < NAR; n3 = n3 + 1)`
109			`if ((resv_ch[n3]==4'd1) && (resv_adr[n3][31:4]==adr1[31:4]))`
110			`next_state <= PRESET1;`
111			`end`
112			`else`
113			`next_state <= PRESET1;`
114			`end`
115			`3'd2: if (!acki2) next_state <= PRESET1;`
116			`3'd3: if (!acki3) next_state <= PRESET1;`
117			`3'd4: if (!acki4) next_state <= PRESET1;`
118			`3'd5: if (!acki5) next_state <= PRESET1;`
119			`3'd6: if (!acki6) next_state <= PRESET1;`
120			`3'd7:`
121			`if (!acki7) begin`
122			`if (cr7) begin`
123			`next_state <= IDLE;`
124			`for (n3 = 0; n3 < NAR; n3 = n3 + 1)`
125			`if ((resv_ch[n3]==4'd7) && (resv_adr[n3][31:4]==adr7[31:4]))`
126			`next_state <= PRESET1;`
127			`end`
128			`else`
129			`next_state <= PRESET1;`
130			`end`
131			`default: ; // no channel selected -> stay in IDLE state`
132			`endcase`
133			`end`
134			`// If an ack is received during a preset cycle it is likely a read cycle that`
135			`// acked a cycle late. Abort the cycle.`
136			`PRESET1:`
137			`if (do_wr)`
138			`next_state <= PRESET2;`
139			`else`
140			`case(ch)`
141			`4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET2;`
142			`4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET2;`
143			`4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET2;`
144			`4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET2;`
145			`4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET2;`
146			`4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET2;`
147			`4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET2;`
148			`4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET2;`
149			`default: next_state <= PRESET2;`
150			`endcase`
151			`// The valid data, data mask and address are placed in app_wdf_data, app_wdf_mask,`
152			`// and memm_addr ahead of time.`
153			`PRESET2:`
154			`if (do_wr)`
155			`next_state <= PRESET3;`
156			`else`
157			`case(ch)`
158			`4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= PRESET3;`
159			`4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= PRESET3;`
160			`4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= PRESET3;`
161			`4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= PRESET3;`
162			`4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= PRESET3;`
163			`4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= PRESET3;`
164			`4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= PRESET3;`
165			`4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= PRESET3;`
166			`default: next_state <= PRESET3;`
167			`endcase`
168			`// PRESET3 determines the read or write command`
169			`PRESET3:`
170			`if (do_wr && !RMW)`
171			`next_state <= WRITE_DATA0;`
172			`else begin`
173			`next_state <= READ_DATA0;`
174			`case(ch)`
175			`4'd0: if (ch0_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
176			`4'd1: if (ch1_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
177			`4'd2: if (ch2_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
178			`4'd3: if (ch3_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
179			`4'd4: if (ch4_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
180			`4'd5: if (ch5_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
181			`4'd6: if (ch6_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
182			`4'd7: if (ch7_taghit) next_state <= IDLE; else next_state <= READ_DATA0;`
183			`default: next_state <= READ_DATA0;`
184			`endcase`
185			`end`
186
187			`// Write data to the data fifo`
188			`// Write occurs when app_wdf_wren is true and app_wdf_rdy is true`
189			`WRITE_DATA0:`
190			`// Issue a write command if the fifo is full.`
191			`// if (!app_wdf_rdy)`
192			`// next_state <= WRITE_DATA1;`
193			`// else`
194			`if (wdf_rdy)// && req_strip_cnt==num_strips)`
195			`next_state <= WRITE_DATA1;`
196			`else`
197			`next_state <= WRITE_DATA0;`
198			`WRITE_DATA1:`
199			`next_state <= WRITE_DATA2;`
200			`WRITE_DATA2:`
201			`if (rdy)`
202			`next_state <= WRITE_DATA3;`
203			`else`
204			`next_state <= WRITE_DATA2;`
205			`WRITE_DATA3:`
206			`next_state <= IDLE;`
207			`/*`
208			`if (req_strip_cnt==num_strips)`
209			`next_state <= IDLE;`
210			`else`
211			`next_state <= WRITE_DATA0;`
212			`*/`
213			`// There could be multiple read requests submitted before any response occurs.`
214			`// Stay in the SET_CMD_RD until all requested strips have been processed.`
215			`READ_DATA0:`
216			`next_state <= READ_DATA1;`
217			`// Could it take so long to do the request that we start getting responses`
218			`// back?`
219			`READ_DATA1:`
220			`if (rdy && req_strip_cnt==num_strips)`
221			`next_state <= READ_DATA2;`
222			`else`
223			`next_state <= READ_DATA1;`
224			`// Wait for incoming responses, but only for so long to prevent a hang.`
225			`READ_DATA2:`
226			`if (rd_data_valid && resp_strip_cnt==num_strips)`
227			`next_state <= WAIT_NACK;`
228			`else`
229			`next_state <= READ_DATA2;`
230
231			`WAIT_NACK:`
232			`// If we're not seeing a nack and there is a channel selected, then the`
233			`// cache tag must not have updated correctly.`
234			`// For writes, assume a nack by now.`
235			`next_state <= IDLE;`
236			`/*`
237			`case(ch)`
238			`3'd0: if (ne_acki0) next_state <= IDLE;`
239			`3'd1: if (ne_acki1) next_state <= IDLE;`
240			`3'd2: if (ne_acki2) next_state <= IDLE;`
241			`3'd3: if (ne_acki3) next_state <= IDLE;`
242			`3'd4: if (ne_acki4) next_state <= IDLE;`
243			`3'd5: if (ne_acki5) next_state <= IDLE;`
244			`3'd6: if (ne_acki6) next_state <= IDLE;`
245			`3'd7: if (ne_acki7) next_state <= IDLE;`
246			`default: next_state <= IDLE;`
247			`endcase`
248			`*/`
249			`default: next_state <= IDLE;`
250			`endcase`
251
252			`// Is the state machine hung?`
253			`if (to)`
254			`next_state <= IDLE;`
255			`end`
256
257			`endmodule`