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[/] [myblaze/] [trunk/] [rtl/] [dsram.py] - Blame information for rev 4

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1 2 rockee
# -*- coding: utf-8 -*-
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"""
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    dsram.py
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    ========
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    Dual port synchronous ram
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    :copyright: Copyright (c) 2010 Jian Luo.
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    :author-email: jian <dot> luo <dot> cn <at> gmail <dot> com.
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    :license: BSD, see LICENSE for details.
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    :revision: $Id: dsram.py 3 2010-11-21 07:17:00Z rockee $
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"""
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from myhdl import *
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from defines import *
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from functions import *
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def DSRAM(dat_o, adr_i, ena_i, dat_w_i, adr_w_i, wre_i, clock,
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           width=32, size=8):
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    """
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    Dual port synchronous RAM with New Data Read-During-Write Behavior
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    """
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    ram = [Signal(intbv(0)[width:]) for i in range(2**size)]
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    #read_addr = Signal(intbv(0)[len(adr_i):])
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    @always(clock.posedge)
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    def logic():
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        if ena_i:
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            if wre_i:
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                ram[int(adr_w_i)].next = dat_w_i
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            dat_o.next = ram[int(adr_i)]
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            #read_addr.next = adr_i
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                # XXX: Hacked to assure read after write
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                #if adr_w_i == adr_i:
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                    #dat_o.next = dat_w_i
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                #else:
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                    #dat_o.next = ram[int(adr_i)]
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            #else:
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                #dat_o.next = ram[int(adr_i)]
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    #@always_comb
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    #def passthrough():
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        #dat_o.next = ram[int(read_addr)]
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    return instances()
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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