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[/] [myblaze/] [trunk/] [rtl/] [functions.py] - Blame information for rev 5

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1 2 rockee 
# -*- coding: utf-8 -*-
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"""
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    functions.py
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    ============
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6 
    Functions
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8 5 rockee 
    :copyright: Copyright (c) 2010 Jian Luo
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    :author-email: jian.luo.cn(at_)gmail.com
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    :license: LGPL, see LICENSE for details
11 2 rockee 
    :revision: $Id: functions.py 5 2010-11-21 10:59:30Z rockee $
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"""
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from myhdl import *
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from defines import *
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def align_mem_load(data, size, address):
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    """
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    Aligns the memory load operation (Big endian decoding)
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    """
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    result = intbv(0)[32:]
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    if size == transfer_size_type.BYTE:
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        if address[1] == 0:
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            if address[0] == 0:
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                result[:] = data[32:24]
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            else:
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                result[:] = data[24:16]
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        else:
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            if address[0] == 0:
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                result[:] = data[16:8]
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            else:
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                result[:] = data[8:]
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    elif size == transfer_size_type.HALFWORD:
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        if address[1] == 0:
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            result[:] = data[32:16]
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        else:
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            result[:] = data[16:]
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    else:
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        result[:] = data
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    return result
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def decode_mem_store(address, size):
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    result = intbv(0)[4:]
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    if size == transfer_size_type.BYTE:
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        if address[1] == 0:
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            if address[0] == 0:
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                result[:] = 0b1000
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            else:
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                result[:] = 0b0100
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        else:
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            if address[0] == 0:
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                result[:] = 0b0010
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            else:
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                result[:] = 0b0001
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    elif size == transfer_size_type.HALFWORD:
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        if address[1] == 0:
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            result[:] = 0b1100
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        else:
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            result[:] = 0b0011
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    else:
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        result[:] = 0b1111
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    #if size == transfer_size_type.BYTE:
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        #if address[1] == 0:
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            #if address[0] == 0:
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                #result[:] = 0b0001
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            #else:
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                #result[:] = 0b0010
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        #else:
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            #if address[0] == 0:
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                #result[:] = 0b0100
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            #else:
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                #result[:] = 0b1000
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    #elif size == transfer_size_type.HALFWORD:
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        #if address[1] == 0:
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            #result[:] = 0b0011
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        #else:
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            #result[:] = 0b1100
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    #else:
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        #result[:] = 0b1111
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    return result
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def align_mem_store(data, size):
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    result = intbv(0)[32:]
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    if size == transfer_size_type.BYTE:
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        result[:] = concat(data[8:], data[8:], data[8:], data[8:])
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    elif size == transfer_size_type.HALFWORD:
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        result[:] = concat(data[16:], data[16:])
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    else:
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        result[:] = data
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    return result
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def forward_condition(reg_write, reg_a, reg_d):
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    result = reg_write and (reg_a == reg_d)
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    return result
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def select_register_data(reg_dat, reg_x, wb_dat, write):
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    tmp = intbv(0)[CFG_DMEM_WIDTH:]
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    if reg_x == 0:
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        tmp[:] = 0
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    elif write:
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        tmp[:] = wb_dat
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    else:
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        tmp[:] = reg_dat
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    return tmp
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def add(a, b, ci):
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    aa = intbv(0)[CFG_DMEM_WIDTH+2:]
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    bb = intbv(0)[CFG_DMEM_WIDTH+2:]
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    cc = intbv(0)[CFG_DMEM_WIDTH+2:]
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    result = intbv(0)[CFG_DMEM_WIDTH+1:]
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    aa[:] = concat(False, a, True)
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    bb[:] = concat(False, b, ci)
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    cc[:] = aa.signed() + bb.signed()
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    result[:] = cc[CFG_DMEM_WIDTH+2:1]
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    return result
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def repeat(input, times):
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    result = intbv(0)[times:]
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    for i in range(times):
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        result[i] = input
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    return result
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def bit_reverse(input, width):
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    result = intbv(0)[width:]
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    for i in range(width):
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        result[width-1-i] = input[i]
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    return result
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# XXX: Verilog don't allow veriable in slice,
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#      the workaround is to write 2 function instead, but that's ugly :-(
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def sign_extend(value, fill, from_size=16, to_size=32):
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    tmp = intbv(0)[to_size:]
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    size = to_size-from_size
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    for i in range(size):
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        tmp[to_size-1-i] = fill
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    tmp[from_size:] = value[from_size:]
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    return tmp
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def sign_extend8(value, fill):
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    tmp = intbv(0)[CFG_DMEM_WIDTH:]
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    size = CFG_DMEM_WIDTH-8
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    for i in range(size):
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        tmp[CFG_DMEM_WIDTH-1-i] = fill
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    tmp[8:] = value[8:]
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    return tmp
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def sign_extend16(value, fill):
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    tmp = intbv(0)[CFG_DMEM_WIDTH:]
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    size = CFG_DMEM_WIDTH-16
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    for i in range(size):
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        tmp[CFG_DMEM_WIDTH-1-i] = fill
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    tmp[16:] = value[16:]
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    return tmp
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#def select_register_data(reg_dat, reg, wb_dat, write)
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### EOF ###
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# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
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