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[/] [myblaze/] [trunk/] [rtl/] [memory.py] - Blame information for rev 5

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# -*- coding: utf-8 -*-
"""
    memory.py
    =========
 
    Memory Stage
 
    :copyright: Copyright (c) 2010 Jian Luo
    :author-email: jian.luo.cn(at_)gmail.com
    :license: LGPL, see LICENSE for details
    :revision: $Id: memory.py 5 2010-11-21 10:59:30Z rockee $
"""
 
from myhdl import *
from defines import *
from functions import *
 
def MemUnit(
        # Inputs
        clock,
        reset,
        enable,
        ex_alu_result,
        ex_reg_d,
        ex_reg_write,
        ex_branch,
        ex_dat_d,
        ex_mem_read,
        ex_mem_write,
        ex_program_counter,
        ex_transfer_size,
        # Outputs
        mm_alu_result,
        mm_mem_read,
        mm_reg_d,
        mm_reg_write,
        mm_transfer_size,
        dmem_data_out,
        dmem_sel_out,
        dmem_we_out,
        dmem_addr_out,
        dmem_ena_out,
        ):
    """
    """
    mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
 
    mm_comb_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
    mm_comb_mem_read = Signal(False)
    mm_comb_reg_d = Signal(intbv(0)[5:])
    mm_comb_reg_write = Signal(False)
    mm_comb_transfer_size = Signal(transfer_size_type.WORD)
 
    @always_comb
    def comb():
        # Local Variables
        alu_result = intbv(0)[CFG_DMEM_WIDTH:]
 
        if ex_branch:
            alu_result[:] = ex_program_counter
        else:
            alu_result[:] = ex_alu_result
 
        # TODO: forwarding
        mem_result.next = ex_dat_d
 
        # pipelining
        mm_comb_alu_result.next = alu_result
        mm_comb_mem_read.next = ex_mem_read
        mm_comb_reg_d.next = ex_reg_d
        mm_comb_reg_write.next = ex_reg_write
        mm_comb_transfer_size.next = ex_transfer_size
 
    @always_comb
    def control_dmem():
        dmem_data_out.next = mem_result
        dmem_sel_out.next = decode_mem_store(ex_alu_result[2:],ex_transfer_size)
        dmem_we_out.next = ex_mem_write
        dmem_addr_out.next = ex_alu_result[CFG_DMEM_SIZE:]
        dmem_ena_out.next = ex_mem_write or ex_mem_read
 
    @always(clock.posedge)
    def seq():
        if reset:
            mm_alu_result.next = 0
            mm_mem_read.next = False
            mm_reg_d.next = 0
            mm_reg_write.next = False
            mm_transfer_size.next = transfer_size_type.WORD
        elif enable:
            mm_alu_result.next = mm_comb_alu_result
            mm_mem_read.next = mm_comb_mem_read
            mm_reg_d.next = mm_comb_reg_d
            mm_reg_write.next = mm_comb_reg_write
            mm_transfer_size.next = mm_comb_transfer_size
        #if dmem_ena_out:
            #if dmem_we_out:
                #print 'write {0:b} {1:x} <- {2:x}'.format(
                #int(dmem_sel_out),
                #int(dmem_addr_out),
                #int(dmem_data_out))
            #else:
                #print 'read {0:b} {1:x}'.format(
                #int(dmem_sel_out),
                #int(dmem_addr_out),)
 
 
    return instances()
 
if __name__ == '__main__':
    clock = Signal(False)
    reset = Signal(False)
    enable = Signal(False)
 
    ex_alu_result = Signal(intbv(0)[32:])
    ex_reg_d = Signal(intbv(0)[5:])
    ex_reg_write = Signal(False)
    ex_branch = Signal(False)
    ex_dat_d = Signal(intbv(0)[32:])
    ex_mem_read = Signal(False)
    ex_mem_write = Signal(False)
    ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])
    ex_transfer_size = Signal(transfer_size_type.WORD)
    mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])
    mm_mem_read = Signal(False)
    mm_reg_d = Signal(intbv(0)[5:])
    mm_reg_write = Signal(False)
    mm_transfer_size = Signal(transfer_size_type.WORD)
    dmem_data_out = Signal(intbv(0)[32:])
    dmem_sel_out = Signal(intbv(0)[4:])
    dmem_we_out = Signal(False)
    dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])
    dmem_ena_out = Signal(False)
 
    args = [
        MemUnit,
        # Inputs
        clock,
        reset,
        enable,
        ex_alu_result,
        ex_reg_d,
        ex_reg_write,
        ex_branch,
        ex_dat_d,
        ex_mem_read,
        ex_mem_write,
        ex_program_counter,
        ex_transfer_size,
        # Outputs
        mm_alu_result,
        mm_mem_read,
        mm_reg_d,
        mm_reg_write,
        mm_transfer_size,
        dmem_data_out,
        dmem_sel_out,
        dmem_we_out,
        dmem_addr_out,
        dmem_ena_out,
    ]
    toVHDL(*args)
    toVerilog(*args)
 
### EOF ###
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
 

Line No.	Rev	Author	Line
1	2	rockee	`# -- coding: utf-8 --`
2			`"""`
3			`memory.py`
4			`=========`
5
6			`Memory Stage`
7
8	5	rockee	`:copyright: Copyright (c) 2010 Jian Luo`
9			`:author-email: jian.luo.cn(at_)gmail.com`
10			`:license: LGPL, see LICENSE for details`
11	2	rockee	`:revision: $Id: memory.py 5 2010-11-21 10:59:30Z rockee $`
12			`"""`
13
14			`from myhdl import *`
15			`from defines import *`
16			`from functions import *`
17
18			`def MemUnit(`
19			`# Inputs`
20			`clock,`
21			`reset,`
22			`enable,`
23			`ex_alu_result,`
24			`ex_reg_d,`
25			`ex_reg_write,`
26			`ex_branch,`
27			`ex_dat_d,`
28			`ex_mem_read,`
29			`ex_mem_write,`
30			`ex_program_counter,`
31			`ex_transfer_size,`
32			`# Outputs`
33			`mm_alu_result,`
34			`mm_mem_read,`
35			`mm_reg_d,`
36			`mm_reg_write,`
37			`mm_transfer_size,`
38			`dmem_data_out,`
39			`dmem_sel_out,`
40			`dmem_we_out,`
41			`dmem_addr_out,`
42			`dmem_ena_out,`
43			`):`
44			`"""`
45			`"""`
46			`mem_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])`
47
48			`mm_comb_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])`
49			`mm_comb_mem_read = Signal(False)`
50			`mm_comb_reg_d = Signal(intbv(0)[5:])`
51			`mm_comb_reg_write = Signal(False)`
52			`mm_comb_transfer_size = Signal(transfer_size_type.WORD)`
53
54			`@always_comb`
55			`def comb():`
56			`# Local Variables`
57			`alu_result = intbv(0)[CFG_DMEM_WIDTH:]`
58
59			`if ex_branch:`
60			`alu_result[:] = ex_program_counter`
61			`else:`
62			`alu_result[:] = ex_alu_result`
63
64			`# TODO: forwarding`
65			`mem_result.next = ex_dat_d`
66
67			`# pipelining`
68			`mm_comb_alu_result.next = alu_result`
69			`mm_comb_mem_read.next = ex_mem_read`
70			`mm_comb_reg_d.next = ex_reg_d`
71			`mm_comb_reg_write.next = ex_reg_write`
72			`mm_comb_transfer_size.next = ex_transfer_size`
73
74			`@always_comb`
75			`def control_dmem():`
76			`dmem_data_out.next = mem_result`
77			`dmem_sel_out.next = decode_mem_store(ex_alu_result[2:],ex_transfer_size)`
78			`dmem_we_out.next = ex_mem_write`
79			`dmem_addr_out.next = ex_alu_result[CFG_DMEM_SIZE:]`
80			`dmem_ena_out.next = ex_mem_write or ex_mem_read`
81
82			`@always(clock.posedge)`
83			`def seq():`
84			`if reset:`
85			`mm_alu_result.next = 0`
86			`mm_mem_read.next = False`
87			`mm_reg_d.next = 0`
88			`mm_reg_write.next = False`
89			`mm_transfer_size.next = transfer_size_type.WORD`
90			`elif enable:`
91			`mm_alu_result.next = mm_comb_alu_result`
92			`mm_mem_read.next = mm_comb_mem_read`
93			`mm_reg_d.next = mm_comb_reg_d`
94			`mm_reg_write.next = mm_comb_reg_write`
95			`mm_transfer_size.next = mm_comb_transfer_size`
96			`#if dmem_ena_out:`
97			`#if dmem_we_out:`
98			`#print 'write {0:b} {1:x} <- {2:x}'.format(`
99			`#int(dmem_sel_out),`
100			`#int(dmem_addr_out),`
101			`#int(dmem_data_out))`
102			`#else:`
103			`#print 'read {0:b} {1:x}'.format(`
104			`#int(dmem_sel_out),`
105			`#int(dmem_addr_out),)`
106
107
108			`return instances()`
109
110			`if __name__ == '__main__':`
111			`clock = Signal(False)`
112			`reset = Signal(False)`
113			`enable = Signal(False)`
114
115			`ex_alu_result = Signal(intbv(0)[32:])`
116			`ex_reg_d = Signal(intbv(0)[5:])`
117			`ex_reg_write = Signal(False)`
118			`ex_branch = Signal(False)`
119			`ex_dat_d = Signal(intbv(0)[32:])`
120			`ex_mem_read = Signal(False)`
121			`ex_mem_write = Signal(False)`
122			`ex_program_counter = Signal(intbv(0)[CFG_IMEM_SIZE:])`
123			`ex_transfer_size = Signal(transfer_size_type.WORD)`
124			`mm_alu_result = Signal(intbv(0)[CFG_DMEM_WIDTH:])`
125			`mm_mem_read = Signal(False)`
126			`mm_reg_d = Signal(intbv(0)[5:])`
127			`mm_reg_write = Signal(False)`
128			`mm_transfer_size = Signal(transfer_size_type.WORD)`
129			`dmem_data_out = Signal(intbv(0)[32:])`
130			`dmem_sel_out = Signal(intbv(0)[4:])`
131			`dmem_we_out = Signal(False)`
132			`dmem_addr_out = Signal(intbv(0)[CFG_DMEM_SIZE:])`
133			`dmem_ena_out = Signal(False)`
134
135			`args = [`
136			`MemUnit,`
137			`# Inputs`
138			`clock,`
139			`reset,`
140			`enable,`
141			`ex_alu_result,`
142			`ex_reg_d,`
143			`ex_reg_write,`
144			`ex_branch,`
145			`ex_dat_d,`
146			`ex_mem_read,`
147			`ex_mem_write,`
148			`ex_program_counter,`
149			`ex_transfer_size,`
150			`# Outputs`
151			`mm_alu_result,`
152			`mm_mem_read,`
153			`mm_reg_d,`
154			`mm_reg_write,`
155			`mm_transfer_size,`
156			`dmem_data_out,`
157			`dmem_sel_out,`
158			`dmem_we_out,`
159			`dmem_addr_out,`
160			`dmem_ena_out,`
161			`]`
162			`toVHDL(*args)`
163			`toVerilog(*args)`
164
165			`### EOF ###`
166			`# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:`
167

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[/] [myblaze/] [trunk/] [rtl/] [memory.py] - Blame information for rev 5