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Release 10.1.03 par K.39 (lin64)

Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

jami::  Sun Nov 21 23:39:05 2010

par -w -intstyle ise -ol std -t 1 SysTop_map.ncd SysTop.ncd SysTop.pcf

Constraints file: SysTop.pcf.

Loading device for application Rf_Device from file '3s500e.nph' in environment

/home/daniel/Applications/Xilinx/10.1/ISE.

   "SysTop" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

Device speed data version:  "PRODUCTION 1.27 2008-01-09".

Design Summary Report:

 Number of External IOBs                          13 out of 232     5%

   Number of External Input IOBs                  3

      Number of External Input IBUFs              3

        Number of LOCed External Input IBUFs      3 out of 3     100%

   Number of External Output IOBs                10

      Number of External Output IOBs             10

        Number of LOCed External Output IOBs      9 out of 10     90%

   Number of External Bidir IOBs                  0

   Number of BUFGMUXs                        1 out of 24      4%

   Number of RAMB16s                        11 out of 20     55%

   Number of Slices                        702 out of 4656   15%

      Number of SLICEMs                      0 out of 2328    0%

Overall effort level (-ol):   Standard

Placer effort level (-pl):    High

Placer cost table entry (-t): 1

Router effort level (-rl):    Standard

Starting initial Timing Analysis.  REAL time: 1 secs

Finished initial Timing Analysis.  REAL time: 1 secs

WARNING:Par:288 - The signal rxd_line_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer

Phase 1.1

Phase 1.1 (Checksum:4fe77) REAL time: 2 secs

Phase 2.7

INFO:Place:834 - Only a subset of IOs are locked. Out of 10 IOs, 9 are locked and 1 are not locked. If you would like to

   print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.

Phase 2.7 (Checksum:4fe77) REAL time: 2 secs

Phase 3.31

Phase 3.31 (Checksum:4fe77) REAL time: 2 secs

Phase 4.2

...

......

Phase 4.2 (Checksum:50e94) REAL time: 2 secs

Phase 5.30

Phase 5.30 (Checksum:50e94) REAL time: 2 secs

Phase 6.3

...

Phase 6.3 (Checksum:50f8b) REAL time: 2 secs

Phase 7.5

Phase 7.5 (Checksum:50f8b) REAL time: 2 secs

Phase 8.8

......................

.......

.....

Phase 8.8 (Checksum:405439) REAL time: 7 secs

Phase 9.5

Phase 9.5 (Checksum:405439) REAL time: 7 secs

Phase 10.18

Phase 10.18 (Checksum:410575) REAL time: 10 secs

Phase 11.5

Phase 11.5 (Checksum:410575) REAL time: 10 secs

REAL time consumed by placer: 10 secs

CPU  time consumed by placer: 10 secs

Writing design to file SysTop.ncd

Total REAL time to Placer completion: 10 secs

Total CPU time to Placer completion: 10 secs

Starting Router

Phase 1: 5979 unrouted;       REAL time: 12 secs

Phase 2: 5657 unrouted;       REAL time: 12 secs

Phase 3: 1686 unrouted;       REAL time: 13 secs

Phase 4: 1686 unrouted; (0)      REAL time: 13 secs

Phase 5: 1686 unrouted; (0)      REAL time: 13 secs

Phase 6: 1686 unrouted; (0)      REAL time: 13 secs

Phase 7: 0 unrouted; (0)      REAL time: 14 secs

Phase 8: 0 unrouted; (0)      REAL time: 14 secs

Phase 9: 0 unrouted; (0)      REAL time: 15 secs

Total REAL time to Router completion: 15 secs

Total CPU time to Router completion: 15 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|         clock_BUFGP | BUFGMUX_X1Y11| No   |  290 |  0.084     |  0.204      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------

  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing

                                            |         |    Slack   | Achievable | Errors |    Score

------------------------------------------------------------------------------------------------------

  TS_clock = PERIOD TIMEGRP "clock" 20 ns H | SETUP   |     2.033ns|    17.967ns|       0|           0

  IGH 50%                                   | HOLD    |     0.595ns|            |       0|           0

------------------------------------------------------------------------------------------------------

All constraints were met.

Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 16 secs

Total CPU time to PAR completion: 16 secs

Peak Memory Usage:  372 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Timing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 3

Number of info messages: 1

Writing design to file SysTop.ncd

PAR done!