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-- File: generated/lfsr_768.vhd
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-- Generated by MyHDL 0.9.0
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-- Date: Thu Jan 11 17:29:05 2018
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_090.all;
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entity lfsr_768 is
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port (
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reset: in std_logic;
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clock: in std_logic;
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lfsr_out: out unsigned(767 downto 0)
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);
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end entity lfsr_768;
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architecture MyHDL of lfsr_768 is
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signal reg_internal: unsigned(767 downto 0);
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begin
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LFSR_768_LFSR_LOGIC: process (clock, reset) is
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begin
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if (reset = '1') then
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reg_internal <= unsigned'"000111010100001110100000101001100101100100010101001001010000110011010101001111011110101110111000011110011100101100001000100100101101111111000101101100111011100011110001101000100011110101010001111011010011101100011101100110101111100110111111001000001011110000001111010100010101001101011111101010110011001011100100111111001110001000101000001010000010111011000010011001110110110111011000110100101010011011010110101101111010010011110011011110100100010000000110010000010101011000011011110000000011011010110010001101001001111100001111110001001000010000000111011001010000110111000001010011111011011101010011110111000010101101001110010111010010011100100001110100101101000101011000011001010101110111010000001000010010101010111010000101001110000011010111010010010111101111111001";
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elsif rising_edge(clock) then
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if (reg_internal(0) = '1') then
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reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("100010000000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));
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else
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reg_internal <= shift_right(reg_internal, 1);
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end if;
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end if;
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end process LFSR_768_LFSR_LOGIC;
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lfsr_out <= reg_internal;
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end architecture MyHDL;
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