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-- Company: RIIC

-- Engineer: Gerhard Hohner Mat.nr.: 7555111

-- 

-- Create Date:    01/07/2004 

-- Design Name:    Diplomarbeit

-- Module Name:    MYCPU - Rtl 

-- Project Name:   32 bit FORTH processor

-- Target Devices: Spartan 3

-- Tool versions:  ISE 8.2

-- Description: contains declarations valid for every source

-- Dependencies: none

-- 

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

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library IEEE;

use IEEE.std_logic_1164.all;

--use IEEE.numeric_std.all;

use IEEE.std_logic_arith.all;

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package Global is

function To_Integer(Arg : in std_ulogic_vector) return integer;

function To_Integer(Arg : in std_ulogic) return integer;

function TO_UNSIGNED (ARG, SIZE: natural) return UNSIGNED;

subtype RAMrange     is natural range 25 downto 0; -- 64MB as example MUST BE REDEFINED !!!

end Global;

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package body Global is

function To_Integer(Arg : in std_ulogic) return integer is

begin

  return CONV_INTEGER(Arg);

end;

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function To_Integer(Arg : in std_ulogic_vector) return integer is

begin

 return CONV_INTEGER(unsigned(Arg));

end;

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  function TO_UNSIGNED (ARG, SIZE: natural) return UNSIGNED is

    variable RESULT: UNSIGNED(SIZE-1 downto 0);

    variable I_VAL: NATURAL := ARG;

  begin

    for I in 0 to RESULT'LEFT loop

      if (I_VAL mod 2) = 0 then

        RESULT(I) := '0';

      else RESULT(I) := '1';

      end if;

      I_VAL := I_VAL/2;

    end loop;

    return RESULT;

  end TO_UNSIGNED;

end Global;

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