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-- Title                                                        : ONFI compliant NAND interface
-- File                                                 : nand_master.vhd
-- Author                                               : Alexey Lyashko <pradd@opencores.org>
-- License                                              : LGPL
-------------------------------------------------------------------------------------------------
-- Description:
-- The nand_master entity is the topmost entity of this ONFi (Open NAND Flash interface <http://www.onfi.org>)
-- compliant NAND flash controller. It provides very simple interface and short and easy to use
-- set of commands.
-- It is important to mention, that the controller takes care of delays and proper NAND command
-- sequences. See documentation for further details.
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.onfi.all;
 
entity nand_master is
        port
        (
                -- System clock
                clk                                     : in    std_logic;
                enable                          : in    std_logic;
                -- NAND chip control hardware interface. These signals should be bound to physical pins.
                nand_cle                                : out   std_logic := '0';
                nand_ale                                : out   std_logic := '0';
                nand_nwe                                : out   std_logic := '1';
                nand_nwp                                : out   std_logic := '0';
                nand_nce                                : out   std_logic := '1';
                nand_nre                                : out std_logic := '1';
                nand_rnb                                : in    std_logic;
                -- NAND chip data hardware interface. These signals should be boiund to physical pins.
                nand_data                       : inout std_logic_vector(15 downto 0);
 
                -- Component interface
                nreset                          : in    std_logic;
                data_out                                : out   std_logic_vector(7 downto 0);
                data_in                         : in    std_logic_vector(7 downto 0);
                busy                                    : out   std_logic := '0';
                activate                                : in    std_logic;
                cmd_in                          : in    std_logic_vector(7 downto 0)
        );
end nand_master;
 
-- Structural architecture of the NAND_MASTER component.
architecture struct of nand_master is
        -- Latch Unit.
        -- This component implements NAND's address and command latch interfaces.
        component latch_unit
                generic(latch_type : latch_t);
                port(
                        activate,
                        clk : in std_logic;
                        data_in : in std_logic_vector(15 downto 0);
                        latch_ctrl,
                        write_enable,
                        busy : out std_logic;
                        data_out : out std_logic_vector(15 downto 0)
                );
        end component;
 
        -- Latch unit related signals
        signal cle_activate                     :       std_logic;
        signal cle_latch_ctrl           :       std_logic;
        signal cle_write_enable         :       std_logic;
        signal cle_busy                         :       std_logic;
        signal cle_data_in                      :       std_logic_vector(15 downto 0);
        signal cle_data_out                     :       std_logic_vector(15 downto 0);
 
        signal ale_activate                     :       std_logic;
        signal ale_latch_ctrl           :       std_logic;
        signal ale_write_enable         :       std_logic;
        signal ale_busy                         :       std_logic;
        signal ale_data_in                      :       std_logic_vector(15 downto 0);
        signal ale_data_out                     :       std_logic_vector(15 downto 0);
 
        -- IO Unit.
        -- This component implements NAND's read/write interfaces.
        component io_unit
                generic (io_type : io_t);
                port(
                        activate,
                        clk : in std_logic;
                        data_in : in std_logic_vector(15 downto 0);
                        io_ctrl,
                        busy : out std_logic;
                        data_out : out std_logic_vector(15 downto 0)
                );
        end component;
 
        -- IO Unit related signals
        signal io_rd_activate           :       std_logic;
        signal io_rd_io_ctrl                    :       std_logic;
        signal io_rd_busy                               :       std_logic;
        signal io_rd_data_in                    :       std_logic_vector(15 downto 0);
        signal io_rd_data_out           :       std_logic_vector(15 downto 0);
 
        signal io_wr_activate           :       std_logic;
        signal io_wr_io_ctrl                    :       std_logic;
        signal io_wr_busy                               :       std_logic;
        signal io_wr_data_in                    :       std_logic_vector(15 downto 0);
        signal io_wr_data_out           :       std_logic_vector(15 downto 0);
 
        -- FSM
        signal state                                    :       master_state_t  := M_RESET;
        signal n_state                                  :       master_state_t := M_RESET;
        signal substate                         :       master_substate_t       := MS_BEGIN;
        signal n_substate                               :       master_substate_t := MS_BEGIN;
 
        signal delay                                    :       integer := 0;
 
        signal byte_count                               :       integer := 0;
        signal page_idx                         :       integer := 0;
        signal page_data                                :       page_t;
        signal page_param                               :       param_page_t;
        signal chip_id                                  :       nand_id_t;
        signal current_address          :       nand_address_t;
        signal data_bytes_per_page      :       integer;
        signal oob_bytes_per_page       :       integer;
        signal addr_cycles                      :       integer;
        signal state_switch                     :       states_t        :=
                (
 
                        1       =>      M_NAND_RESET,
                        2       =>      M_NAND_READ_PARAM_PAGE,
                        3       =>      M_NAND_READ_ID,
                        4       =>      M_NAND_BLOCK_ERASE,
                        5       =>      M_NAND_READ_STATUS,
                        6       =>      M_NAND_READ,
                        7       =>      M_NAND_PAGE_PROGRAM,
                        8       =>      MI_GET_STATUS,
                        9       =>      MI_CHIP_ENABLE,
                        10      =>      MI_CHIP_DISABLE,
                        11      =>      MI_WRITE_PROTECT,
                        12      =>      MI_WRITE_ENABLE,
                        13      =>      MI_RESET_INDEX,
                        14      =>      MI_GET_ID_BYTE,
                        15      =>      MI_GET_PARAM_PAGE_BYTE,
                        16      =>      MI_GET_DATA_PAGE_BYTE,
                        17      =>      MI_SET_DATA_PAGE_BYTE,
                        18      =>      MI_GET_CURRENT_ADDRESS_BYTE,
                        19      =>      MI_SET_CURRENT_ADDRESS_BYTE,
                        others => M_IDLE
                );
 
--      The following is a sort of a status register. Bit set to 1 means TRUE, bit set to 0 means FALSE:
--      0 - is ONFI compliant
--      1 - bus width (0 - x8 / 1 - x16)
--      2 - is chip enabled
--      3 - is chip write protected
--      4 - array pointer out of bounds
--      5 - 
--      6 - 
--      7 - 
        signal status                                   :       std_logic_vector(7 downto 0) := x"00";
begin
 
        -- Asynchronous command latch interface.
        ACL: latch_unit
        generic map (latch_type => LATCH_CMD)
        port map
        (
                activate => cle_activate,
                latch_ctrl => cle_latch_ctrl,
                write_enable => cle_write_enable,
                busy => cle_busy,
                clk => clk,
                data_in => cle_data_in,
                data_out => cle_data_out
        );
 
        -- Asynchronous address latch interface.
        AAL: latch_unit
        generic map (latch_type => LATCH_ADDR)
        port map
        (
                activate => ale_activate,
                latch_ctrl => ale_latch_ctrl,
                write_enable => ale_write_enable,
                busy => ale_busy,
                clk => clk,
                data_in => ale_data_in,
                data_out => ale_data_out
        );
 
        -- Output to NAND
        IO_WR: io_unit
        generic map (io_type => IO_WRITE)
        port map
        (
                clk => clk,
                activate => io_wr_activate,
                data_in => io_wr_data_in,
                data_out => io_wr_data_out,
                io_ctrl => io_wr_io_ctrl,
                busy => io_wr_busy
        );
 
        -- Input from NAND
        IO_RD: io_unit
        generic map (io_type => IO_READ)
        port map
        (
                clk => clk,
                activate => io_rd_activate,
                data_in => io_rd_data_in,
                data_out => io_rd_data_out,
                io_ctrl => io_rd_io_ctrl,
                busy => io_rd_busy
        );
 
        -- Busy indicator
        busy    <= '0'   when state = M_IDLE else
                                '1';
 
        -- Bidirection NAND data interface.
        --nand_data     <=      (cle_data_out or ale_data_out or io_wr_data_out) when (cle_busy or ale_busy or io_wr_busy) = '1' else x"ZZZZ";
        nand_data       <=      cle_data_out when cle_busy = '1' else
                                                ale_data_out when ale_busy = '1' else
                                                io_wr_data_out when io_wr_busy = '1' else
                                                "ZZZZZZZZZZZZZZZZ";
        io_rd_data_in   <=      nand_data;
 
        -- Command Latch Enable
        nand_cle                <= cle_latch_ctrl;
 
        -- Address Latch Enable
        nand_ale                <= ale_latch_ctrl;
 
        -- Write Enable
        nand_nwe                <=      cle_write_enable and ale_write_enable and io_wr_io_ctrl;
 
        -- Read Enable
        nand_nre                <= io_rd_io_ctrl;
 
        -- Activation of command latch unit
        cle_activate    <=      '1'     when    state = M_NAND_RESET or                                                                                                                                                 -- initiate submission of RESET command
                                                                                        (state = M_NAND_READ_PARAM_PAGE and substate = MS_BEGIN) or                                                     -- initiate submission of READ PARAMETER PAGE command
                                                                                        (state = M_NAND_BLOCK_ERASE and substate = MS_BEGIN) or                                                         -- initiate submission of BLOCK ERASE command
                                                                                        (state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND1) or                                       -- initiate submission of BLOCK ERASE 2 command
                                                                                        (state = M_NAND_READ_STATUS and substate = MS_BEGIN) or                                                         -- initiate submission of READ STATUS command
                                                                                        (state = M_NAND_READ and substate = MS_BEGIN) or                                                                                -- initiate read mode for READ command
                                                                                        (state = M_NAND_READ and substate = MS_SUBMIT_COMMAND1) or                                                      -- initiate submission of READ command
                                                                                        (state = M_NAND_PAGE_PROGRAM and substate = MS_BEGIN) or                                                                -- initiate write mode for PAGE PROGRAM command
                                                                                        (state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_COMMAND1) or                              -- initiate submission for PAGE PROGRAM command
                                                                                        (state = M_NAND_READ_ID and substate = MS_BEGIN) else                                                                   -- initiate submission of READ ID command
                                                        '0';
 
        -- Activation of address latch unit
        ale_activate    <=      '1'     when    (state = M_NAND_READ_PARAM_PAGE and substate = MS_SUBMIT_COMMAND) or                            -- initiate address submission for READ PARAMETER PAGE command
                                                                                        (state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND) or                                        -- initiate address submission for BLOCK ERASE command
                                                                                        (state = M_NAND_READ and substate = MS_SUBMIT_COMMAND) or                                                       -- initiate address submission for READ command
                                                                                        (state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_ADDRESS) or                                       -- initiate address submission for PAGE PROGRAM command
                                                                                        (state = M_NAND_READ_ID and substate = MS_SUBMIT_COMMAND) else                                          -- initiate address submission for READ ID command
                                                        '0';
 
        -- Activation of read byte mechanism
        io_rd_activate  <=      '1'     when    (state = M_NAND_READ_PARAM_PAGE and substate = MS_READ_DATA0) or                                        -- initiate byte read for READ PARAMETER PAGE command
                                                                                        (state = M_NAND_READ_STATUS and substate = MS_READ_DATA0) or                                            -- initiate byte read for READ STATUS command
                                                                                        (state = M_NAND_READ and substate = MS_READ_DATA0) or                                                                   -- initiate byte read for READ command
                                                                                        (state = M_NAND_READ_ID and substate = MS_READ_DATA0) else                                                      -- initiate byte read for READ ID command
                                                        '0';
 
        -- Activation of write byte mechanism
        io_wr_activate  <=      '1'     when    (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3)     else                                    -- initiate byte write for PAGE_PROGRAM command
                                                        '0';
 
        MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)
                variable tmp_int                :       std_logic_vector(31 downto 0);
                variable tmp                    :       integer;
        begin
                if(nreset = '0')then
                        state                                                   <= M_RESET;
 
--              elsif(activate = '1')then
--                      state                                                   <= state_switch(to_integer(unsigned(cmd_in)));
 
                elsif(rising_edge(clk) and enable = '0')then
                        case state is
                                -- RESET state. Speaks for itself
                                when M_RESET =>
                                        state                                   <= M_IDLE;
                                        substate                                <= MS_BEGIN;
                                        delay                                   <= 0;
                                        byte_count                      <= 0;
                                        page_idx                                <= 0;
                                        current_address(0)<= x"00";
                                        current_address(1)<= x"00";
                                        current_address(2)<= x"00";
                                        current_address(3)<= x"00";
                                        current_address(4)<= x"00";
                                        data_bytes_per_page     <= 0;
                                        oob_bytes_per_page      <= 0;
                                        addr_cycles                     <= 0;
                                        status                          <= x"08";               -- We start write protected!
                                        nand_nce                                <= '1';
                                        nand_nwp                                <= '0';
 
                                -- This is in fact a command interpreter
                                when M_IDLE =>
                                        if(activate = '1')then
                                                state                           <= state_switch(to_integer(unsigned(cmd_in)));
                                        end if;
 
                                -- Reset the NAND chip
                                when M_NAND_RESET =>
                                        cle_data_in                     <= x"00ff";
                                        state                                   <= M_WAIT;
                                        n_state                         <= M_IDLE;
                                        delay                                   <= t_wb + 8;
 
                                -- Read the status register of the controller
                                when MI_GET_STATUS =>
                                        data_out                                <= status;
                                        state                                   <= M_IDLE;
 
                                -- Set CE# to '0' (enable NAND chip)
                                when MI_CHIP_ENABLE =>
                                        nand_nce                                <= '0';
                                        state                                   <= M_IDLE;
                                        status(2)                       <= '1';
 
                                -- Set CE# to '1' (disable NAND chip)
                                when MI_CHIP_DISABLE =>
                                        nand_nce                                <= '1';
                                        state                                   <= M_IDLE;
                                        status(2)                       <= '0';
 
                                -- Set WP# to '0' (enable write protection)
                                when MI_WRITE_PROTECT =>
                                        nand_nwp                                <= '0';
                                        status(3)                       <= '1';
                                        state                                   <= M_IDLE;
 
                                -- Set WP# to '1' (disable write protection)
                                -- By default, this controller has WP# set to 0 on reset
                                when MI_WRITE_ENABLE =>
                                        nand_nwp                                <= '1';
                                        status(3)                       <= '0';
                                        state                                   <= M_IDLE;
 
                                -- Reset the index register.
                                -- Index register holds offsets into JEDEC ID, Parameter Page buffer or Data Page buffer depending on
                                -- the operation being performed
                                when MI_RESET_INDEX =>
                                        page_idx                                <= 0;
                                        state                                   <= M_IDLE;
 
                                -- Read 1 byte from JEDEC ID and increment the index register.
                                -- If the value points outside the 5 byte JEDEC ID array, 
                                -- the register is reset to 0 and bit 4 of the status register
                                -- is set to '1'
                                when MI_GET_ID_BYTE =>
                                        if(page_idx < 5)then
                                                data_out                                <= chip_id(page_idx);
                                                page_idx                                <= page_idx + 1;
                                                status(4)                       <= '0';
                                        else
                                                data_out                                <= x"00";
                                                page_idx                                <= 0;
                                                status(4)                       <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Read 1 byte from 256 bytes buffer that holds the Parameter Page.
                                -- If the value goes beyond 255, then the register is reset and 
                                -- bit 4 of the status register is set to '1'
                                when MI_GET_PARAM_PAGE_BYTE =>
                                        if(page_idx < 256)then
                                                data_out                                <= page_param(page_idx);
                                                page_idx                                <= page_idx + 1;
                                                status(4)                       <= '0';
                                        else
                                                data_out                                <= x"00";
                                                page_idx                                <= 0;
                                                status(4)                       <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Read 1 byte from the buffer that holds the content of last read 
                                -- page. The limit is variable and depends on the values in 
                                -- the Parameter Page. In case the index register points beyond 
                                -- valid page content, its value is reset and bit 4 of the status
                                -- register is set to '1'
                                when MI_GET_DATA_PAGE_BYTE =>
                                        if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
                                                data_out                                <= page_data(page_idx);
                                                page_idx                                <= page_idx + 1;
                                                status(4)                       <= '0';
                                        else
                                                data_out                                <= x"00";
                                                page_idx                                <= 0;
                                                status(4)                       <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Write 1 byte into the Data Page buffer at offset specified by
                                -- the index register. If the value of the index register points 
                                -- beyond valid page content, its value is reset and bit 4 of
                                -- the status register is set to '1'
                                when MI_SET_DATA_PAGE_BYTE =>
                                        if(page_idx < data_bytes_per_page + oob_bytes_per_page)then
                                                page_data(page_idx)     <= data_in;
                                                page_idx                                        <= page_idx + 1;
                                                status(4)                               <= '0';
                                        else
                                                page_idx                                        <= 0;
                                                status(4)                               <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Gets the address byte specified by the index register. Bit 4 
                                -- of the status register is set to '1' if the value of the index 
                                -- register points beyond valid address data and the value of 
                                -- the index register is reset
                                when MI_GET_CURRENT_ADDRESS_BYTE =>
                                        if(page_idx < addr_cycles)then
                                                data_out                                        <= current_address(page_idx);
                                                page_idx                                        <= page_idx + 1;
                                                status(4)                               <= '0';
                                        else
                                                page_idx                                        <= 0;
                                                status(4)                               <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Sets the value of the address byte specified by the index register.Bit 4 
                                -- of the status register is set to '1' if the value of the index 
                                -- register points beyond valid address data and the value of 
                                -- the index register is reset
                                when MI_SET_CURRENT_ADDRESS_BYTE =>
                                        if(page_idx < addr_cycles)then
                                                current_address(page_idx) <= data_in;
                                                page_idx                                        <= page_idx + 1;
                                                status(4)                               <= '0';
                                        else
                                                page_idx                                        <= 0;
                                                status(4)                               <= '1';
                                        end if;
                                        state                                           <= M_IDLE;
 
                                -- Program one page.
                                when M_NAND_PAGE_PROGRAM =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"0080";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                   <= M_WAIT;
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
                                                byte_count              <= 0;
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                byte_count              <= byte_count + 1;
                                                ale_data_in             <= x"00"&current_address(byte_count);
                                                substate                        <= MS_SUBMIT_ADDRESS;
 
                                        elsif(substate = MS_SUBMIT_ADDRESS)then
                                                if(byte_count < addr_cycles)then
                                                        substate                <= MS_SUBMIT_COMMAND;
                                                else
                                                        substate                <= MS_WRITE_DATA0;
                                                end if;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
 
                                        elsif(substate = MS_WRITE_DATA0)then
                                                delay                           <= t_adl;
                                                state                           <= M_DELAY;
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
                                                substate                        <=      MS_WRITE_DATA1;
                                                page_idx                        <= 0;
                                                byte_count              <= 0;
 
                                        elsif(substate = MS_WRITE_DATA1)then
                                                byte_count              <= byte_count + 1;
                                                page_idx                        <= page_idx + 1;
                                                io_wr_data_in   <= x"00"&page_data(page_idx);
                                                if(status(1) = '0')then
                                                        substate                <= MS_WRITE_DATA3;
                                                else
                                                        substate                <= MS_WRITE_DATA2;
                                                end if;
 
                                        elsif(substate = MS_WRITE_DATA2)then
                                                page_idx                        <= page_idx + 1;
                                                io_wr_data_in(15 downto 8) <= page_data(page_idx);
                                                substate                        <= MS_WRITE_DATA3;
 
                                        elsif(substate = MS_WRITE_DATA3)then
                                                if(byte_count < data_bytes_per_page + oob_bytes_per_page)then
                                                        substate                <= MS_WRITE_DATA1;
                                                else
                                                        substate                <= MS_SUBMIT_COMMAND1;
                                                end if;
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
                                                state                           <= M_WAIT;
 
                                        elsif(substate = MS_SUBMIT_COMMAND1)then
                                                cle_data_in             <= x"0010";
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
                                                state                           <= M_WAIT;
                                                substate                        <= MS_WAIT;
 
                                        elsif(substate = MS_WAIT)then
                                                delay                           <= t_wb + t_prog;
                                                state                           <= M_DELAY;
                                                n_state                 <= M_NAND_PAGE_PROGRAM;
                                                substate                        <= MS_END;
                                                byte_count              <= 0;
                                                page_idx                        <= 0;
 
                                        elsif(substate = MS_END)then
                                                state                           <= M_WAIT;
                                                n_state                 <= M_IDLE;
                                                substate                        <= MS_BEGIN;
                                        end if;
 
 
                                -- Reads single page into the buffer.
                                when M_NAND_READ =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"0000";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ;
                                                byte_count              <= 0;
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                byte_count              <= byte_count + 1;
                                                ale_data_in             <= x"00"&current_address(byte_count);
                                                substate                        <= MS_SUBMIT_ADDRESS;
 
                                        elsif(substate = MS_SUBMIT_ADDRESS)then
                                                if(byte_count < addr_cycles)then
                                                        substate                <= MS_SUBMIT_COMMAND;
                                                else
                                                        substate                <= MS_SUBMIT_COMMAND1;
                                                end if;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ;
 
                                        elsif(substate = MS_SUBMIT_COMMAND1)then
                                                cle_data_in             <= x"0030";
                                                substate                        <= MS_DELAY;
                                                state                   <= M_WAIT;
                                                n_state                 <= M_NAND_READ;
 
                                        elsif(substate = MS_DELAY)then
                                                delay                           <= t_wb;
                                                substate                        <= MS_READ_DATA0;
                                                state                           <= M_DELAY;
                                                n_state                 <= M_NAND_READ;
                                                byte_count              <= 0;
                                                page_idx                        <= 0;
 
                                        elsif(substate = MS_READ_DATA0)then
                                                byte_count              <= byte_count + 1;
                                                n_state                 <= M_NAND_READ;
                                                state                           <= M_WAIT;
                                                substate                        <= MS_READ_DATA1;
 
                                        elsif(substate = MS_READ_DATA1)then
                                                page_data(page_idx)     <= io_rd_data_out(7 downto 0);
                                                page_idx                        <= page_idx + 1;
                                                if(byte_count = data_bytes_per_page + oob_bytes_per_page and status(1) = '0')then
                                                        substate                <= MS_END;
                                                else
                                                        if(status(1) = '0')then
                                                                substate                <= MS_READ_DATA0;
                                                        else
                                                                substate                <= MS_READ_DATA2;
                                                        end if;
                                                end if;
 
                                        elsif(substate = MS_READ_DATA2)then
                                                page_idx                        <= page_idx + 1;
                                                page_data(page_idx)     <= io_rd_data_out(15 downto 8);
                                                if(byte_count = data_bytes_per_page + oob_bytes_per_page)then
                                                        substate                <= MS_END;
                                                else
                                                        substate                <= MS_READ_DATA0;
                                                end if;
 
                                        elsif(substate = MS_END)then
                                                substate                        <= MS_BEGIN;
                                                state                           <= M_IDLE;
                                                byte_count              <= 0;
                                        end if;
 
                                -- Read status byte
                                when M_NAND_READ_STATUS =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"0070";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ_STATUS;
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                delay                           <= t_whr;
                                                substate                        <= MS_READ_DATA0;
                                                state                           <= M_DELAY;
                                                n_state                 <= M_NAND_READ_STATUS;
 
                                        elsif(substate = MS_READ_DATA0)then
                                                substate                        <= MS_READ_DATA1;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ_STATUS;
 
                                        elsif(substate = MS_READ_DATA1)then                                             -- This is to make sure 'data_out' has valid data before 'busy' goes low.
                                                data_out                        <= io_rd_data_out(7 downto 0);
                                                state                           <= M_NAND_READ_STATUS;
                                                substate                        <= MS_END;
 
                                        elsif(substate = MS_END)then
                                                substate                        <= MS_BEGIN;
                                                state                           <= M_IDLE;
                                        end if;
 
                                -- Erase block specified by current_address
                                when M_NAND_BLOCK_ERASE =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"0060";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_BLOCK_ERASE;
                                                byte_count              <= 3;                                                   -- number of address bytes to submit
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                byte_count              <= byte_count - 1;
                                                ale_data_in(15 downto 8) <= x"00";
                                                ale_data_in(7 downto 0)  <= current_address(5 - byte_count);
                                                substate                        <= MS_SUBMIT_ADDRESS;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_BLOCK_ERASE;
 
                                        elsif(substate = MS_SUBMIT_ADDRESS)then
                                                if(0 < byte_count)then
                                                        substate                <= MS_SUBMIT_COMMAND;
                                                else
                                                        substate                <= MS_SUBMIT_COMMAND1;
                                                end if;
 
                                        elsif(substate = MS_SUBMIT_COMMAND1)then
                                                cle_data_in             <= x"00d0";
                                                substate                        <= MS_END;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_BLOCK_ERASE;
 
                                        elsif(substate = MS_END)then
                                                n_state                 <= M_IDLE;
                                                delay                   <= t_wb + t_bers;
                                                state                           <= M_DELAY;
                                                substate                        <= MS_BEGIN;
                                                byte_count              <= 0;
                                        end if;
 
                                -- Read NAND chip JEDEC ID
                                when M_NAND_READ_ID =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"0090";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                           <= M_WAIT;
                                                n_state                         <= M_NAND_READ_ID;
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                ale_data_in             <= X"0000";
                                                substate                        <= MS_SUBMIT_ADDRESS;
                                                state                   <= M_WAIT;
                                                n_state                 <= M_NAND_READ_ID;
 
                                        elsif(substate = MS_SUBMIT_ADDRESS)then
                                                delay                           <= t_wb;
                                                state                           <= M_DELAY;
                                                n_state                 <= M_NAND_READ_ID;
                                                substate                        <= MS_READ_DATA0;
                                                byte_count              <= 5;
                                                page_idx                        <= 0;
 
                                        elsif(substate = MS_READ_DATA0)then
                                                byte_count              <= byte_count - 1;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ_ID;
                                                substate                        <= MS_READ_DATA1;
 
                                        elsif(substate = MS_READ_DATA1)then
                                                chip_id(page_idx)       <= io_rd_data_out(7 downto 0);
                                                if(0 < byte_count)then
                                                        page_idx                                        <= page_idx + 1;
                                                        substate                                        <= MS_READ_DATA0;
                                                else
                                                        substate                                        <= MS_END;
                                                end if;
 
                                        elsif(substate = MS_END)then
                                                byte_count              <= 0;
                                                page_idx                        <= 0;
                                                substate                        <= MS_BEGIN;
                                                state                           <= M_IDLE;
                                        end if;
 
                                -- *data_in is assigned one clock cycle after *_activate is triggered!!!!
                                -- According to ONFI's timing diagrams this should be normal, but who knows...
                                when M_NAND_READ_PARAM_PAGE =>
                                        if(substate = MS_BEGIN)then
                                                cle_data_in             <= x"00ec";
                                                substate                        <= MS_SUBMIT_COMMAND;
                                                state                           <= M_WAIT;
                                                n_state                         <= M_NAND_READ_PARAM_PAGE;
 
                                        elsif(substate = MS_SUBMIT_COMMAND)then
                                                ale_data_in             <= X"0000";
                                                substate                        <= MS_SUBMIT_ADDRESS;
                                                state                   <= M_WAIT;
                                                n_state                 <= M_NAND_READ_PARAM_PAGE;
 
                                        elsif(substate = MS_SUBMIT_ADDRESS)then
                                                delay                           <= t_wb + t_rr;
                                                state                           <= M_WAIT;--M_DELAY;
                                                n_state                 <= M_NAND_READ_PARAM_PAGE;
                                                substate                        <= MS_READ_DATA0;
                                                byte_count              <= 256;
                                                page_idx                        <= 0;
 
                                        elsif(substate = MS_READ_DATA0)then
                                                byte_count              <= byte_count - 1;
                                                state                           <= M_WAIT;
                                                n_state                 <= M_NAND_READ_PARAM_PAGE;
                                                substate                        <= MS_READ_DATA1;
 
                                        elsif(substate = MS_READ_DATA1)then
                                                page_param(page_idx)    <= io_rd_data_out(7 downto 0);
                                                if(0 < byte_count)then
                                                        page_idx                                        <= page_idx + 1;
                                                        substate                                        <= MS_READ_DATA0;
                                                else
                                                        substate                                        <= MS_END;
                                                end if;
 
                                        elsif(substate = MS_END)then
                                                byte_count              <= 0;
                                                page_idx                        <= 0;
                                                substate                        <= MS_BEGIN;
                                                state                           <= M_IDLE;
 
                                                -- Check the chip for being ONFI compliant
                                                if(page_param(0) = x"4f" and page_param(1) = x"4e" and page_param(2) = x"46" and page_param(3) = x"49")then
                                                        -- Set status bit 0
                                                        status(0)                                        <= '1';
 
                                                        -- Bus width
                                                        status(1)                                       <= page_param(6)(0);
 
                                                        -- Setup counters:
                                                        -- Number of bytes per page
                                                        tmp_int                                         := page_param(83)&page_param(82)&page_param(81)&page_param(80);
                                                        data_bytes_per_page             <= to_integer(unsigned(tmp_int));
 
                                                        -- Number of spare bytes per page (OOB)
                                                        tmp_int                                         := "0000000000000000" & page_param(85) & page_param(84);
                                                        oob_bytes_per_page              <= to_integer(unsigned(tmp_int));
 
                                                        -- Number of address cycles
                                                        addr_cycles                                     <= to_integer(unsigned(page_param(101)(3 downto 0))) + to_integer(unsigned(page_param(101)(7 downto 4)));
                                                end if;
                                        end if;
 
                                -- Wait for latch and IO modules to become ready as well as for NAND's R/B# to be '1'
                                when M_WAIT =>
                                        if(delay > 1)then
                                                delay                           <= delay - 1;
                                        elsif('0' = (cle_busy or ale_busy or io_rd_busy or io_wr_busy or (not nand_rnb)))then
                                                state                           <= n_state;
                                        end if;
 
                                -- Simple delay mechanism
                                when M_DELAY =>
                                        if(delay > 1)then
                                                delay                   <= delay - 1;
                                        else
                                                state                           <= n_state;
                                        end if;
 
                                -- For just in case ("Shit happens..." (C) Forrest Gump)
                                when others =>
                                        state                           <= M_RESET;
                        end case;
                end if;
        end process;
end struct;
 

Line No.	Rev	Author	Line
1	9	pradd	`-------------------------------------------------------------------------------------------------`
2			`-------------------------------------------------------------------------------------------------`
3	10	pradd	`-- Title : ONFI compliant NAND interface`
4	9	pradd	`-- File : nand_master.vhd`
5			`-- Author : Alexey Lyashko <pradd@opencores.org>`
6			`-- License : LGPL`
7			`-------------------------------------------------------------------------------------------------`
8			`-- Description:`
9			`-- The nand_master entity is the topmost entity of this ONFi (Open NAND Flash interface <http://www.onfi.org>)`
10			`-- compliant NAND flash controller. It provides very simple interface and short and easy to use`
11			`-- set of commands.`
12			`-- It is important to mention, that the controller takes care of delays and proper NAND command`
13			`-- sequences. See documentation for further details.`
14			`-------------------------------------------------------------------------------------------------`
15			`-------------------------------------------------------------------------------------------------`
16
17
18
19			`library ieee;`
20			`use ieee.std_logic_1164.all;`
21			`use ieee.numeric_std.all;`
22			`use work.onfi.all;`
23
24			`entity nand_master is`
25			`port`
26			`(`
27			`-- System clock`
28			`clk : in std_logic;`
29	12	pradd	`enable : in std_logic;`
30	9	pradd	`-- NAND chip control hardware interface. These signals should be bound to physical pins.`
31			`nand_cle : out std_logic := '0';`
32			`nand_ale : out std_logic := '0';`
33			`nand_nwe : out std_logic := '1';`
34			`nand_nwp : out std_logic := '0';`
35			`nand_nce : out std_logic := '1';`
36			`nand_nre : out std_logic := '1';`
37			`nand_rnb : in std_logic;`
38			`-- NAND chip data hardware interface. These signals should be boiund to physical pins.`
39			`nand_data : inout std_logic_vector(15 downto 0);`
40
41			`-- Component interface`
42			`nreset : in std_logic;`
43			`data_out : out std_logic_vector(7 downto 0);`
44			`data_in : in std_logic_vector(7 downto 0);`
45			`busy : out std_logic := '0';`
46			`activate : in std_logic;`
47			`cmd_in : in std_logic_vector(7 downto 0)`
48			`);`
49			`end nand_master;`
50
51			`-- Structural architecture of the NAND_MASTER component.`
52			`architecture struct of nand_master is`
53			`-- Latch Unit.`
54			`-- This component implements NAND's address and command latch interfaces.`
55			`component latch_unit`
56			`generic(latch_type : latch_t);`
57			`port(`
58			`activate,`
59			`clk : in std_logic;`
60			`data_in : in std_logic_vector(15 downto 0);`
61			`latch_ctrl,`
62			`write_enable,`
63			`busy : out std_logic;`
64			`data_out : out std_logic_vector(15 downto 0)`
65			`);`
66			`end component;`
67
68			`-- Latch unit related signals`
69			`signal cle_activate : std_logic;`
70			`signal cle_latch_ctrl : std_logic;`
71			`signal cle_write_enable : std_logic;`
72			`signal cle_busy : std_logic;`
73			`signal cle_data_in : std_logic_vector(15 downto 0);`
74			`signal cle_data_out : std_logic_vector(15 downto 0);`
75
76			`signal ale_activate : std_logic;`
77			`signal ale_latch_ctrl : std_logic;`
78			`signal ale_write_enable : std_logic;`
79			`signal ale_busy : std_logic;`
80			`signal ale_data_in : std_logic_vector(15 downto 0);`
81			`signal ale_data_out : std_logic_vector(15 downto 0);`
82
83			`-- IO Unit.`
84			`-- This component implements NAND's read/write interfaces.`
85			`component io_unit`
86			`generic (io_type : io_t);`
87			`port(`
88			`activate,`
89			`clk : in std_logic;`
90			`data_in : in std_logic_vector(15 downto 0);`
91			`io_ctrl,`
92			`busy : out std_logic;`
93			`data_out : out std_logic_vector(15 downto 0)`
94			`);`
95			`end component;`
96
97			`-- IO Unit related signals`
98			`signal io_rd_activate : std_logic;`
99			`signal io_rd_io_ctrl : std_logic;`
100			`signal io_rd_busy : std_logic;`
101			`signal io_rd_data_in : std_logic_vector(15 downto 0);`
102			`signal io_rd_data_out : std_logic_vector(15 downto 0);`
103
104			`signal io_wr_activate : std_logic;`
105			`signal io_wr_io_ctrl : std_logic;`
106			`signal io_wr_busy : std_logic;`
107			`signal io_wr_data_in : std_logic_vector(15 downto 0);`
108			`signal io_wr_data_out : std_logic_vector(15 downto 0);`
109
110			`-- FSM`
111			`signal state : master_state_t := M_RESET;`
112			`signal n_state : master_state_t := M_RESET;`
113			`signal substate : master_substate_t := MS_BEGIN;`
114			`signal n_substate : master_substate_t := MS_BEGIN;`
115
116			`signal delay : integer := 0;`
117
118			`signal byte_count : integer := 0;`
119			`signal page_idx : integer := 0;`
120			`signal page_data : page_t;`
121			`signal page_param : param_page_t;`
122			`signal chip_id : nand_id_t;`
123			`signal current_address : nand_address_t;`
124			`signal data_bytes_per_page : integer;`
125			`signal oob_bytes_per_page : integer;`
126			`signal addr_cycles : integer;`
127			`signal state_switch : states_t :=`
128			`(`
129
130			`1 => M_NAND_RESET,`
131			`2 => M_NAND_READ_PARAM_PAGE,`
132			`3 => M_NAND_READ_ID,`
133			`4 => M_NAND_BLOCK_ERASE,`
134			`5 => M_NAND_READ_STATUS,`
135			`6 => M_NAND_READ,`
136			`7 => M_NAND_PAGE_PROGRAM,`
137			`8 => MI_GET_STATUS,`
138			`9 => MI_CHIP_ENABLE,`
139			`10 => MI_CHIP_DISABLE,`
140			`11 => MI_WRITE_PROTECT,`
141			`12 => MI_WRITE_ENABLE,`
142			`13 => MI_RESET_INDEX,`
143			`14 => MI_GET_ID_BYTE,`
144			`15 => MI_GET_PARAM_PAGE_BYTE,`
145			`16 => MI_GET_DATA_PAGE_BYTE,`
146			`17 => MI_SET_DATA_PAGE_BYTE,`
147			`18 => MI_GET_CURRENT_ADDRESS_BYTE,`
148			`19 => MI_SET_CURRENT_ADDRESS_BYTE,`
149			`others => M_IDLE`
150			`);`
151
152			`-- The following is a sort of a status register. Bit set to 1 means TRUE, bit set to 0 means FALSE:`
153			`-- 0 - is ONFI compliant`
154			`-- 1 - bus width (0 - x8 / 1 - x16)`
155			`-- 2 - is chip enabled`
156			`-- 3 - is chip write protected`
157			`-- 4 - array pointer out of bounds`
158			`-- 5 -`
159			`-- 6 -`
160			`-- 7 -`
161			`signal status : std_logic_vector(7 downto 0) := x"00";`
162			`begin`
163
164			`-- Asynchronous command latch interface.`
165			`ACL: latch_unit`
166			`generic map (latch_type => LATCH_CMD)`
167			`port map`
168			`(`
169			`activate => cle_activate,`
170			`latch_ctrl => cle_latch_ctrl,`
171			`write_enable => cle_write_enable,`
172			`busy => cle_busy,`
173			`clk => clk,`
174			`data_in => cle_data_in,`
175			`data_out => cle_data_out`
176			`);`
177
178			`-- Asynchronous address latch interface.`
179			`AAL: latch_unit`
180			`generic map (latch_type => LATCH_ADDR)`
181			`port map`
182			`(`
183			`activate => ale_activate,`
184			`latch_ctrl => ale_latch_ctrl,`
185			`write_enable => ale_write_enable,`
186			`busy => ale_busy,`
187			`clk => clk,`
188			`data_in => ale_data_in,`
189			`data_out => ale_data_out`
190			`);`
191
192			`-- Output to NAND`
193			`IO_WR: io_unit`
194			`generic map (io_type => IO_WRITE)`
195			`port map`
196			`(`
197			`clk => clk,`
198			`activate => io_wr_activate,`
199			`data_in => io_wr_data_in,`
200			`data_out => io_wr_data_out,`
201			`io_ctrl => io_wr_io_ctrl,`
202			`busy => io_wr_busy`
203			`);`
204
205			`-- Input from NAND`
206			`IO_RD: io_unit`
207			`generic map (io_type => IO_READ)`
208			`port map`
209			`(`
210			`clk => clk,`
211			`activate => io_rd_activate,`
212			`data_in => io_rd_data_in,`
213			`data_out => io_rd_data_out,`
214			`io_ctrl => io_rd_io_ctrl,`
215			`busy => io_rd_busy`
216			`);`
217
218			`-- Busy indicator`
219			`busy <= '0' when state = M_IDLE else`
220			`'1';`
221
222			`-- Bidirection NAND data interface.`
223			`--nand_data <= (cle_data_out or ale_data_out or io_wr_data_out) when (cle_busy or ale_busy or io_wr_busy) = '1' else x"ZZZZ";`
224			`nand_data <= cle_data_out when cle_busy = '1' else`
225			`ale_data_out when ale_busy = '1' else`
226			`io_wr_data_out when io_wr_busy = '1' else`
227			`"ZZZZZZZZZZZZZZZZ";`
228			`io_rd_data_in <= nand_data;`
229
230			`-- Command Latch Enable`
231			`nand_cle <= cle_latch_ctrl;`
232
233			`-- Address Latch Enable`
234			`nand_ale <= ale_latch_ctrl;`
235
236			`-- Write Enable`
237			`nand_nwe <= cle_write_enable and ale_write_enable and io_wr_io_ctrl;`
238
239			`-- Read Enable`
240			`nand_nre <= io_rd_io_ctrl;`
241
242			`-- Activation of command latch unit`
243	10	pradd	`cle_activate <= '1' when state = M_NAND_RESET or -- initiate submission of RESET command`
244	9	pradd	`(state = M_NAND_READ_PARAM_PAGE and substate = MS_BEGIN) or -- initiate submission of READ PARAMETER PAGE command`
245			`(state = M_NAND_BLOCK_ERASE and substate = MS_BEGIN) or -- initiate submission of BLOCK ERASE command`
246			`(state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND1) or -- initiate submission of BLOCK ERASE 2 command`
247			`(state = M_NAND_READ_STATUS and substate = MS_BEGIN) or -- initiate submission of READ STATUS command`
248			`(state = M_NAND_READ and substate = MS_BEGIN) or -- initiate read mode for READ command`
249			`(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND1) or -- initiate submission of READ command`
250			`(state = M_NAND_PAGE_PROGRAM and substate = MS_BEGIN) or -- initiate write mode for PAGE PROGRAM command`
251			`(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_COMMAND1) or -- initiate submission for PAGE PROGRAM command`
252			`(state = M_NAND_READ_ID and substate = MS_BEGIN) else -- initiate submission of READ ID command`
253			`'0';`
254
255			`-- Activation of address latch unit`
256			`ale_activate <= '1' when (state = M_NAND_READ_PARAM_PAGE and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ PARAMETER PAGE command`
257			`(state = M_NAND_BLOCK_ERASE and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for BLOCK ERASE command`
258			`(state = M_NAND_READ and substate = MS_SUBMIT_COMMAND) or -- initiate address submission for READ command`
259			`(state = M_NAND_PAGE_PROGRAM and substate = MS_SUBMIT_ADDRESS) or -- initiate address submission for PAGE PROGRAM command`
260			`(state = M_NAND_READ_ID and substate = MS_SUBMIT_COMMAND) else -- initiate address submission for READ ID command`
261			`'0';`
262
263			`-- Activation of read byte mechanism`
264			`io_rd_activate <= '1' when (state = M_NAND_READ_PARAM_PAGE and substate = MS_READ_DATA0) or -- initiate byte read for READ PARAMETER PAGE command`
265			`(state = M_NAND_READ_STATUS and substate = MS_READ_DATA0) or -- initiate byte read for READ STATUS command`
266			`(state = M_NAND_READ and substate = MS_READ_DATA0) or -- initiate byte read for READ command`
267			`(state = M_NAND_READ_ID and substate = MS_READ_DATA0) else -- initiate byte read for READ ID command`
268			`'0';`
269
270			`-- Activation of write byte mechanism`
271			`io_wr_activate <= '1' when (state = M_NAND_PAGE_PROGRAM and substate = MS_WRITE_DATA3) else -- initiate byte write for PAGE_PROGRAM command`
272			`'0';`
273
274			`MASTER: process(clk, nreset, activate, cmd_in, data_in, state_switch)`
275			`variable tmp_int : std_logic_vector(31 downto 0);`
276			`variable tmp : integer;`
277			`begin`
278			`if(nreset = '0')then`
279			`state <= M_RESET;`
280
281			`-- elsif(activate = '1')then`
282			`-- state <= state_switch(to_integer(unsigned(cmd_in)));`
283
284	12	pradd	`elsif(rising_edge(clk) and enable = '0')then`
285	9	pradd	`case state is`
286			`-- RESET state. Speaks for itself`
287			`when M_RESET =>`
288			`state <= M_IDLE;`
289			`substate <= MS_BEGIN;`
290			`delay <= 0;`
291			`byte_count <= 0;`
292			`page_idx <= 0;`
293			`current_address(0)<= x"00";`
294			`current_address(1)<= x"00";`
295			`current_address(2)<= x"00";`
296			`current_address(3)<= x"00";`
297			`current_address(4)<= x"00";`
298			`data_bytes_per_page <= 0;`
299			`oob_bytes_per_page <= 0;`
300			`addr_cycles <= 0;`
301			`status <= x"08"; -- We start write protected!`
302			`nand_nce <= '1';`
303			`nand_nwp <= '0';`
304
305			`-- This is in fact a command interpreter`
306			`when M_IDLE =>`
307			`if(activate = '1')then`
308			`state <= state_switch(to_integer(unsigned(cmd_in)));`
309			`end if;`
310
311			`-- Reset the NAND chip`
312			`when M_NAND_RESET =>`
313			`cle_data_in <= x"00ff";`
314			`state <= M_WAIT;`
315			`n_state <= M_IDLE;`
316	12	pradd	`delay <= t_wb + 8;`
317	9	pradd
318	10	pradd	`-- Read the status register of the controller`
319	9	pradd	`when MI_GET_STATUS =>`
320			`data_out <= status;`
321			`state <= M_IDLE;`
322
323	10	pradd	`-- Set CE# to '0' (enable NAND chip)`
324	9	pradd	`when MI_CHIP_ENABLE =>`
325			`nand_nce <= '0';`
326			`state <= M_IDLE;`
327			`status(2) <= '1';`
328
329	10	pradd	`-- Set CE# to '1' (disable NAND chip)`
330	9	pradd	`when MI_CHIP_DISABLE =>`
331			`nand_nce <= '1';`
332			`state <= M_IDLE;`
333			`status(2) <= '0';`
334
335	10	pradd	`-- Set WP# to '0' (enable write protection)`
336	9	pradd	`when MI_WRITE_PROTECT =>`
337			`nand_nwp <= '0';`
338			`status(3) <= '1';`
339			`state <= M_IDLE;`
340
341	10	pradd	`-- Set WP# to '1' (disable write protection)`
342			`-- By default, this controller has WP# set to 0 on reset`
343	9	pradd	`when MI_WRITE_ENABLE =>`
344			`nand_nwp <= '1';`
345			`status(3) <= '0';`
346			`state <= M_IDLE;`
347
348	10	pradd	`-- Reset the index register.`
349			`-- Index register holds offsets into JEDEC ID, Parameter Page buffer or Data Page buffer depending on`
350			`-- the operation being performed`
351	9	pradd	`when MI_RESET_INDEX =>`
352			`page_idx <= 0;`
353			`state <= M_IDLE;`
354
355	10	pradd	`-- Read 1 byte from JEDEC ID and increment the index register.`
356			`-- If the value points outside the 5 byte JEDEC ID array,`
357			`-- the register is reset to 0 and bit 4 of the status register`
358			`-- is set to '1'`
359	9	pradd	`when MI_GET_ID_BYTE =>`
360			`if(page_idx < 5)then`
361			`data_out <= chip_id(page_idx);`
362			`page_idx <= page_idx + 1;`
363			`status(4) <= '0';`
364			`else`
365			`data_out <= x"00";`
366			`page_idx <= 0;`
367			`status(4) <= '1';`
368			`end if;`
369			`state <= M_IDLE;`
370
371	10	pradd	`-- Read 1 byte from 256 bytes buffer that holds the Parameter Page.`
372			`-- If the value goes beyond 255, then the register is reset and`
373			`-- bit 4 of the status register is set to '1'`
374	9	pradd	`when MI_GET_PARAM_PAGE_BYTE =>`
375			`if(page_idx < 256)then`
376			`data_out <= page_param(page_idx);`
377			`page_idx <= page_idx + 1;`
378			`status(4) <= '0';`
379			`else`
380			`data_out <= x"00";`
381			`page_idx <= 0;`
382			`status(4) <= '1';`
383			`end if;`
384			`state <= M_IDLE;`
385
386	10	pradd	`-- Read 1 byte from the buffer that holds the content of last read`
387			`-- page. The limit is variable and depends on the values in`
388			`-- the Parameter Page. In case the index register points beyond`
389			`-- valid page content, its value is reset and bit 4 of the status`
390			`-- register is set to '1'`
391	9	pradd	`when MI_GET_DATA_PAGE_BYTE =>`
392			`if(page_idx < data_bytes_per_page + oob_bytes_per_page)then`
393			`data_out <= page_data(page_idx);`
394			`page_idx <= page_idx + 1;`
395			`status(4) <= '0';`
396			`else`
397			`data_out <= x"00";`
398			`page_idx <= 0;`
399			`status(4) <= '1';`
400			`end if;`
401			`state <= M_IDLE;`
402
403	10	pradd	`-- Write 1 byte into the Data Page buffer at offset specified by`
404			`-- the index register. If the value of the index register points`
405			`-- beyond valid page content, its value is reset and bit 4 of`
406			`-- the status register is set to '1'`
407	9	pradd	`when MI_SET_DATA_PAGE_BYTE =>`
408			`if(page_idx < data_bytes_per_page + oob_bytes_per_page)then`
409			`page_data(page_idx) <= data_in;`
410			`page_idx <= page_idx + 1;`
411			`status(4) <= '0';`
412			`else`
413			`page_idx <= 0;`
414			`status(4) <= '1';`
415			`end if;`
416			`state <= M_IDLE;`
417
418	10	pradd	`-- Gets the address byte specified by the index register. Bit 4`
419			`-- of the status register is set to '1' if the value of the index`
420			`-- register points beyond valid address data and the value of`
421			`-- the index register is reset`
422	9	pradd	`when MI_GET_CURRENT_ADDRESS_BYTE =>`
423			`if(page_idx < addr_cycles)then`
424			`data_out <= current_address(page_idx);`
425			`page_idx <= page_idx + 1;`
426			`status(4) <= '0';`
427			`else`
428			`page_idx <= 0;`
429			`status(4) <= '1';`
430			`end if;`
431			`state <= M_IDLE;`
432
433	10	pradd	`-- Sets the value of the address byte specified by the index register.Bit 4`
434			`-- of the status register is set to '1' if the value of the index`
435			`-- register points beyond valid address data and the value of`
436			`-- the index register is reset`
437	9	pradd	`when MI_SET_CURRENT_ADDRESS_BYTE =>`
438			`if(page_idx < addr_cycles)then`
439			`current_address(page_idx) <= data_in;`
440			`page_idx <= page_idx + 1;`
441			`status(4) <= '0';`
442			`else`
443			`page_idx <= 0;`
444			`status(4) <= '1';`
445			`end if;`
446			`state <= M_IDLE;`
447
448			`-- Program one page.`
449			`when M_NAND_PAGE_PROGRAM =>`
450			`if(substate = MS_BEGIN)then`
451			`cle_data_in <= x"0080";`
452			`substate <= MS_SUBMIT_COMMAND;`
453			`state <= M_WAIT;`
454			`n_state <= M_NAND_PAGE_PROGRAM;`
455			`byte_count <= 0;`
456
457			`elsif(substate = MS_SUBMIT_COMMAND)then`
458			`byte_count <= byte_count + 1;`
459			`ale_data_in <= x"00"&current_address(byte_count);`
460			`substate <= MS_SUBMIT_ADDRESS;`
461
462			`elsif(substate = MS_SUBMIT_ADDRESS)then`
463			`if(byte_count < addr_cycles)then`
464			`substate <= MS_SUBMIT_COMMAND;`
465			`else`
466			`substate <= MS_WRITE_DATA0;`
467			`end if;`
468			`state <= M_WAIT;`
469			`n_state <= M_NAND_PAGE_PROGRAM;`
470
471			`elsif(substate = MS_WRITE_DATA0)then`
472			`delay <= t_adl;`
473			`state <= M_DELAY;`
474			`n_state <= M_NAND_PAGE_PROGRAM;`
475			`substate <= MS_WRITE_DATA1;`
476			`page_idx <= 0;`
477			`byte_count <= 0;`
478
479			`elsif(substate = MS_WRITE_DATA1)then`
480			`byte_count <= byte_count + 1;`
481			`page_idx <= page_idx + 1;`
482			`io_wr_data_in <= x"00"&page_data(page_idx);`
483			`if(status(1) = '0')then`
484			`substate <= MS_WRITE_DATA3;`
485			`else`
486			`substate <= MS_WRITE_DATA2;`
487			`end if;`
488
489			`elsif(substate = MS_WRITE_DATA2)then`
490			`page_idx <= page_idx + 1;`
491			`io_wr_data_in(15 downto 8) <= page_data(page_idx);`
492			`substate <= MS_WRITE_DATA3;`
493
494			`elsif(substate = MS_WRITE_DATA3)then`
495			`if(byte_count < data_bytes_per_page + oob_bytes_per_page)then`
496			`substate <= MS_WRITE_DATA1;`
497			`else`
498			`substate <= MS_SUBMIT_COMMAND1;`
499			`end if;`
500			`n_state <= M_NAND_PAGE_PROGRAM;`

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[/] [nand_controller/] [trunk/] [VHDL/] [nand_master.vhd] - Blame information for rev 13