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[/] [nand_controller/] [trunk/] [VHDL/] [testbench.vhd] - Blame information for rev 13

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1 11 pradd 
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-- Title                                                        : ONFI compliant NAND interface
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-- File                                                 : testbench.vhd
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-- Author                                               : Alexey Lyashko <pradd@opencores.org>
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-- License                                              : LGPL
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-------------------------------------------------------------------------------------------------
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-- Description:
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-- This is the testbench file for the NAND_MASTER module
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.onfi.all;
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entity tb is
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        --port
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        --(
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        --);
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end tb;
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architecture test of tb is
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        component nand_master
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                port
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                (
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                        -- System clock
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                        clk                                     : in    std_logic;
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                        -- NAND chip control hardware interface. These signals should be bound to physical pins.
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                        nand_cle                                : out   std_logic := '0';
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                        nand_ale                                : out   std_logic := '0';
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                        nand_nwe                                : out   std_logic := '1';
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                        nand_nwp                                : out   std_logic := '0';
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                        nand_nce                                : out   std_logic := '1';
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                        nand_nre                                : out std_logic := '1';
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                        nand_rnb                                : in    std_logic;
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                        -- NAND chip data hardware interface. These signals should be boiund to physical pins.
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                        nand_data                       : inout std_logic_vector(15 downto 0);
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                        -- Component interface
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                        nreset                          : in    std_logic := '1';
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                        data_out                                : out   std_logic_vector(7 downto 0);
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                        data_in                         : in    std_logic_vector(7 downto 0);
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                        busy                                    : out   std_logic := '0';
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                        activate                                : in    std_logic := '0';
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                        cmd_in                          : in    std_logic_vector(7 downto 0)
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                );
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        end component;
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        -- Internal interface
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        signal nand_cle : std_logic;
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        signal nand_ale : std_logic;
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        signal nand_nwe : std_logic;
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        signal nand_nwp : std_logic;
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        signal nand_nce :       std_logic;
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        signal nand_nre : std_logic;
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        signal nand_rnb : std_logic := '1';
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        signal nand_data: std_logic_vector(15 downto 0);
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        signal nreset   : std_logic := '1';
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        signal data_out : std_logic_vector(7 downto 0);
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        signal data_in  : std_logic_vector(7 downto 0);
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        signal busy     : std_logic;
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        signal activate : std_logic;
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        signal cmd_in   : std_logic_vector(7 downto 0);
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        signal clk      : std_logic := '1';
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begin
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        NM:nand_master
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        port map
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        (
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                clk => clk,
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                nand_cle => nand_cle,
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                nand_ale => nand_ale,
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                nand_nwe => nand_nwe,
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                nand_nwp => nand_nwp,
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                nand_nce => nand_nce,
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                nand_nre => nand_nre,
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                nand_rnb => nand_rnb,
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                nand_data=> nand_data,
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                nreset   => nreset,
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                data_out => data_out,
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                data_in  => data_in,
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                busy     => busy,
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                activate => activate,
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                cmd_in   => cmd_in
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        );
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        CLOCK:process
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        begin
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                clk <= '1';
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                wait for 1.25ns;
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                clk <= '0';
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                wait for 1.25ns;
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        end process;
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        TP: process
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        begin
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                activate <= '0';
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                nreset <= '1';
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                nand_data <= "ZZZZZZZZZZZZZZZZ";
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                -- Enable the chip
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                wait for 5ns;
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                cmd_in <= x"09";
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                -- Read JEDEC ID
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                data_in <= x"00";
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                cmd_in <= x"03";
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                wait for 5ns;
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                -- Provide ID
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                wait for 155ns;
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                nand_data <= x"002c";
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                wait for 32.5ns;
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                nand_data <= x"00e5";
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                wait for 32.5ns;
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                nand_data <= x"00ff";
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                wait for 32.5ns;
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                nand_data <= x"0003";
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                wait for 32.5ns;
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                nand_data <= x"0086";
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                wait for 32.5ns;
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                nand_data <= "ZZZZZZZZZZZZZZZZ";
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                wait for 5ns;
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                -- Read the bytes of the ID
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                cmd_in <= x"0e";
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                -- 1
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                wait for 2.5ns;
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                -- 2
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                wait for 2.5ns;
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                -- 3
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                wait for 2.5ns;
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                -- 4
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                wait for 2.5ns;
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                -- 5
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                cmd_in <= x"08";
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                wait for 2.5ns;
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                activate <= '1';
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                wait for 2.5ns;
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                activate <= '0';
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                wait;
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        end process;
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end test;

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