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fcorthay |
--##############################################################################
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--
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-- nanoblaze_tb
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-- Stimuli generator for the NanoBlaze processor testbench
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--
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-- Provides clock and reset to the DUT.
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-- Inverts I/O data out to I/O data in for test purpose.
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--
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-- Waits for the end of the test signalled by the processor by writing
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-- at I/O address 0. The data signals if the tests were successful or not.
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--
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--------------------------------------------------------------------------------
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--
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-- Versions / Authors
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-- 1.0 Francois Corthay first implementation
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--
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-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
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--
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-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
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-- <http://www.hevs.ch/en/rad-instituts/institut-systemes-industriels/>.
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--
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--------------------------------------------------------------------------------
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--
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-- Hierarchy
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-- Used by "nanoblaze_tb".
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--
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--##############################################################################
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY nanoBlaze_tester IS
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GENERIC(
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addressBitNb : positive := 8;
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dataBitNb : positive := 8
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);
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PORT(
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reset : OUT std_ulogic
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clock : OUT std_uLogic;
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en : OUT std_uLogic;
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dataAddress : IN unsigned(addressBitNb-1 DOWNTO 0);
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dataOut : IN std_ulogic_vector(dataBitNb-1 DOWNTO 0);
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dataIn : OUT std_ulogic_vector(dataBitNb-1 DOWNTO 0);
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readStrobe : IN std_uLogic;
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writeStrobe : IN std_uLogic;
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int : OUT std_uLogic;
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intAck : IN std_uLogic;
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);
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END nanoBlaze_tester ;
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--==============================================================================
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ARCHITECTURE test OF nanoBlaze_tester IS
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constant clockFrequency: real := 100.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal dataReg: std_ulogic_vector(dataOut'range);
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- enable
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en <= '1';
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------------------------------------------------------------------------------
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-- data
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storeData: process(clock_int)
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begin
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if rising_edge(clock_int) then
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if writeStrobe = '1' then
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dataReg <= dataOut;
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end if;
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end if;
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end process storeData;
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dataIn <= not dataReg;
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------------------------------------------------------------------------------
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-- error checking
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checkBus: process(clock_int)
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begin
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if rising_edge(clock_int) then
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if writeStrobe = '1' then
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if (dataAddress = 0) and (unsigned(dataOut) = 0) then
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assert false
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report "Testbench reports error (output value 0 at address 0)"
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severity failure;
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end if;
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if (dataAddress = 0) and (unsigned(dataOut) = 1) then
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assert false
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report
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cr & cr &
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"--------------------------------------------------------------------------------" & cr &
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"Testbench reports successful end of simulation (output value 1 at address 0)" & cr &
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"--------------------------------------------------------------------------------" & cr &
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cr
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severity failure;
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end if;
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end if;
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end if;
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end process checkBus;
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END ARCHITECTURE test;
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