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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:       Universidad Pontificia Bolivariana
// Engineer:      Fabio Andres Guzman Figueroa
// 
// Create Date:    19:48:58 05/14/2012 
// Design Name: 
// Module Name:    control_unit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module control_unit(
    input clk,
    input rst,
    input [15:0] instruction,
    input z,
    input c,
    output reg [7:0] port_addr,
    output reg write_e,
    output reg read_e,
    output reg insel,
    output reg we,
    output reg [2:0] raa,
    output reg [2:0] rab,
    output reg [2:0] wa,
    output reg [2:0] opalu,
    output reg [2:0] sh,
    output reg selpc,
    output reg ldpc,
    output reg ldflag,
    output reg [10:0] naddress,
    output reg selk,
    output reg [7:0] KTE,
         input [10:0] stack_addr,
         output reg wr_en, rd_en,
         output reg [7:0] imm,
         output reg selimm
    );
 
 
parameter fetch=        5'd0;
parameter decode=       5'd1;
 
parameter ldi=          5'd2;
parameter ldm=          5'd3;
parameter stm=          5'd4;
parameter cmp=          5'd5;
parameter add=          5'd6;
parameter sub=          5'd7;
parameter andi= 5'd8;
parameter oor=          5'd9;
parameter xori= 5'd10;
parameter jmp=          5'd11;
parameter jpz=          5'd12;
parameter jnz=          5'd13;
parameter jpc=          5'd14;
parameter jnc=          5'd15;
parameter csr=          5'd16;
parameter ret=          5'd17;
 
parameter adi=          5'd18;
parameter csz=          5'd19;
parameter cnz=          5'd20;
parameter csc=          5'd21;
parameter cnc=          5'd22;
parameter sl0=          5'd23;
parameter sl1=          5'd24;
parameter sr0=          5'd25;
parameter sr1=          5'd26;
parameter rrl=          5'd27;
parameter rrr=          5'd28;
parameter noti= 5'd29;
 
parameter nop=          5'd30;
 
wire [4:0] opcode;
reg [4:0] state;
 
assign opcode=instruction[15:11];
 
always@(posedge clk or posedge rst)
        if (rst)
                state<=decode;
        else
                case (state)
                        fetch: state<=decode;
 
                        decode: case (opcode)
                                                        2:      state<=ldi;
                                                        3:              state<=ldm;
                                                        4:              state<=stm;
                                                        5:              state<=cmp;
                                                        6:              state<=add;
                                                        7:              state<=sub;
                                                        8:              state<=andi;
                                                        9:              state<=oor;
                                                        10:     state<=xori;
                                                        11:     state<=jmp;
                                                        12:     state<=jpz;
                                                        13:     state<=jnz;
                                                        14:     state<=jpc;
                                                        15:     state<=jnc;
                                                        16:     state<=csr;
                                                        17:     state<=ret;
                                                        18:     state<=adi;
                                                        19:     state<=csz;
                                                        20:     state<=cnz;
                                                        21:     state<=csc;
                                                        22:     state<=cnc;
                                                        23:     state<=sl0;
                                                        24:     state<=sl1;
                                                        25:     state<=sr0;
                                                        26:     state<=sr1;
                                                        27:     state<=rrl;
                                                        28:     state<=rrr;
                                                        29:     state<=noti;
                                                        default:        state<=nop;
                                                endcase
 
                        ldi:    state<=fetch;
 
                        ldm:    state<=fetch;
 
                        stm:    state<=fetch;
 
                        cmp:    state<=fetch;
 
                        add:    state<=fetch;
 
                        sub:    state<=fetch;
 
                        andi:   state<=fetch;
 
                        oor:    state<=fetch;
 
                        xori:   state<=fetch;
 
                        jmp:    state<=fetch;
 
                        jpz:    state<=fetch;
 
                        jnz:    state<=fetch;
 
                        jpc:    state<=fetch;
 
                        jnc:    state<=fetch;
 
                        csr:    state<=fetch;
 
                        ret:    state<=fetch;
 
                        adi:    state<=fetch;
 
                        csz:    state<=fetch;
 
                        cnz:    state<=fetch;
 
                        csc:    state<=fetch;
 
                        cnc:    state<=fetch;
 
                        sl0:    state<=fetch;
 
                        sl1:    state<=fetch;
 
                        sr0:    state<=fetch;
 
                        sr1:    state<=fetch;
 
                        rrl:    state<=fetch;
 
                        rrr:    state<=fetch;
 
                        noti:   state<=fetch;
 
                        nop:    state<=fetch;
                        endcase
 
 
 
always@(*)
        begin
                port_addr<=0;
                write_e<=0;
                read_e<=0;
                insel<=0;
                we<=0;
                raa<=0;
                rab<=0;
                wa<=0;
                opalu<=4;
                sh<=4;
                selpc<=0;
                ldpc<=1;
                ldflag<=0;
                naddress<=0;
                selk<=0;
                KTE<=0;
                wr_en<=0;
                rd_en<=0;
                imm<=0;
                selimm<=0;
 
                case (state)
                        fetch: ldpc<=0;
 
                        decode:  begin
                                                        ldpc<=0;
                                                        if (opcode==stm)
                                                                begin
                                                                        raa<=instruction[10:8];
                                                                        port_addr<=instruction[7:0];
                                                                end
                                                        else if (opcode==ldm)
                                                                begin
                                                                        wa<=instruction[10:8];
                                                                        port_addr<=instruction[7:0];
                                                                end
                                                        else if (opcode==ret)
                                                                begin
                                                                        rd_en<=1;
                                                                end
                                                end
 
                        ldi:    begin
                                                selk<=1;
                                                KTE<=instruction[7:0];
                                                we<=1;
                                                wa<=instruction[10:8];
                                        end
 
                        ldm:    begin
                                                wa<=instruction[10:8];
                                                we<=1;
                                                read_e<=1;
                                                port_addr<=instruction[7:0];
                                        end
 
                        stm:    begin
                                                raa<=instruction[10:8];
                                                write_e<=1;
                                                port_addr<=instruction[7:0];
                                        end
 
                        cmp:    begin
                                                ldflag<=1;
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                opalu<=6;
                                        end
 
                        add:    begin
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=5;
                                                we<=1;
                                        end
 
                        sub:    begin
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=6;
                                                we<=1;
                                        end
 
                        andi:   begin
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=1;
                                                we<=1;
                                        end
 
                        oor:    begin
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=3;
                                                we<=1;
                                        end
 
                        xori:   begin
                                                raa<=instruction[10:8];
                                                rab<=instruction[7:5];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=2;
                                                we<=1;
                                        end
 
                        jmp:    begin
                                                naddress<=instruction[10:0];
                                                selpc<=1;
                                                ldpc<=1;
                                        end
 
                        jpz:            if (z)
                                                begin
                                                        naddress<=instruction[10:0];
                                                        selpc<=1;
                                                        ldpc<=1;
                                                end
 
                        jnz:            if (!z)
                                                        begin
                                                                naddress<=instruction[10:0];
                                                                selpc<=1;
                                                                ldpc<=1;
                                                        end
 
 
                        jpc:    if (c)
                                                        begin
                                                                naddress<=instruction[10:0];
                                                                selpc<=1;
                                                                ldpc<=1;
                                                        end
 
 
                        jnc:    if (!c)
                                                        begin
                                                                naddress<=instruction[10:0];
                                                                selpc<=1;
                                                                ldpc<=1;
                                                        end
 
                        csr:    begin
                                                naddress<=instruction[10:0];
                                                selpc<=1;
                                                ldpc<=1;
                                                wr_en<=1;
                                        end
 
                        ret:    begin
                                                naddress<=stack_addr;
                                                selpc<=1;
                                                ldpc<=1;
                                        end
 
                        adi:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                imm<=instruction[7:0];
                                                selimm<=1;
                                                insel<=1;
                                                opalu<=5;
                                                we<=1;
                                        end
 
                        csz:    if (z)
                                                begin
                                                        naddress<=instruction[10:0];
                                                        selpc<=1;
                                                        ldpc<=1;
                                                        wr_en<=1;
                                                end
 
                        cnz:    if (!z)
                                                begin
                                                        naddress<=instruction[10:0];
                                                        selpc<=1;
                                                        ldpc<=1;
                                                        wr_en<=1;
                                                end
 
                        csc:    if (c)
                                                begin
                                                        naddress<=instruction[10:0];
                                                        selpc<=1;
                                                        ldpc<=1;
                                                        wr_en<=1;
                                                end
 
                        cnc:    if (!c)
                                                begin
                                                        naddress<=instruction[10:0];
                                                        selpc<=1;
                                                        ldpc<=1;
                                                        wr_en<=1;
                                                end
 
                        sl0:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=0;
                                                we<=1;
                                        end
 
                        sl1:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=5;
                                                we<=1;
                                        end
 
                        sr0:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=2;
                                                we<=1;
                                        end
 
                        sr1:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=6;
                                                we<=1;
                                        end
 
                        rrl:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=1;
                                                we<=1;
                                        end
 
                        rrr:    begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                sh<=3;
                                                we<=1;
                                        end
 
                        noti:   begin
                                                raa<=instruction[10:8];
                                                wa<=instruction[10:8];
                                                insel<=1;
                                                opalu<=0;
                                                we<=1;
                                        end
 
                        nop:    opalu<=4;
 
                endcase
        end
 
 
endmodule

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[/] [natalius_8bit_risc/] [trunk/] [processor_core/] [control_unit.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	fabioandre	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: Universidad Pontificia Bolivariana`
4			`// Engineer: Fabio Andres Guzman Figueroa`
5			`//`
6			`// Create Date: 19:48:58 05/14/2012`
7			`// Design Name:`
8			`// Module Name: control_unit`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module control_unit(`
22			`input clk,`
23			`input rst,`
24			`input [15:0] instruction,`
25			`input z,`
26			`input c,`
27			`output reg [7:0] port_addr,`
28			`output reg write_e,`
29			`output reg read_e,`
30			`output reg insel,`
31			`output reg we,`
32			`output reg [2:0] raa,`
33			`output reg [2:0] rab,`
34			`output reg [2:0] wa,`
35			`output reg [2:0] opalu,`
36			`output reg [2:0] sh,`
37			`output reg selpc,`
38			`output reg ldpc,`
39			`output reg ldflag,`
40			`output reg [10:0] naddress,`
41			`output reg selk,`
42			`output reg [7:0] KTE,`
43			`input [10:0] stack_addr,`
44			`output reg wr_en, rd_en,`
45			`output reg [7:0] imm,`
46			`output reg selimm`
47			`);`
48
49
50			`parameter fetch= 5'd0;`
51			`parameter decode= 5'd1;`
52
53			`parameter ldi= 5'd2;`
54			`parameter ldm= 5'd3;`
55			`parameter stm= 5'd4;`
56			`parameter cmp= 5'd5;`
57			`parameter add= 5'd6;`
58			`parameter sub= 5'd7;`
59			`parameter andi= 5'd8;`
60			`parameter oor= 5'd9;`
61			`parameter xori= 5'd10;`
62			`parameter jmp= 5'd11;`
63			`parameter jpz= 5'd12;`
64			`parameter jnz= 5'd13;`
65			`parameter jpc= 5'd14;`
66			`parameter jnc= 5'd15;`
67			`parameter csr= 5'd16;`
68			`parameter ret= 5'd17;`
69
70			`parameter adi= 5'd18;`
71			`parameter csz= 5'd19;`
72			`parameter cnz= 5'd20;`
73			`parameter csc= 5'd21;`
74			`parameter cnc= 5'd22;`
75			`parameter sl0= 5'd23;`
76			`parameter sl1= 5'd24;`
77			`parameter sr0= 5'd25;`
78			`parameter sr1= 5'd26;`
79			`parameter rrl= 5'd27;`
80			`parameter rrr= 5'd28;`
81			`parameter noti= 5'd29;`
82
83			`parameter nop= 5'd30;`
84
85			`wire [4:0] opcode;`
86			`reg [4:0] state;`
87
88			`assign opcode=instruction[15:11];`
89
90			`always@(posedge clk or posedge rst)`
91			`if (rst)`
92			`state<=decode;`
93			`else`
94			`case (state)`
95			`fetch: state<=decode;`
96
97			`decode: case (opcode)`
98			`2: state<=ldi;`
99			`3: state<=ldm;`
100			`4: state<=stm;`
101			`5: state<=cmp;`
102			`6: state<=add;`
103			`7: state<=sub;`
104			`8: state<=andi;`
105			`9: state<=oor;`
106			`10: state<=xori;`
107			`11: state<=jmp;`
108			`12: state<=jpz;`
109			`13: state<=jnz;`
110			`14: state<=jpc;`
111			`15: state<=jnc;`
112			`16: state<=csr;`
113			`17: state<=ret;`
114			`18: state<=adi;`
115			`19: state<=csz;`
116			`20: state<=cnz;`
117			`21: state<=csc;`
118			`22: state<=cnc;`
119			`23: state<=sl0;`
120			`24: state<=sl1;`
121			`25: state<=sr0;`
122			`26: state<=sr1;`
123			`27: state<=rrl;`
124			`28: state<=rrr;`
125			`29: state<=noti;`
126			`default: state<=nop;`
127			`endcase`
128
129			`ldi: state<=fetch;`
130
131			`ldm: state<=fetch;`
132
133			`stm: state<=fetch;`
134
135			`cmp: state<=fetch;`
136
137			`add: state<=fetch;`
138
139			`sub: state<=fetch;`
140
141			`andi: state<=fetch;`
142
143			`oor: state<=fetch;`
144
145			`xori: state<=fetch;`
146
147			`jmp: state<=fetch;`
148
149			`jpz: state<=fetch;`
150
151			`jnz: state<=fetch;`
152
153			`jpc: state<=fetch;`
154
155			`jnc: state<=fetch;`
156
157			`csr: state<=fetch;`
158
159			`ret: state<=fetch;`
160
161			`adi: state<=fetch;`
162
163			`csz: state<=fetch;`
164
165			`cnz: state<=fetch;`
166
167			`csc: state<=fetch;`
168
169			`cnc: state<=fetch;`
170
171			`sl0: state<=fetch;`
172
173			`sl1: state<=fetch;`
174
175			`sr0: state<=fetch;`
176
177			`sr1: state<=fetch;`
178
179			`rrl: state<=fetch;`
180
181			`rrr: state<=fetch;`
182
183			`noti: state<=fetch;`
184
185			`nop: state<=fetch;`
186			`endcase`
187
188
189
190			`always@(*)`
191			`begin`
192			`port_addr<=0;`
193			`write_e<=0;`
194			`read_e<=0;`
195			`insel<=0;`
196			`we<=0;`
197			`raa<=0;`
198			`rab<=0;`
199			`wa<=0;`
200			`opalu<=4;`
201			`sh<=4;`
202			`selpc<=0;`
203			`ldpc<=1;`
204			`ldflag<=0;`
205			`naddress<=0;`
206			`selk<=0;`
207			`KTE<=0;`
208			`wr_en<=0;`
209			`rd_en<=0;`
210			`imm<=0;`
211			`selimm<=0;`
212
213			`case (state)`
214			`fetch: ldpc<=0;`
215
216			`decode: begin`
217			`ldpc<=0;`
218			`if (opcode==stm)`
219			`begin`
220			`raa<=instruction[10:8];`
221			`port_addr<=instruction[7:0];`
222			`end`
223			`else if (opcode==ldm)`
224			`begin`
225			`wa<=instruction[10:8];`
226			`port_addr<=instruction[7:0];`
227			`end`
228			`else if (opcode==ret)`
229			`begin`
230			`rd_en<=1;`
231			`end`
232			`end`
233
234			`ldi: begin`
235			`selk<=1;`
236			`KTE<=instruction[7:0];`
237			`we<=1;`
238			`wa<=instruction[10:8];`
239			`end`
240
241			`ldm: begin`
242			`wa<=instruction[10:8];`
243			`we<=1;`
244			`read_e<=1;`
245			`port_addr<=instruction[7:0];`
246			`end`
247
248			`stm: begin`
249			`raa<=instruction[10:8];`
250			`write_e<=1;`
251			`port_addr<=instruction[7:0];`
252			`end`
253
254			`cmp: begin`
255			`ldflag<=1;`
256			`raa<=instruction[10:8];`
257			`rab<=instruction[7:5];`
258			`opalu<=6;`
259			`end`
260
261			`add: begin`
262			`raa<=instruction[10:8];`
263			`rab<=instruction[7:5];`
264			`wa<=instruction[10:8];`
265			`insel<=1;`
266			`opalu<=5;`
267			`we<=1;`
268			`end`
269
270			`sub: begin`
271			`raa<=instruction[10:8];`
272			`rab<=instruction[7:5];`
273			`wa<=instruction[10:8];`
274			`insel<=1;`
275			`opalu<=6;`
276			`we<=1;`
277			`end`
278
279			`andi: begin`
280			`raa<=instruction[10:8];`
281			`rab<=instruction[7:5];`
282			`wa<=instruction[10:8];`
283			`insel<=1;`
284			`opalu<=1;`
285			`we<=1;`
286			`end`
287
288			`oor: begin`
289			`raa<=instruction[10:8];`
290			`rab<=instruction[7:5];`
291			`wa<=instruction[10:8];`
292			`insel<=1;`
293			`opalu<=3;`
294			`we<=1;`
295			`end`
296
297			`xori: begin`
298			`raa<=instruction[10:8];`
299			`rab<=instruction[7:5];`
300			`wa<=instruction[10:8];`
301			`insel<=1;`
302			`opalu<=2;`
303			`we<=1;`
304			`end`
305
306			`jmp: begin`
307			`naddress<=instruction[10:0];`
308			`selpc<=1;`
309			`ldpc<=1;`
310			`end`
311
312			`jpz: if (z)`
313			`begin`
314			`naddress<=instruction[10:0];`
315			`selpc<=1;`
316			`ldpc<=1;`
317			`end`
318
319			`jnz: if (!z)`
320			`begin`
321			`naddress<=instruction[10:0];`
322			`selpc<=1;`
323			`ldpc<=1;`
324			`end`
325
326
327			`jpc: if (c)`
328			`begin`
329			`naddress<=instruction[10:0];`
330			`selpc<=1;`
331			`ldpc<=1;`
332			`end`
333
334
335			`jnc: if (!c)`
336			`begin`
337			`naddress<=instruction[10:0];`
338			`selpc<=1;`
339			`ldpc<=1;`
340			`end`
341
342			`csr: begin`
343			`naddress<=instruction[10:0];`
344			`selpc<=1;`
345			`ldpc<=1;`
346			`wr_en<=1;`
347			`end`
348
349			`ret: begin`
350			`naddress<=stack_addr;`
351			`selpc<=1;`
352			`ldpc<=1;`
353			`end`
354
355			`adi: begin`
356			`raa<=instruction[10:8];`
357			`wa<=instruction[10:8];`
358			`imm<=instruction[7:0];`
359			`selimm<=1;`
360			`insel<=1;`
361			`opalu<=5;`
362			`we<=1;`
363			`end`
364
365			`csz: if (z)`
366			`begin`
367			`naddress<=instruction[10:0];`
368			`selpc<=1;`
369			`ldpc<=1;`
370			`wr_en<=1;`
371			`end`
372
373			`cnz: if (!z)`
374			`begin`
375			`naddress<=instruction[10:0];`
376			`selpc<=1;`
377			`ldpc<=1;`
378			`wr_en<=1;`
379			`end`
380
381			`csc: if (c)`
382			`begin`
383			`naddress<=instruction[10:0];`
384			`selpc<=1;`
385			`ldpc<=1;`
386			`wr_en<=1;`
387			`end`
388
389			`cnc: if (!c)`
390			`begin`
391			`naddress<=instruction[10:0];`
392			`selpc<=1;`
393			`ldpc<=1;`
394			`wr_en<=1;`
395			`end`
396
397			`sl0: begin`
398			`raa<=instruction[10:8];`
399			`wa<=instruction[10:8];`
400			`insel<=1;`
401			`sh<=0;`
402			`we<=1;`
403			`end`
404
405			`sl1: begin`
406			`raa<=instruction[10:8];`
407			`wa<=instruction[10:8];`
408			`insel<=1;`
409			`sh<=5;`
410			`we<=1;`
411			`end`
412
413			`sr0: begin`
414			`raa<=instruction[10:8];`
415			`wa<=instruction[10:8];`
416			`insel<=1;`
417			`sh<=2;`
418			`we<=1;`
419			`end`
420
421			`sr1: begin`
422			`raa<=instruction[10:8];`
423			`wa<=instruction[10:8];`
424			`insel<=1;`
425			`sh<=6;`
426			`we<=1;`
427			`end`
428
429			`rrl: begin`
430			`raa<=instruction[10:8];`
431			`wa<=instruction[10:8];`
432			`insel<=1;`
433			`sh<=1;`
434			`we<=1;`
435			`end`
436
437			`rrr: begin`
438			`raa<=instruction[10:8];`
439			`wa<=instruction[10:8];`
440			`insel<=1;`
441			`sh<=3;`
442			`we<=1;`
443			`end`
444
445			`noti: begin`
446			`raa<=instruction[10:8];`
447			`wa<=instruction[10:8];`
448			`insel<=1;`
449			`opalu<=0;`
450			`we<=1;`
451			`end`
452
453			`nop: opalu<=4;`
454
455			`endcase`
456			`end`
457
458
459			`endmodule`