OpenCores
URL https://opencores.org/ocsvn/natalius_8bit_risc/natalius_8bit_risc/trunk

Subversion Repositories natalius_8bit_risc

[/] [natalius_8bit_risc/] [trunk/] [processor_core/] [regfile.v] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 fabioandre 
`timescale 1ns / 1ps
2 
//////////////////////////////////////////////////////////////////////////////////
3 
// Company:
4 
// Engineer:
5 
//
6 
// Create Date:    19:13:24 05/02/2012
7 
// Design Name:
8 
// Module Name:    regfile
9 
// Project Name:
10 
// Target Devices:
11 
// Tool versions:
12 
// Description:
13 
//
14 
// Dependencies:
15 
//
16 
// Revision:
17 
// Revision 0.01 - File Created
18 
// Additional Comments:
19 
//
20 
//////////////////////////////////////////////////////////////////////////////////
21 
module regfile(
22 
    input [7:0] datain,
23 
    input clk, we,
24 
    input [2:0] wa,
25 
    input [2:0] raa,
26 
    input [2:0] rab,
27 
    output [7:0] porta,
28 
    output [7:0] portb
29 
    );
30 
 
31 
 
32 
reg [7:0] mem [7:0];
33 
 
34 
    always@(posedge clk)
35 
         begin
36 
                 mem[0]<=0;
37 
                 if(we)
38 
                        mem[wa]<=datain;
39 
         end
40 
 
41 
assign porta=mem[raa];
42 
assign portb=mem[rab];
43 
 
44 
 
45 
endmodule
46 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.