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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name:    nCore
// Author: STEFAN, Istvan
// Published under GPL
// With exceptions and address masking for multitasking
//////////////////////////////////////////////////////////////////////////////////
module nCore(IP, DP, In, data_out, data_in, clkin);
        parameter inst_mvA=4'd0;//Move reg to a
        parameter inst_coA=4'd1;//Move constant to a[3:0]
        parameter inst_mvB=4'd2;//Move reg to b
        parameter inst_coB=4'd3;//Move constant to b[3:0]
        parameter inst_csB=4'd4;//b[7:4]<-b[3:0];b[3:0]<-constant
        parameter inst_shl=4'd5;//Shift to left, a<reg,carry->flag,if zero->flag
        parameter inst_shr=4'd6;//Shift to right a>>b->reg,carry->flag,if zero->flag
        parameter inst_and=4'd7;//Aritmetical and a&b->reg,if zero->flag
        parameter inst_orr=4'd8;//Aritmetical or  a|b->reg,if zero->flag
        parameter inst_xor=4'd9;//Aritmetical xor a^b->reg,if zero->flag
        parameter inst_add=4'd10;//Unsigned add    a+b->reg,carry->flag,if zero->flag
        parameter inst_sub=4'd11;//Unsigned sub    a-b->reg,carry->flag,if zero->flag
        parameter inst_int=4'd12;
        parameter inst_ire=4'd13;
        parameter inst_Imv=4'd14;//Move IP to reg
        parameter inst_jmp=4'd15;//Move reg to IP if a[0]
 
//buswidth constants
parameter dw=15;
 
        output [dw:0] IP;
        output [dw:0] DP;
        input [7:0] In;
        output [dw:0] data_out;
        input [dw:0] data_in;
        input clkin;
 
//Instructions
        wire [7:0] In;
//Sign of the clock
        wire clk;
//Instruction pointer
        reg [dw:0] IP=0;//init to 0
//Data pointer
        reg [dw:0] DP=0;//init to 0
        //Contact with the data memory
        wire [dw:0] data_in;
        wire [dw:0] data_out;
 
//WDT of 1^20 tick defined at IP counting
//      reg [19:0] wdt=0;//what kind of size? Could/should we change at runtime?
//Source registers
        reg [dw:0] a=0;
        reg [dw:0] b=0;
//General registers
        reg [dw:0] regs [12:0];
        reg [dw:0] mask;//Register for masking addresses
        wire [dw:0] Dmask;//Mask for data address masking
        wire [dw:0] Imask;//Mask for instruction address masking
//Flag register
        reg [9:0] FLAG=0;//init to 0
        wire [9:0] FLAG_new;
        wire F_zero,F_pre_add,F_pre_sub,F_pre_shl,F_pre_shr;
//Interrupt
        reg int=1;//We start in interrupt state to allow setting the environement
//Temp reg of results
        reg [dw:0] c;
//The wires of part results
        wire inst_ALU;//We have an alu-instruction in In[7:4]
        wire [dw:0] w_add;
        wire [dw:0] w_sub;
        wire [dw:0] w_shl;//shift to left
        wire [dw:0] w_shr;//shift to right
        wire [dw:0] w_and;
        wire [dw:0] w_orr;
        wire [dw:0] w_xor;
        wire [3:0] w_con;//load constant
//Begin of ALU
 
assign {F_pre_add,w_add}=a+b;
assign {F_pre_sub,w_sub}=a-b;
assign {F_pre_shl,w_shl}=a<
assign {w_shr,F_pre_shr}=a>>b[3:0];
 
assign w_and=a&b;
assign w_orr=a|b;
assign w_xor=a^b;
assign w_con=In[3:0];
 
assign inst_ALU=((In[7:4]==inst_and)||(In[7:4]==inst_orr)
        ||(In[7:4]==inst_xor)||(In[7:4]==inst_add)
        ||(In[7:4]==inst_shr)||(In[7:4]==inst_shl)
        ||(In[7:4]==inst_sub));
 
//End of ALU
 
//WDT
        reg [19:0] wdt=0;//what kind of size? Could/should we change at runtime?
 
//Instruction pointer
always @(negedge clk)
        if ((In[7:4]==inst_jmp)&&(a[0]))
                begin
                        if(int)//Using the whole address space is allowed only in interrupt
                                IP=c;
                        else
                                IP=Imask&c;//Masking IP address
                end
        else if((In[7:4]==inst_int)||(wdt==20'hFFFFF))//if wdt runned over,
                //we can decide what to do:switch to the next task or kill the current task
                //                                                                                                                                              (was not cooperativ)
                begin
                        IP=16;//begin of the code of the interrupt
                        int=1;
                end
        else if((In[7:4]==inst_ire))
                begin
                        IP=regs[12];
                        int=0;
                end
        else
                IP=IP+1;//Adder!
 
 
always @(posedge clk)
begin
        if(In[7:4]==inst_int)//Every int call is a possible task-switch
                wdt=0;
        else
                wdt=wdt+1;
end
 
//Contact with the data memory
assign data_out=(inst_ALU||(In[7:4]==inst_Imv))&(In[3:0]==14)&~clk?c:data_in;
 
//Setting the flags
        assign F_zero=(c==16'h0000);
 
        assign FLAG_new[0]=inst_ALU?F_zero:FLAG[0];
        assign FLAG_new[3]=(In[7:4]==inst_shl)?F_pre_shl:FLAG[3];
        assign FLAG_new[4]=(In[7:4]==inst_shr)?F_pre_shr:FLAG[4];
        assign FLAG_new[1]=(In[7:4]==inst_add)?F_pre_add:FLAG[1];
        assign FLAG_new[2]=(In[7:4]==inst_sub)?F_pre_sub:FLAG[2];
        assign FLAG_new[5]=(wdt==20'hFFFFF);//WDT overflow
        assign FLAG_new[6]=((~clk)&&(~int)&&((inst_ALU)||(In[7:4]==inst_Imv))
                                &&(mask[1]))?//IP page mismatch//We aren't in int
                        ((Imask&IP)!=(Imask&c))
                        :FLAG[6];
        assign FLAG_new[7]=((~clk)&&(~int)&&((inst_ALU)||(In[7:4]==inst_Imv))
                                &&(mask[2]))?//DP page mismatch
                        ((Dmask&DP)!=(Dmask&c))
                        :FLAG[7];
        assign FLAG_new[8]=((~clk)&&(~int)&&(mask[0])&&//Restricted reg utilisation
                        (inst_ALU||(In[7:4]==inst_Imv)//Restricted reg write
                        ||(In[7:4]==inst_mvA)||(In[7:4]==inst_mvB)
                        ||(In[7:4]==inst_jmp)))?//Restricted reg read
                        ((In[3:0]>8)&&(In[3:0]<13)):FLAG[8];//If this is restricted reg, and we are in preemptiv mode
 
        assign FLAG_new[9]=(In[7:4]==inst_int);//Interrupt call
 
 
//Implementation of the registres
wire i_mvA;
wire i_mvB;
wire i_mvR;
assign i_mvA=((In[7:4]==inst_mvA)||(In[7:4]==inst_coA))&&clk;
assign i_mvB=((In[7:4]==inst_mvB)||(In[7:4]==inst_coB)||(In[7:4]==inst_csB))&&clk;
assign i_mvR=(inst_ALU||(In[7:4]==inst_Imv)||(In[7:4]==inst_int))&&clk;
 
//First source register
always @(negedge i_mvA)
                a=c;
 
//Second source register
always @(negedge i_mvB)
                b=c;
 
//Keep the result
always @(negedge clk)
                case (In[7:4])
                        //inst_mvA
                        inst_coA: c=w_con;
                        //inst_mvB
                        inst_coB: c=w_con;
                        inst_csB: c=w_con;
                        inst_shl: c=w_shl;
                        inst_shr: c=w_shr;
                        inst_and: c=w_and;
                        inst_orr: c=w_orr;
                        inst_xor: c=w_xor;
                        inst_add: c=w_add;
                        inst_sub: c=w_sub;
                        //inst_int
                        //inst_ire
                        inst_Imv: c=IP;
                        //inst_jmp
                        default:
                                case (In[3:0])
                                        15: c=FLAG;
                                        14: c=data_in;
                                        13: c=DP;
                                        default:
                                                c=regs[In[3:0]];
                                endcase
                endcase
 
always @(posedge clk)
begin
        FLAG=FLAG_new;
end
 
always @(negedge i_mvR)//TODO!!!
begin
if(int)
        begin
        if(In[3:0]==15)
                mask=c;
        if(In[3:0]==13)
                DP=c;
        else
                regs[In[3:0]]=c;
        end
else
        begin
//Handle the exceptions
                if((In[7:4]==inst_int)||(wdt==20'hFFFFF))
                begin
                        regs[12]=IP;
                        regs[11]=FLAG_new;
                        regs[10]=a;
                        regs[9]=b;
                end
                else begin
                        if(In[3:0]<13)//Comparator!
                                regs[In[3:0]]=c;
                        else
                                if(In[3:0]==13)
                                                DP=Dmask&c;//Masking DP address
                        end
        end
end
 
//Setting the masks
assign Dmask=32'hFFFF0000>>mask[11:8];
assign Imask=32'hFFFF0000>>mask[7:4];
//regs[15] mask on write in interrupt/ FLAG on read
//data:regs[14]
//DP:regs[13]
//retA:regs[12]:address of the return from interrupt
//Exceptions:
//              mask[0]:1->preemptive, 0->cooperative task
//              mask[1]:page fault, code section (IP)
//              mask[2]:page fault, data section (DP)
//              mask[3]:
BUFGP U1 (.I(clkin),.O(clk));
 
endmodule

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[/] [ncore/] [web_uploads/] [NCORE3.V] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	root	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Module Name: nCore`
4			`// Author: STEFAN, Istvan`
5			`// Published under GPL`
6			`// With exceptions and address masking for multitasking`
7			`//////////////////////////////////////////////////////////////////////////////////`
8			`module nCore(IP, DP, In, data_out, data_in, clkin);`
9			`parameter inst_mvA=4'd0;//Move reg to a`
10			`parameter inst_coA=4'd1;//Move constant to a[3:0]`
11			`parameter inst_mvB=4'd2;//Move reg to b`
12			`parameter inst_coB=4'd3;//Move constant to b[3:0]`
13			`parameter inst_csB=4'd4;//b[7:4]<-b[3:0];b[3:0]<-constant`
14			`parameter inst_shl=4'd5;//Shift to left, a<reg,carry->flag,if zero->flag`
15			`parameter inst_shr=4'd6;//Shift to right a>>b->reg,carry->flag,if zero->flag`
16			`parameter inst_and=4'd7;//Aritmetical and a&b->reg,if zero->flag`
17			`parameter inst_orr=4'd8;//Aritmetical or a\|b->reg,if zero->flag`
18			`parameter inst_xor=4'd9;//Aritmetical xor a^b->reg,if zero->flag`
19			`parameter inst_add=4'd10;//Unsigned add a+b->reg,carry->flag,if zero->flag`
20			`parameter inst_sub=4'd11;//Unsigned sub a-b->reg,carry->flag,if zero->flag`
21			`parameter inst_int=4'd12;`
22			`parameter inst_ire=4'd13;`
23			`parameter inst_Imv=4'd14;//Move IP to reg`
24			`parameter inst_jmp=4'd15;//Move reg to IP if a[0]`
25
26			`//buswidth constants`
27			`parameter dw=15;`
28
29			`output [dw:0] IP;`
30			`output [dw:0] DP;`
31			`input [7:0] In;`
32			`output [dw:0] data_out;`
33			`input [dw:0] data_in;`
34			`input clkin;`
35
36			`//Instructions`
37			`wire [7:0] In;`
38			`//Sign of the clock`
39			`wire clk;`
40			`//Instruction pointer`
41			`reg [dw:0] IP=0;//init to 0`
42			`//Data pointer`
43			`reg [dw:0] DP=0;//init to 0`
44			`//Contact with the data memory`
45			`wire [dw:0] data_in;`
46			`wire [dw:0] data_out;`
47
48			`//WDT of 1^20 tick defined at IP counting`
49			`// reg [19:0] wdt=0;//what kind of size? Could/should we change at runtime?`
50			`//Source registers`
51			`reg [dw:0] a=0;`
52			`reg [dw:0] b=0;`
53			`//General registers`
54			`reg [dw:0] regs [12:0];`
55			`reg [dw:0] mask;//Register for masking addresses`
56			`wire [dw:0] Dmask;//Mask for data address masking`
57			`wire [dw:0] Imask;//Mask for instruction address masking`
58			`//Flag register`
59			`reg [9:0] FLAG=0;//init to 0`
60			`wire [9:0] FLAG_new;`
61			`wire F_zero,F_pre_add,F_pre_sub,F_pre_shl,F_pre_shr;`
62			`//Interrupt`
63			`reg int=1;//We start in interrupt state to allow setting the environement`
64			`//Temp reg of results`
65			`reg [dw:0] c;`
66			`//The wires of part results`
67			`wire inst_ALU;//We have an alu-instruction in In[7:4]`
68			`wire [dw:0] w_add;`
69			`wire [dw:0] w_sub;`
70			`wire [dw:0] w_shl;//shift to left`
71			`wire [dw:0] w_shr;//shift to right`
72			`wire [dw:0] w_and;`
73			`wire [dw:0] w_orr;`
74			`wire [dw:0] w_xor;`
75			`wire [3:0] w_con;//load constant`
76			`//Begin of ALU`
77
78			`assign {F_pre_add,w_add}=a+b;`
79			`assign {F_pre_sub,w_sub}=a-b;`
80			`assign {F_pre_shl,w_shl}=a<`
81			`assign {w_shr,F_pre_shr}=a>>b[3:0];`
82
83			`assign w_and=a&b;`
84			`assign w_orr=a\|b;`
85			`assign w_xor=a^b;`
86			`assign w_con=In[3:0];`
87
88			`assign inst_ALU=((In[7:4]==inst_and)\|\|(In[7:4]==inst_orr)`
89			`\|\|(In[7:4]==inst_xor)\|\|(In[7:4]==inst_add)`
90			`\|\|(In[7:4]==inst_shr)\|\|(In[7:4]==inst_shl)`
91			`\|\|(In[7:4]==inst_sub));`
92
93			`//End of ALU`
94
95			`//WDT`
96			`reg [19:0] wdt=0;//what kind of size? Could/should we change at runtime?`
97
98			`//Instruction pointer`
99			`always @(negedge clk)`
100			`if ((In[7:4]==inst_jmp)&&(a[0]))`
101			`begin`
102			`if(int)//Using the whole address space is allowed only in interrupt`
103			`IP=c;`
104			`else`
105			`IP=Imask&c;//Masking IP address`
106			`end`
107			`else if((In[7:4]==inst_int)\|\|(wdt==20'hFFFFF))//if wdt runned over,`
108			`//we can decide what to do:switch to the next task or kill the current task`
109			`// (was not cooperativ)`
110			`begin`
111			`IP=16;//begin of the code of the interrupt`
112			`int=1;`
113			`end`
114			`else if((In[7:4]==inst_ire))`
115			`begin`
116			`IP=regs[12];`
117			`int=0;`
118			`end`
119			`else`
120			`IP=IP+1;//Adder!`
121
122
123			`always @(posedge clk)`
124			`begin`
125			`if(In[7:4]==inst_int)//Every int call is a possible task-switch`
126			`wdt=0;`
127			`else`
128			`wdt=wdt+1;`
129			`end`
130
131			`//Contact with the data memory`
132			`assign data_out=(inst_ALU\|\|(In[7:4]==inst_Imv))&(In[3:0]==14)&~clk?c:data_in;`
133
134			`//Setting the flags`
135			`assign F_zero=(c==16'h0000);`
136
137			`assign FLAG_new[0]=inst_ALU?F_zero:FLAG[0];`
138			`assign FLAG_new[3]=(In[7:4]==inst_shl)?F_pre_shl:FLAG[3];`
139			`assign FLAG_new[4]=(In[7:4]==inst_shr)?F_pre_shr:FLAG[4];`
140			`assign FLAG_new[1]=(In[7:4]==inst_add)?F_pre_add:FLAG[1];`
141			`assign FLAG_new[2]=(In[7:4]==inst_sub)?F_pre_sub:FLAG[2];`
142			`assign FLAG_new[5]=(wdt==20'hFFFFF);//WDT overflow`
143			`assign FLAG_new[6]=((~clk)&&(~int)&&((inst_ALU)\|\|(In[7:4]==inst_Imv))`
144			`&&(mask[1]))?//IP page mismatch//We aren't in int`
145			`((Imask&IP)!=(Imask&c))`
146			`:FLAG[6];`
147			`assign FLAG_new[7]=((~clk)&&(~int)&&((inst_ALU)\|\|(In[7:4]==inst_Imv))`
148			`&&(mask[2]))?//DP page mismatch`
149			`((Dmask&DP)!=(Dmask&c))`
150			`:FLAG[7];`
151			`assign FLAG_new[8]=((~clk)&&(~int)&&(mask[0])&&//Restricted reg utilisation`
152			`(inst_ALU\|\|(In[7:4]==inst_Imv)//Restricted reg write`
153			`\|\|(In[7:4]==inst_mvA)\|\|(In[7:4]==inst_mvB)`
154			`\|\|(In[7:4]==inst_jmp)))?//Restricted reg read`
155			`((In[3:0]>8)&&(In[3:0]<13)):FLAG[8];//If this is restricted reg, and we are in preemptiv mode`
156
157			`assign FLAG_new[9]=(In[7:4]==inst_int);//Interrupt call`
158
159
160			`//Implementation of the registres`
161			`wire i_mvA;`
162			`wire i_mvB;`
163			`wire i_mvR;`
164			`assign i_mvA=((In[7:4]==inst_mvA)\|\|(In[7:4]==inst_coA))&&clk;`
165			`assign i_mvB=((In[7:4]==inst_mvB)\|\|(In[7:4]==inst_coB)\|\|(In[7:4]==inst_csB))&&clk;`
166			`assign i_mvR=(inst_ALU\|\|(In[7:4]==inst_Imv)\|\|(In[7:4]==inst_int))&&clk;`
167
168			`//First source register`
169			`always @(negedge i_mvA)`
170			`a=c;`
171
172			`//Second source register`
173			`always @(negedge i_mvB)`
174			`b=c;`
175
176			`//Keep the result`
177			`always @(negedge clk)`
178			`case (In[7:4])`
179			`//inst_mvA`
180			`inst_coA: c=w_con;`
181			`//inst_mvB`
182			`inst_coB: c=w_con;`
183			`inst_csB: c=w_con;`
184			`inst_shl: c=w_shl;`
185			`inst_shr: c=w_shr;`
186			`inst_and: c=w_and;`
187			`inst_orr: c=w_orr;`
188			`inst_xor: c=w_xor;`
189			`inst_add: c=w_add;`
190			`inst_sub: c=w_sub;`
191			`//inst_int`
192			`//inst_ire`
193			`inst_Imv: c=IP;`
194			`//inst_jmp`
195			`default:`
196			`case (In[3:0])`
197			`15: c=FLAG;`
198			`14: c=data_in;`
199			`13: c=DP;`
200			`default:`
201			`c=regs[In[3:0]];`
202			`endcase`
203			`endcase`
204
205			`always @(posedge clk)`
206			`begin`
207			`FLAG=FLAG_new;`
208			`end`
209
210			`always @(negedge i_mvR)//TODO!!!`
211			`begin`
212			`if(int)`
213			`begin`
214			`if(In[3:0]==15)`
215			`mask=c;`
216			`if(In[3:0]==13)`
217			`DP=c;`
218			`else`
219			`regs[In[3:0]]=c;`
220			`end`
221			`else`
222			`begin`
223			`//Handle the exceptions`
224			`if((In[7:4]==inst_int)\|\|(wdt==20'hFFFFF))`
225			`begin`
226			`regs[12]=IP;`
227			`regs[11]=FLAG_new;`
228			`regs[10]=a;`
229			`regs[9]=b;`
230			`end`
231			`else begin`
232			`if(In[3:0]<13)//Comparator!`
233			`regs[In[3:0]]=c;`
234			`else`
235			`if(In[3:0]==13)`
236			`DP=Dmask&c;//Masking DP address`
237			`end`
238			`end`
239			`end`
240
241			`//Setting the masks`
242			`assign Dmask=32'hFFFF0000>>mask[11:8];`
243			`assign Imask=32'hFFFF0000>>mask[7:4];`
244			`//regs[15] mask on write in interrupt/ FLAG on read`
245			`//data:regs[14]`
246			`//DP:regs[13]`
247			`//retA:regs[12]:address of the return from interrupt`
248			`//Exceptions:`
249			`// mask[0]:1->preemptive, 0->cooperative task`
250			`// mask[1]:page fault, code section (IP)`
251			`// mask[2]:page fault, data section (DP)`
252			`// mask[3]:`
253			`BUFGP U1 (.I(clkin),.O(clk));`
254
255			`endmodule`