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/*
NEC     IR PROTOCOL DECODER
DESCRIPTION
        Demo for NEC IR decoder.
IO DETAILS
        clk             >>      Clock
        rst             >>      Reset
        ir              >>      IR input
        led             >>      Decoded value displayed on leds
AUTHOR:
        Jagadeesh J, Design Engineer.
COMPANY:
        KENOSYS EMBEDDED SOLUTIONS, SALEM, TAMILNADU, INDIA
 */
module nec (
        input clk,rst,
        input ir,
        output reg [7:0]led
        );
 
wire ir_in;
assign ir_in = ir;
 
 
reg [8:0]state_reg, state_next;
reg [31:0]led_reg, led_next;
reg [19:0]count_reg;
wire [19:0]count_next;
reg c_bit_next, c_bit_reg;
reg done_tick;
reg c_load;
wire [7:0]led_tmp;
 
//States
localparam [8:0] IDLE            =       9'h001,
                                        START           =       9'h002,
                                        SYNC            =       9'h004,
                                        WAIT_HIGH       =       9'h008,
                                        FETCH           =       9'h010,
                                        BCOUNT          =       9'h020,
                                        WAIT_LOW        =       9'h040,
                                        CHECK           =       9'h080,
                                        DONE            =       9'h100;
 
localparam [19:0]        START_TIME      =       20'd448000,                      //448000,
                                        SYNC_TIME       =       20'd210000,                      //210000,
                                        CENTER          =       20'd42000;                       //42000;
 
//Pulse Edge detection circuit
reg [1:0]e_bit;
wire f_edge, r_edge;
always@(posedge clk, negedge rst)
        if(!rst)
                e_bit   <=      2'b00;
        else
                e_bit <= {e_bit[0],ir_in};
 
assign f_edge = e_bit[1] & (~e_bit[0]);
assign r_edge = (~e_bit[1]) & e_bit[0];
 
//Registers     
always@(posedge clk, negedge rst)
begin
        if(!rst)
        begin
                state_reg       <=              IDLE;
                led_reg         <=              32'h80000000;
                count_reg       <=              20'h00000;
                c_bit_reg       <=              1'b0;
                led                     <=              8'h00;
        end
        else
        begin
                state_reg       <=              state_next;
                led_reg         <=              led_next;
                count_reg       <=              count_next;
                c_bit_reg       <=              c_bit_next;
                led                     <=              led_tmp;
        end
end
 
assign count_next = (c_load)?count_reg+1'b1:20'h00000;
 
always@*
begin
        state_next              =       state_reg;
        led_next                =       led_reg;
        done_tick               =       1'b0;
        c_load                  =       1'b0;
        c_bit_next              =       c_bit_reg;
        case(state_reg)
                IDLE:
                begin
                        if(f_edge)
                                state_next = START;
                end
                START:
                begin
                        c_load = 1'b1;
                        if(r_edge)
                        begin
                                if(count_reg > START_TIME)
                                begin
                                        state_next      =       SYNC;
                                        c_load = 1'b0;
                                end
                                else
                                begin
                                        state_next      =       IDLE;
                                        c_load = 1'b0;
                                end
                        end
                end
                SYNC:
                begin
                        c_load = 1'b1;
                        if(f_edge)
                        begin
                                if(count_reg > SYNC_TIME)
                                begin
                                        state_next      =       WAIT_HIGH;
                                        c_load = 1'b0;
                                end
                                else
                                begin
                                        state_next      =       IDLE;
                                        c_load = 1'b0;
                                end
                        end
                end
                WAIT_HIGH:
                begin
                        if(r_edge)
                                state_next      =       FETCH;
                end
                WAIT_LOW:
                begin
                        if(f_edge)
                                state_next      =       WAIT_HIGH;
                end
                FETCH:
                begin
                        c_load = 1'b1;
                        if(count_reg > CENTER)
                        begin
                                c_bit_next      =       led_reg[0];
                                led_next        =       {ir_in,led_reg[31:1]};
                                c_load = 1'b0;
                                state_next      =       BCOUNT;
                        end
                end
                BCOUNT:
                begin
                        if(c_bit_reg)
                                state_next = DONE;
                        else
                        begin
                                if(led_reg[31])
                                        state_next      =       WAIT_LOW;
                                else
                                        state_next      =       WAIT_HIGH;
                        end
                end
                DONE:
                begin
                        if(((led_reg[7:0]^led_reg[15:8]) == 8'hff)&&((led_reg[23:16]^led_reg[31:24]) == 8'hff))
                        begin
                                done_tick = 1'b1;
                                led_next        =       32'h80000000;
                                state_next      =       IDLE;
                        end
                end
        endcase
end
assign led_tmp = (done_tick)?led_reg[23:16]:led;
endmodule
 

Line No.	Rev	Author	Line
1	2	jagadeeshj	`/*`
2			`NEC IR PROTOCOL DECODER`
3			`DESCRIPTION`
4			`Demo for NEC IR decoder.`
5			`IO DETAILS`
6			`clk >> Clock`
7			`rst >> Reset`
8			`ir >> IR input`
9			`led >> Decoded value displayed on leds`
10			`AUTHOR:`
11			`Jagadeesh J, Design Engineer.`
12			`COMPANY:`
13			`KENOSYS EMBEDDED SOLUTIONS, SALEM, TAMILNADU, INDIA`
14			`*/`
15			`module nec (`
16			`input clk,rst,`
17			`input ir,`
18			`output reg [7:0]led`
19			`);`
20
21			`wire ir_in;`
22			`assign ir_in = ir;`
23
24
25			`reg [8:0]state_reg, state_next;`
26			`reg [31:0]led_reg, led_next;`
27			`reg [19:0]count_reg;`
28			`wire [19:0]count_next;`
29			`reg c_bit_next, c_bit_reg;`
30			`reg done_tick;`
31			`reg c_load;`
32			`wire [7:0]led_tmp;`
33
34			`//States`
35			`localparam [8:0] IDLE = 9'h001,`
36			`START = 9'h002,`
37			`SYNC = 9'h004,`
38			`WAIT_HIGH = 9'h008,`
39			`FETCH = 9'h010,`
40			`BCOUNT = 9'h020,`
41			`WAIT_LOW = 9'h040,`
42			`CHECK = 9'h080,`
43			`DONE = 9'h100;`
44
45			`localparam [19:0] START_TIME = 20'd448000, //448000,`
46			`SYNC_TIME = 20'd210000, //210000,`
47			`CENTER = 20'd42000; //42000;`
48
49			`//Pulse Edge detection circuit`
50			`reg [1:0]e_bit;`
51			`wire f_edge, r_edge;`
52			`always@(posedge clk, negedge rst)`
53			`if(!rst)`
54			`e_bit <= 2'b00;`
55			`else`
56			`e_bit <= {e_bit[0],ir_in};`
57
58			`assign f_edge = e_bit[1] & (~e_bit[0]);`
59			`assign r_edge = (~e_bit[1]) & e_bit[0];`
60
61			`//Registers`
62			`always@(posedge clk, negedge rst)`
63			`begin`
64			`if(!rst)`
65			`begin`
66			`state_reg <= IDLE;`
67			`led_reg <= 32'h80000000;`
68			`count_reg <= 20'h00000;`
69			`c_bit_reg <= 1'b0;`
70			`led <= 8'h00;`
71			`end`
72			`else`
73			`begin`
74			`state_reg <= state_next;`
75			`led_reg <= led_next;`
76			`count_reg <= count_next;`
77			`c_bit_reg <= c_bit_next;`
78			`led <= led_tmp;`
79			`end`
80			`end`
81
82			`assign count_next = (c_load)?count_reg+1'b1:20'h00000;`
83
84			`always@*`
85			`begin`
86			`state_next = state_reg;`
87			`led_next = led_reg;`
88			`done_tick = 1'b0;`
89			`c_load = 1'b0;`
90			`c_bit_next = c_bit_reg;`
91			`case(state_reg)`
92			`IDLE:`
93			`begin`
94			`if(f_edge)`
95			`state_next = START;`
96			`end`
97			`START:`
98			`begin`
99			`c_load = 1'b1;`
100			`if(r_edge)`
101			`begin`
102			`if(count_reg > START_TIME)`
103			`begin`
104			`state_next = SYNC;`
105			`c_load = 1'b0;`
106			`end`
107			`else`
108			`begin`
109			`state_next = IDLE;`
110			`c_load = 1'b0;`
111			`end`
112			`end`
113			`end`
114			`SYNC:`
115			`begin`
116			`c_load = 1'b1;`
117			`if(f_edge)`
118			`begin`
119			`if(count_reg > SYNC_TIME)`
120			`begin`
121			`state_next = WAIT_HIGH;`
122			`c_load = 1'b0;`
123			`end`
124			`else`
125			`begin`
126			`state_next = IDLE;`
127			`c_load = 1'b0;`
128			`end`
129			`end`
130			`end`
131			`WAIT_HIGH:`
132			`begin`
133			`if(r_edge)`
134			`state_next = FETCH;`
135			`end`
136			`WAIT_LOW:`
137			`begin`
138			`if(f_edge)`
139			`state_next = WAIT_HIGH;`
140			`end`
141			`FETCH:`
142			`begin`
143			`c_load = 1'b1;`
144			`if(count_reg > CENTER)`
145			`begin`
146			`c_bit_next = led_reg[0];`
147			`led_next = {ir_in,led_reg[31:1]};`
148			`c_load = 1'b0;`
149			`state_next = BCOUNT;`
150			`end`
151			`end`
152			`BCOUNT:`
153			`begin`
154			`if(c_bit_reg)`
155			`state_next = DONE;`
156			`else`
157			`begin`
158			`if(led_reg[31])`
159			`state_next = WAIT_LOW;`
160			`else`
161			`state_next = WAIT_HIGH;`
162			`end`
163			`end`
164			`DONE:`
165			`begin`
166			`if(((led_reg[7:0]^led_reg[15:8]) == 8'hff)&&((led_reg[23:16]^led_reg[31:24]) == 8'hff))`
167			`begin`
168			`done_tick = 1'b1;`
169			`led_next = 32'h80000000;`
170			`state_next = IDLE;`
171			`end`
172			`end`
173			`endcase`
174			`end`
175			`assign led_tmp = (done_tick)?led_reg[23:16]:led;`
176			`endmodule`
177

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[/] [nec_ir_decoder/] [trunk/] [rtl/] [nec.v] - Blame information for rev 2