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[/] [nec_ir_decoder/] [trunk/] [rtl/] [nec.v] - Blame information for rev 3

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/*
 This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
 
AUTHOR:
        Jagadeesh J, Design Engineer.
        Email : jagadeeshj@kenosys.in
        Tel   : 91-8098701730
COMPANY:
        KENOSYS EMBEDDED SOLUTIONS, SALEM, TAMILNADU, INDIA
 */
 
module nec (
        input clk,rst,
        input ir,
        output reg [7:0]led
        );
 
wire ir_in;
assign ir_in = ir;
 
 
reg [8:0]state_reg, state_next;
reg [31:0]led_reg, led_next;
reg [19:0]count_reg;
wire [19:0]count_next;
reg c_bit_next, c_bit_reg;
reg done_tick;
reg c_load;
wire [7:0]led_tmp;
 
//States
localparam [8:0] IDLE            =       9'h001,
                                        START           =       9'h002,
                                        SYNC            =       9'h004,
                                        WAIT_HIGH       =       9'h008,
                                        FETCH           =       9'h010,
                                        BCOUNT          =       9'h020,
                                        WAIT_LOW        =       9'h040,
                                        CHECK           =       9'h080,
                                        DONE            =       9'h100;
 
localparam [19:0]        START_TIME      =       20'd448000,                      //448000,
                                        SYNC_TIME       =       20'd210000,                      //210000,
                                        CENTER          =       20'd42000;                       //42000;
 
//Pulse Edge detection circuit
reg [1:0]e_bit;
wire f_edge, r_edge;
always@(posedge clk, negedge rst)
        if(!rst)
                e_bit   <=      2'b00;
        else
                e_bit <= {e_bit[0],ir_in};
 
assign f_edge = e_bit[1] & (~e_bit[0]);
assign r_edge = (~e_bit[1]) & e_bit[0];
 
//Registers     
always@(posedge clk, negedge rst)
begin
        if(!rst)
        begin
                state_reg       <=              IDLE;
                led_reg         <=              32'h80000000;
                count_reg       <=              20'h00000;
                c_bit_reg       <=              1'b0;
                led                     <=              8'h00;
        end
        else
        begin
                state_reg       <=              state_next;
                led_reg         <=              led_next;
                count_reg       <=              count_next;
                c_bit_reg       <=              c_bit_next;
                led                     <=              led_tmp;
        end
end
 
assign count_next = (c_load)?count_reg+1'b1:20'h00000;
 
always@*
begin
        state_next              =       state_reg;
        led_next                =       led_reg;
        done_tick               =       1'b0;
        c_load                  =       1'b0;
        c_bit_next              =       c_bit_reg;
        case(state_reg)
                IDLE:
                begin
                        if(f_edge)
                                state_next = START;
                end
                START:
                begin
                        c_load = 1'b1;
                        if(r_edge)
                        begin
                                if(count_reg > START_TIME)
                                begin
                                        state_next      =       SYNC;
                                        c_load = 1'b0;
                                end
                                else
                                begin
                                        state_next      =       IDLE;
                                        c_load = 1'b0;
                                end
                        end
                end
                SYNC:
                begin
                        c_load = 1'b1;
                        if(f_edge)
                        begin
                                if(count_reg > SYNC_TIME)
                                begin
                                        state_next      =       WAIT_HIGH;
                                        c_load = 1'b0;
                                end
                                else
                                begin
                                        state_next      =       IDLE;
                                        c_load = 1'b0;
                                end
                        end
                end
                WAIT_HIGH:
                begin
                        if(r_edge)
                                state_next      =       FETCH;
                end
                WAIT_LOW:
                begin
                        if(f_edge)
                                state_next      =       WAIT_HIGH;
                end
                FETCH:
                begin
                        c_load = 1'b1;
                        if(count_reg > CENTER)
                        begin
                                c_bit_next      =       led_reg[0];
                                led_next        =       {ir_in,led_reg[31:1]};
                                c_load = 1'b0;
                                state_next      =       BCOUNT;
                        end
                end
                BCOUNT:
                begin
                        if(c_bit_reg)
                                state_next = DONE;
                        else
                        begin
                                if(led_reg[31])
                                        state_next      =       WAIT_LOW;
                                else
                                        state_next      =       WAIT_HIGH;
                        end
                end
                DONE:
                begin
                        if(((led_reg[7:0]^led_reg[15:8]) == 8'hff)&&((led_reg[23:16]^led_reg[31:24]) == 8'hff))
                        begin
                                done_tick = 1'b1;
                                led_next        =       32'h80000000;
                                state_next      =       IDLE;
                        end
                end
        endcase
end
assign led_tmp = (done_tick)?led_reg[23:16]:led;
endmodule
 

Line No.	Rev	Author	Line
1	2	jagadeeshj	`/*`
2	3	jagadeeshj	`This program is free software: you can redistribute it and/or modify`
3			`it under the terms of the GNU General Public License as published by`
4			`the Free Software Foundation, either version 3 of the License, or`
5			`(at your option) any later version.`
6
7			`This program is distributed in the hope that it will be useful,`
8			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
9			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
10			`GNU General Public License for more details.`
11
12			`You should have received a copy of the GNU General Public License`
13			`along with this program. If not, see <http://www.gnu.org/licenses/>.`
14
15
16	2	jagadeeshj	`AUTHOR:`
17			`Jagadeesh J, Design Engineer.`
18	3	jagadeeshj	`Email : jagadeeshj@kenosys.in`
19			`Tel : 91-8098701730`
20	2	jagadeeshj	`COMPANY:`
21			`KENOSYS EMBEDDED SOLUTIONS, SALEM, TAMILNADU, INDIA`
22			`*/`
23	3	jagadeeshj
24	2	jagadeeshj	`module nec (`
25			`input clk,rst,`
26			`input ir,`
27			`output reg [7:0]led`
28			`);`
29
30			`wire ir_in;`
31			`assign ir_in = ir;`
32
33
34			`reg [8:0]state_reg, state_next;`
35			`reg [31:0]led_reg, led_next;`
36			`reg [19:0]count_reg;`
37			`wire [19:0]count_next;`
38			`reg c_bit_next, c_bit_reg;`
39			`reg done_tick;`
40			`reg c_load;`
41			`wire [7:0]led_tmp;`
42
43			`//States`
44			`localparam [8:0] IDLE = 9'h001,`
45			`START = 9'h002,`
46			`SYNC = 9'h004,`
47			`WAIT_HIGH = 9'h008,`
48			`FETCH = 9'h010,`
49			`BCOUNT = 9'h020,`
50			`WAIT_LOW = 9'h040,`
51			`CHECK = 9'h080,`
52			`DONE = 9'h100;`
53
54			`localparam [19:0] START_TIME = 20'd448000, //448000,`
55			`SYNC_TIME = 20'd210000, //210000,`
56			`CENTER = 20'd42000; //42000;`
57
58			`//Pulse Edge detection circuit`
59			`reg [1:0]e_bit;`
60			`wire f_edge, r_edge;`
61			`always@(posedge clk, negedge rst)`
62			`if(!rst)`
63			`e_bit <= 2'b00;`
64			`else`
65			`e_bit <= {e_bit[0],ir_in};`
66
67			`assign f_edge = e_bit[1] & (~e_bit[0]);`
68			`assign r_edge = (~e_bit[1]) & e_bit[0];`
69
70			`//Registers`
71			`always@(posedge clk, negedge rst)`
72			`begin`
73			`if(!rst)`
74			`begin`
75			`state_reg <= IDLE;`
76			`led_reg <= 32'h80000000;`
77			`count_reg <= 20'h00000;`
78			`c_bit_reg <= 1'b0;`
79			`led <= 8'h00;`
80			`end`
81			`else`
82			`begin`
83			`state_reg <= state_next;`
84			`led_reg <= led_next;`
85			`count_reg <= count_next;`
86			`c_bit_reg <= c_bit_next;`
87			`led <= led_tmp;`
88			`end`
89			`end`
90
91			`assign count_next = (c_load)?count_reg+1'b1:20'h00000;`
92
93			`always@*`
94			`begin`
95			`state_next = state_reg;`
96			`led_next = led_reg;`
97			`done_tick = 1'b0;`
98			`c_load = 1'b0;`
99			`c_bit_next = c_bit_reg;`
100			`case(state_reg)`
101			`IDLE:`
102			`begin`
103			`if(f_edge)`
104			`state_next = START;`
105			`end`
106			`START:`
107			`begin`
108			`c_load = 1'b1;`
109			`if(r_edge)`
110			`begin`
111			`if(count_reg > START_TIME)`
112			`begin`
113			`state_next = SYNC;`
114			`c_load = 1'b0;`
115			`end`
116			`else`
117			`begin`
118			`state_next = IDLE;`
119			`c_load = 1'b0;`
120			`end`
121			`end`
122			`end`
123			`SYNC:`
124			`begin`
125			`c_load = 1'b1;`
126			`if(f_edge)`
127			`begin`
128			`if(count_reg > SYNC_TIME)`
129			`begin`
130			`state_next = WAIT_HIGH;`
131			`c_load = 1'b0;`
132			`end`
133			`else`
134			`begin`
135			`state_next = IDLE;`
136			`c_load = 1'b0;`
137			`end`
138			`end`
139			`end`
140			`WAIT_HIGH:`
141			`begin`
142			`if(r_edge)`
143			`state_next = FETCH;`
144			`end`
145			`WAIT_LOW:`
146			`begin`
147			`if(f_edge)`
148			`state_next = WAIT_HIGH;`
149			`end`
150			`FETCH:`
151			`begin`
152			`c_load = 1'b1;`
153			`if(count_reg > CENTER)`
154			`begin`
155			`c_bit_next = led_reg[0];`
156			`led_next = {ir_in,led_reg[31:1]};`
157			`c_load = 1'b0;`
158			`state_next = BCOUNT;`
159			`end`
160			`end`
161			`BCOUNT:`
162			`begin`
163			`if(c_bit_reg)`
164			`state_next = DONE;`
165			`else`
166			`begin`
167			`if(led_reg[31])`
168			`state_next = WAIT_LOW;`
169			`else`
170			`state_next = WAIT_HIGH;`
171			`end`
172			`end`
173			`DONE:`
174			`begin`
175			`if(((led_reg[7:0]^led_reg[15:8]) == 8'hff)&&((led_reg[23:16]^led_reg[31:24]) == 8'hff))`
176			`begin`
177			`done_tick = 1'b1;`
178			`led_next = 32'h80000000;`
179			`state_next = IDLE;`
180			`end`
181			`end`
182			`endcase`
183			`end`
184			`assign led_tmp = (done_tick)?led_reg[23:16]:led;`
185			`endmodule`
186

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[/] [nec_ir_decoder/] [trunk/] [rtl/] [nec.v] - Blame information for rev 3