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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V)
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[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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## Introduction
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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**[NEORV32 CPU](#CPU-Features)**
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The CPU implements an `rv32i RISC-V` core with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and
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`PMP` (physical memory protection) extensions. It passes the official [RISC-V compliance tests](https://github.com/stnolting/neorv32_riscv_compliance)
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and is compliant to the *Unprivileged ISA Specification [Version 2.2](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)*
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and a subset of the *Privileged Architecture Specification [Version 1.12-draft](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)*.
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If you do not want to use the NEORV32 Processor setup, you can also use the CPU in
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stand-alone mode and build your own SoC around it.
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**[NEORV32 Processor](#Processor-Features)**
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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memories and an external bus interface for connectivity and custom extension.
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All optional features and modules beyond the base CPU can be enabled and configured via
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[VHDL generics](#Top-Entities).
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The processor is intended as ready-to-use auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller. Its top entity can be directly
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synthesized for any target technology without modifications.
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This project comes with a complete software ecosystem that features core
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libraries for high-level usage of the provided functions and peripherals,
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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even a builtin bootloader for easy program upload via UART.
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All software source files provide a doxygen-based documentary (available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)).
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**[How to get started?](Getting-Started)**
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The processor is intended to work "out of the box". Just synthesize the
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain) by yourself, you can also
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download [pre-compiled toolchains](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look at the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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This project is hosted on [GitHub](https://github.com/stnolting/neorv32) and [opencores.org](https://opencores.org/projects/neorv32).
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A not-so-complete project log can be found on [hackaday.io](https://hackaday.io/project/174167-the-neorv32-risc-v-processor).
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###  Key Features
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- RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions
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- GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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- Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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- [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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- Detailed [datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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- Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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- Fully synchronous design, no latches, no gated clocks
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- Small hardware footprint and high operating frequency
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- Highly configurable CPU and processor setup
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- [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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### Design Principles
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 * From zero to main(): Completely open source and documented.
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 * Plain VHDL without technology-specific parts like attributes, macros or primitives.
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 * Easy to use – working out of the box.
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 * Clean synchronous design, no wacky combinatorial interfaces.
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 * Be as small as possible – but with a reasonable size-performance tradeoff.
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 * The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project component                                                               | CI status | Note     |
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|:--------------------------------------------------------------------------------|:----------|:---------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32)                       | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) | [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt)          | [![Build Status](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### To-Do / Wish List
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- Add AXI(-Lite) bridges
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- Synthesis results (+ wrappers?) for more platforms
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- Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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- Implement further CPU extensions:
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  - Atomic operations (`A`)
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  - Bitmanipulation operations (`B`), when they are "official"
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  - Floating-point instructions (`F`)
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  - ...
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## Features
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### Processor Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor top's generics.
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- Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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- Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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- Optional machine system timer (**MTIME**), RISC-V-compliant
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- Optional universal asynchronous receiver and transmitter (**UART**)
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- Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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- Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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- Optional general purpose parallel IO port (**GPIO**), 16xOut & 16xIn, with pin-change interrupt
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- Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**)
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- Optional watchdog timer (**WDT**)
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- Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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- Optional GARO-based true random number generator (**TRNG**)
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- Optional dummy device (**DEVNULL**); used for debugging; can also be used for *fast* simulation console output
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- Optional custom functions unit (**CFU**) for tightly-coupled custom co-processors
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- System configuration information memory to check hardware configuration by software (**SYSINFO**)
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### CPU Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_cpu.png)
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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**General**:
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  * Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via bus I/D mux)
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  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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  * No hardware support of unaligned accesses - they will trigger an exception
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  * Little-endian byte order
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  * All reserved or unimplemented instructions will raise an illegal instruction exception
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  * Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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**RV32I base instruction set** (`I` extension):
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  * ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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  * Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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  * Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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  * System instructions: `ECALL` `EBREAK` `FENCE`
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**Compressed instructions** (`C` extension):
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  * ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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  * Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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  * Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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  * Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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  * Reduced register file (only the 16 lowest registers)
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**Integer multiplication and division hardware** (`M` extension):
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  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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  * Division instructions: `DIV` `DIVU` `REM` `REMU`
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  * By default, the multiplier and divider cores use an iterative bit-serial processing scheme
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  * Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
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**Privileged architecture / CSR access** (`Zicsr` extension):
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  * Privilege levels: `M-mode` (Machine mode)
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  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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  * System instructions: `MRET` `WFI`
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  * Counter CSRs: `[m]cycle[h]` `[m]instret[h]` `time[h]`
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  * Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause`(read-only!) `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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  * Supported exceptions and interrupts:
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    * Misaligned instruction address
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    * Instruction access fault
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    * Illegal instruction
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    * Breakpoint (via `ebreak` instruction)
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    * Load address misaligned
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    * Load access fault
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    * Store address misaligned
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    * Store access fault
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    * Environment call from M-mode (via `ecall` instruction)
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    * Machine timer interrupt `mti` (via processor's MTIME unit)
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    * Machine software interrupt `msi` (via external signal)
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    * Machine external interrupt `mei` (via external signal)
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    * Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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  * Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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  * System instructions: `FENCE.I`
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**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
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  * Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
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### Non-RISC-V-Compliant Issues
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime
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* `mcause` CSR is read-only
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* The `[m]cycleh` and `[m]instreth` CSR counters are only 20-bit wide (in contrast to original 32-bit)
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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* All invalid, unimplemented, unspecified or disabled instructions will trigger an illegal instruction exception
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### NEORV32-Specific CPU Extensions
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The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
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## FPGA Implementation Results
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### NEORV32 CPU
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This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (e.g., no PMP). No constraints were used at all.
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Results generated for hardware version: `1.3.6.5`
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| CPU Configuration                | LEs        | FFs      | Memory bits | DSPs | f_max   |
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|:---------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
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| `rv32i`                          |       1113 |      479 |       2048  |    0 | 109 MHz |
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| `rv32i`   + `Zicsr` + `Zifencei` |       1851 |      817 |       2048  |    0 | 100 MHz |
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| `rv32im`  + `Zicsr` + `Zifencei` |       2462 |     1065 |       2048  |    0 | 100 MHz |
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| `rv32imc` + `Zicsr` + `Zifencei` |       2714 |     1064 |       2048  |    0 | 100 MHz |
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| `rv32emc` + `Zicsr` + `Zifencei` |       2717 |     1064 |       1024  |    0 | 100 MHz |
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### NEORV32 Processor-Internal Peripherals and Memories
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Results generated for hardware version: `1.3.6.5`
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| Module    | Description                                     | LEs | FFs | Memory bits | DSPs |
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|:----------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM  | Bootloader ROM (4kB)                            |   4 |   1 |      32 768 |    0 |
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| BUSSWITCH | Mux for CPU I & D interfaces                    |  62 |   8 |           0 |    0 |
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| CFU       | Custom functions unit                           |   - |   - |           - |    - |
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| DEVNULL   | Dummy device                                    |   3 |   1 |           0 |    0 |
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| DMEM      | Processor-internal data memory (8kB)            |  12 |   2 |      65 536 |    0 |
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| GPIO      | General purpose input/output ports              |  40 |  33 |           0 |    0 |
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| IMEM      | Processor-internal instruction memory (16kb)    |   7 |   2 |     131 072 |    0 |
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| MTIME     | Machine system timer                            | 266 | 166 |           0 |    0 |
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| PWM       | Pulse-width modulation controller               |  72 |  69 |           0 |    0 |
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| SPI       | Serial peripheral interface                     | 198 | 125 |           0 |    0 |
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| SYSINFO   | System configuration information memory         |  10 |   9 |           0 |    0 |
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| TRNG      | True random number generator                    | 105 |  93 |           0 |    0 |
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| TWI       | Two-wire interface                              |  75 |  44 |           0 |    0 |
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| UART      | Universal asynchronous receiver/transmitter     | 153 | 108 |           0 |    0 |
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| WDT       | Watchdog timer                                  |  59 |  45 |           0 |    0 |
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### NEORV32 Processor - Exemplary FPGA Setups
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Exemplary processor implementation results for different FPGA platforms. The processor setup uses *all provided peripherals* (but not the _CFU_),
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no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
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processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
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to FPGA pins - except for the Wishbone bus and the interrupt signals.
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Results generated for hardware version: `1.4.0.0`
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| Vendor  | FPGA                              | Board            | Toolchain                  | Strategy | CPU Configuration                         | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency      |
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|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|---------------:|
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| Intel   | Cyclone IV `EP4CE22F17C6N`        | Terasic DE0-Nano | Quartus Prime Lite 19.1    | balanced | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 4020 (18%) | 1766  (8%) | 0 (0%) | 231424 (38%) |          - |        - |        100 MHz |
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| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0     | Radiant 2.1 (Synplify Pro) | default  | `rv32icu`  + `Zicsr` + `Zifencei`         | 4249 (80%) | 1617 (31%) | 0 (0%) |            - |   12 (40%) | 4 (100%) |  *c* 20.25 MHz |
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| Xilinx  | Artix-7 `XC7A35TICSG324-1L`       | Arty A7-35T      | Vivado 2019.2              | default  | `rv32imcu` + `Zicsr` + `Zifencei` + `PMP` | 2447 (12%) | 1803  (4%) | 0 (0%) |            - |    8 (16%) |        - |    *c* 100 MHz |
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**_Notes_**
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* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
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* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
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bootloader to store and automatically boot an application program after reset (both tested successfully).
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* The setups with `PMP` implement 2 regions with a minimal granularity of 32kB.
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## Performance
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### CoreMark Benchmark
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
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[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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Results generated for hardware version: `1.3.7.3`
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313
~~~
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**Configuration**
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Hardware:    32kB IMEM, 16kB DMEM, 100MHz clock
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CoreMark:    2000 iterations, MEM_METHOD is MEM_STACK
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Compiler:    RISCV32-GCC 10.1.0
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Peripherals: UART for printing the results
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~~~
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| CPU                    | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
322
|:-----------------------|:---------------:|:------------:|:--------------:|:-------------:|
323
| `rv32i`                |    26 748 bytes |        `-O3` |          28.98 |        0.2898 |
324
| `rv32im`               |    25 580 bytes |        `-O3` |          60.60 |        0.6060 |
325
| `rv32imc`              |    19 636 bytes |        `-O3` |          62.50 |        0.6250 |
326
| `rv32imc` + _FAST_MUL_ |    19 636 bytes |        `-O3` |          76.92 |        0.7692 |
327 2 zero_gravi
 
328 20 zero_gravi
The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
329 2 zero_gravi
 
330 22 zero_gravi
 
331 2 zero_gravi
### Instruction Cycles
332
 
333 11 zero_gravi
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
334 9 zero_gravi
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
335
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
336 2 zero_gravi
CPU extensions.
337
 
338
Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
339
`M` extension use a bit-serial approach and require several cycles for completion.
340
 
341 6 zero_gravi
The following table shows the performance results for successfully running 2000 CoreMark
342 9 zero_gravi
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
343 12 zero_gravi
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
344 19 zero_gravi
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
345 2 zero_gravi
 
346 22 zero_gravi
Results generated for hardware version: `1.3.7.3`
347 2 zero_gravi
 
348 22 zero_gravi
| CPU                    | Required Clock Cycles | Executed Instructions | Average CPI |
349
|:-----------------------|----------------------:|----------------------:|:-----------:|
350
| `rv32i`                |         6 955 817 507 |         1 468 927 290 |        4.73 |
351
| `rv32im`               |         3 376 961 507 |           601 565 750 |        5.61 |
352
| `rv32imc`              |         3 274 832 513 |           601 565 964 |        5.44 |
353
| `rv32imc` + _FAST_MUL_ |         2 689 845 200 |           601 565 890 |        4.47 |
354 2 zero_gravi
 
355 20 zero_gravi
The _FAST_MUL_ configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic).
356 2 zero_gravi
 
357 12 zero_gravi
 
358 22 zero_gravi
 
359 14 zero_gravi
## Top Entities
360 2 zero_gravi
 
361 23 zero_gravi
The top entity of the **NEORV32 Processor** is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
362 2 zero_gravi
Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
363
(except for the TWI signals, which are of type *std_logic*).
364
 
365 23 zero_gravi
The top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd) (from the `rtl/core` folder).
366 16 zero_gravi
All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively.
367 14 zero_gravi
 
368
Use the generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
369 23 zero_gravi
Detailed information regarding the signals and configuration generics can be found in
370
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
371 2 zero_gravi
 
372 23 zero_gravi
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project), can be found
373
in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder.
374 14 zero_gravi
 
375 22 zero_gravi
 
376 23 zero_gravi
### CPU
377
 
378
```vhdl
379
entity neorv32_cpu is
380
  generic (
381
    -- General --
382
    HW_THREAD_ID                 : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
383
    CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
384
    -- RISC-V CPU Extensions --
385
    CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
386
    CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
387
    CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
388
    CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
389
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
390
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;  -- implement instruction stream sync.?
391
    -- Extension Options --
392
    FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
393
    -- Physical Memory Protection (PMP) --
394
    PMP_USE                      : boolean := false; -- implement PMP?
395
    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 8)
396
    PMP_GRANULARITY              : natural := 14;    -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
397
    -- Bus Interface --
398
    BUS_TIMEOUT                  : natural := 15     -- cycles after which a valid bus access will timeout
399
  );
400
  port (
401
    -- global control --
402
    clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
403
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
404
    -- instruction bus interface --
405
    i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
406
    i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
407
    i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
408
    i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
409
    i_bus_we_o     : out std_ulogic; -- write enable
410
    i_bus_re_o     : out std_ulogic; -- read enable
411
    i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
412
    i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
413
    i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
414
    i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
415
    -- data bus interface --
416
    d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
417
    d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
418
    d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
419
    d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
420
    d_bus_we_o     : out std_ulogic; -- write enable
421
    d_bus_re_o     : out std_ulogic; -- read enable
422
    d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
423
    d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
424
    d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
425
    d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
426
    -- system time input from MTIME --
427
    time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
428
    -- interrupts (risc-v compliant) --
429
    msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
430
    mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
431
    mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
432
    -- fast interrupts (custom) --
433
    firq_i         : in  std_ulogic_vector(3 downto 0) := (others => '0')
434
  );
435
end neorv32_cpu;
436
```
437
 
438
 
439 14 zero_gravi
### Processor
440
 
441 2 zero_gravi
```vhdl
442
entity neorv32_top is
443
  generic (
444
    -- General --
445 12 zero_gravi
    CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
446 8 zero_gravi
    BOOTLOADER_USE               : boolean := true;   -- implement processor-internal bootloader?
447 12 zero_gravi
    USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
448 2 zero_gravi
    -- RISC-V CPU Extensions --
449 14 zero_gravi
    CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
450 8 zero_gravi
    CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
451 14 zero_gravi
    CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
452 15 zero_gravi
    CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
453 8 zero_gravi
    CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
454
    CPU_EXTENSION_RISCV_Zifencei : boolean := true;   -- implement instruction stream sync.?
455 19 zero_gravi
    -- Extension Options --
456
    FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
457 15 zero_gravi
    -- Physical Memory Protection (PMP) --
458 19 zero_gravi
    PMP_USE                      : boolean := false; -- implement PMP?
459
    PMP_NUM_REGIONS              : natural := 4;     -- number of regions (max 8)
460 23 zero_gravi
    PMP_GRANULARITY              : natural := 14;    -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64kB
461
    -- Internal Instruction memory --
462 14 zero_gravi
    MEM_INT_IMEM_USE             : boolean := true;   -- implement processor-internal instruction memory
463 8 zero_gravi
    MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
464 14 zero_gravi
    MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
465 23 zero_gravi
    -- Internal Data memory --
466 8 zero_gravi
    MEM_INT_DMEM_USE             : boolean := true;   -- implement processor-internal data memory
467
    MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
468 23 zero_gravi
    -- External memory interface --
469 8 zero_gravi
    MEM_EXT_USE                  : boolean := false;  -- implement external memory bus interface?
470
    MEM_EXT_REG_STAGES           : natural := 2;      -- number of interface register stages (0,1,2)
471 14 zero_gravi
    MEM_EXT_TIMEOUT              : natural := 15;     -- cycles after which a valid bus access will timeout
472 2 zero_gravi
    -- Processor peripherals --
473 8 zero_gravi
    IO_GPIO_USE                  : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
474
    IO_MTIME_USE                 : boolean := true;   -- implement machine system timer (MTIME)?
475
    IO_UART_USE                  : boolean := true;   -- implement universal asynchronous receiver/transmitter (UART)?
476
    IO_SPI_USE                   : boolean := true;   -- implement serial peripheral interface (SPI)?
477
    IO_TWI_USE                   : boolean := true;   -- implement two-wire interface (TWI)?
478
    IO_PWM_USE                   : boolean := true;   -- implement pulse-width modulation unit (PWM)?
479
    IO_WDT_USE                   : boolean := true;   -- implement watch dog timer (WDT)?
480
    IO_TRNG_USE                  : boolean := false;  -- implement true random number generator (TRNG)?
481 23 zero_gravi
    IO_DEVNULL_USE               : boolean := true;   -- implement dummy device (DEVNULL)?
482
    IO_CFU_USE                   : boolean := false   -- implement custom functions unit (CFU)?
483 2 zero_gravi
  );
484
  port (
485
    -- Global control --
486 14 zero_gravi
    clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
487
    rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
488 2 zero_gravi
    -- Wishbone bus interface (available if MEM_EXT_USE = true) --
489 14 zero_gravi
    wb_adr_o   : out std_ulogic_vector(31 downto 0); -- address
490
    wb_dat_i   : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
491
    wb_dat_o   : out std_ulogic_vector(31 downto 0); -- write data
492
    wb_we_o    : out std_ulogic; -- read/write
493
    wb_sel_o   : out std_ulogic_vector(03 downto 0); -- byte enable
494
    wb_stb_o   : out std_ulogic; -- strobe
495
    wb_cyc_o   : out std_ulogic; -- valid cycle
496
    wb_ack_i   : in  std_ulogic := '0'; -- transfer acknowledge
497
    wb_err_i   : in  std_ulogic := '0'; -- transfer error
498 12 zero_gravi
    -- Advanced memory control signals (available if MEM_EXT_USE = true) --
499 14 zero_gravi
    fence_o    : out std_ulogic; -- indicates an executed FENCE operation
500
    fencei_o   : out std_ulogic; -- indicates an executed FENCEI operation
501 2 zero_gravi
    -- GPIO (available if IO_GPIO_USE = true) --
502 22 zero_gravi
    gpio_o     : out std_ulogic_vector(31 downto 0); -- parallel output
503
    gpio_i     : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
504 2 zero_gravi
    -- UART (available if IO_UART_USE = true) --
505 14 zero_gravi
    uart_txd_o : out std_ulogic; -- UART send data
506
    uart_rxd_i : in  std_ulogic := '0'; -- UART receive data
507 2 zero_gravi
    -- SPI (available if IO_SPI_USE = true) --
508 14 zero_gravi
    spi_sck_o  : out std_ulogic; -- SPI serial clock
509
    spi_sdo_o  : out std_ulogic; -- controller data out, peripheral data in
510
    spi_sdi_i  : in  std_ulogic := '0'; -- controller data in, peripheral data out
511
    spi_csn_o  : out std_ulogic_vector(07 downto 0); -- SPI CS
512 2 zero_gravi
    -- TWI (available if IO_TWI_USE = true) --
513 14 zero_gravi
    twi_sda_io : inout std_logic := 'H'; -- twi serial data line
514
    twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
515 2 zero_gravi
    -- PWM (available if IO_PWM_USE = true) --
516 14 zero_gravi
    pwm_o      : out std_ulogic_vector(03 downto 0); -- pwm channels
517
    -- Interrupts --
518
    msw_irq_i  : in  std_ulogic := '0'; -- machine software interrupt
519
    mext_irq_i : in  std_ulogic := '0'  -- machine external interrupt
520 2 zero_gravi
  );
521
end neorv32_top;
522
```
523
 
524 22 zero_gravi
 
525 2 zero_gravi
 
526
## Getting Started
527
 
528
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
529
 
530
[![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
531
 
532
 
533 14 zero_gravi
### Toolchain
534 2 zero_gravi
 
535
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
536
and build the toolchain by yourself, or you can download a prebuilt one and install it.
537
 
538 14 zero_gravi
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
539
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
540 2 zero_gravi
 
541 23 zero_gravi
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
542 14 zero_gravi
Make sure to use the `ilp32` or `ilp32e` ABI.
543 2 zero_gravi
 
544 15 zero_gravi
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
545
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
546 2 zero_gravi
 
547
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
548
 
549
 
550 22 zero_gravi
### Dowload the NEORV32 Project
551 2 zero_gravi
 
552 23 zero_gravi
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
553 12 zero_gravi
 
554 2 zero_gravi
    $ git clone https://github.com/stnolting/neorv32.git
555
 
556 23 zero_gravi
Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
557
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
558 2 zero_gravi
 
559 22 zero_gravi
 
560
### Create a new Hardware Project
561
 
562 23 zero_gravi
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
563
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
564
 
565 11 zero_gravi
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
566
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
567
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
568 2 zero_gravi
 
569 23 zero_gravi
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output sginals are
570
propagated as actual entity signals. Basically, its a FPGA "hello world" example:
571
 
572 2 zero_gravi
```vhdl
573 9 zero_gravi
  entity neorv32_test_setup is
574
    port (
575
      -- Global control --
576
      clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
577
      rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
578
      -- GPIO --
579
      gpio_o     : out std_ulogic_vector(7 downto 0); -- parallel output
580
      -- UART --
581
      uart_txd_o : out std_ulogic; -- UART send data
582
      uart_rxd_i : in  std_ulogic := '0' -- UART receive data
583
    );
584
  end neorv32_test_setup;
585 2 zero_gravi
```
586
 
587
 
588 23 zero_gravi
### Check the Toolchain
589 2 zero_gravi
 
590 11 zero_gravi
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
591 2 zero_gravi
`sw/example/blink_led` and run:
592
 
593
    neorv32/sw/example/blink_led$ make check
594
 
595 23 zero_gravi
 
596
### Compiling an Example Program
597
 
598 9 zero_gravi
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
599
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
600 23 zero_gravi
*executable* `neorv32_exe.bin` in the same folder:
601 2 zero_gravi
 
602 23 zero_gravi
    neorv32/sw/example/blink_led$ make clean_all exe
603 2 zero_gravi
 
604 23 zero_gravi
 
605
### Upload the Executable via the Bootloader
606
 
607
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
608 2 zero_gravi
uses the following default UART configuration:
609
 
610
- 19200 Baud
611
- 8 data bits
612
- 1 stop bit
613
- No parity bits
614
- No transmission / flow control protocol (raw bytes only)
615 23 zero_gravi
- Newline on `\r\n` (carriage return & newline) - also for sent data
616 2 zero_gravi
 
617 23 zero_gravi
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
618 2 zero_gravi
 
619 9 zero_gravi
```
620
  << NEORV32 Bootloader >>
621
 
622
  BLDV: Jul  6 2020
623
  HWV:  1.0.1.0
624
  CLK:  0x0134FD90 Hz
625 13 zero_gravi
  USER: 0x0001CE40
626 9 zero_gravi
  MISA: 0x42801104
627
  CONF: 0x03FF0035
628
  IMEM: 0x00010000 bytes @ 0x00000000
629
  DMEM: 0x00010000 bytes @ 0x80000000
630
 
631
  Autoboot in 8s. Press key to abort.
632
  Aborted.
633
 
634
  Available CMDs:
635
   h: Help
636
   r: Restart
637
   u: Upload
638
   s: Store to flash
639
   l: Load from flash
640
   e: Execute
641
  CMD:> u
642
  Awaiting neorv32_exe.bin... OK
643
  CMD:> e
644
  Booting...
645
 
646
  Blinking LED demo program
647
```
648 2 zero_gravi
 
649 9 zero_gravi
Going further: Take a look at the _Let's Get It Started!_ chapter of the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
650 2 zero_gravi
 
651
 
652
 
653 9 zero_gravi
## Contribute
654 2 zero_gravi
 
655 9 zero_gravi
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
656 23 zero_gravi
to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [drop me a line](mailto:stnolting@gmail.com).
657 2 zero_gravi
 
658 22 zero_gravi
If you'd like to contribute:
659
 
660 23 zero_gravi
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
661
2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
662
3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32`
663
3. Commit your modifications: `git commit -m "Awesome new feature!"`
664
4. Push to the branch: `git push origin awesome_new_feature_branch`
665 22 zero_gravi
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
666
 
667 9 zero_gravi
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
668 2 zero_gravi
 
669
 
670 9 zero_gravi
 
671 11 zero_gravi
## Legal
672 2 zero_gravi
 
673 12 zero_gravi
This project is released under the BSD 3-Clause license. No copyright infringement intended.
674 11 zero_gravi
Other implied or used projects might have different licensing - see their documentation to get more information.
675
 
676
#### Citation
677
 
678 2 zero_gravi
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
679
 
680
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
681
 
682 9 zero_gravi
#### BSD 3-Clause License
683 2 zero_gravi
 
684
Copyright (c) 2020, Stephan Nolting. All rights reserved.
685
 
686
Redistribution and use in source and binary forms, with or without modification, are
687
permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of
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conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
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conditions and the following disclaimer in the documentation and/or other materials
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provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
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endorse or promote products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
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OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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OF THE POSSIBILITY OF SUCH DAMAGE.
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#### Limitation of Liability for External Links
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Our website contains links to the websites of third parties („external links“). As the
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content of these websites is not under our control, we cannot assume any liability for
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such external content. In all cases, the provider of information of the linked websites
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is liable for the content and accuracy of the information provided. At the point in time
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when the links were placed, no infringements of the law were recognisable to us. As soon
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as an infringement of the law becomes known to us, we will immediately remove the
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link in question.
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#### Proprietary  Notice
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
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"Artix" and "Vivado" are trademarks of Xilinx, Inc.
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"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
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"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
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## Acknowledgements
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[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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