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# [The NEORV32 Processor](https://github.com/stnolting/neorv32) (RISC-V)
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[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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## Table of Content
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* [Overview](#Overview)
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* [Project Status](#Status)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Top Entities](#Top-Entities)
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* [**Getting Started**](#Getting-Started)
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* [Contribute](#Contribute)
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* [Legal](#Legal)
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The project consists of two main parts:
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### [NEORV32 CPU](#CPU-Features)
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The CPU implements a `rv32i RISC-V` core with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and
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`PMP` (physical memory protection) extensions. It passes the official [RISC-V compliance tests](https://github.com/stnolting/neorv32_riscv_compliance)
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and is compliant to the *Unprivileged ISA Specification [Version 2.2](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)*
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and a subset of the *Privileged Architecture Specification [Version 1.12-draft](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)*.
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If you do not want to use the NEORV32 Processor setup, you can also use the CPU in
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stand-alone mode and build your own SoC around it.
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### [NEORV32 Processor](#Processor-Features)
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Based on the NEORV32 CPU, the NEORV32 Processor is a full-scale RISC-V microcontroller system (**SoC**)
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that already provides common peripherals like GPIO, serial interfaces, timers, embedded
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memories and an external bus interface for connectivity and custom extension.
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All optional features and modules beyond the base CPU can be enabled and configured via
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[VHDL generics](#Top-Entities).
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The processor is intended as ready-to-use auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller. Its top entity can be directly
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synthesized for any target technology without modifications.
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This project comes with a complete software ecosystem that features core
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libraries for high-level usage of the provided functions and peripherals,
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makefiles, a runtime environment, several example programs to start with - including a free RTOS demo - and
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even a builtin bootloader for easy program upload via UART.
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### [How to get started?](#Getting-Started)
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The processor is intended to work "out of the box". Just synthesize the
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[test setup](#Create-a-new-Hardware-Project), upload it to your FPGA board of choice and start playing
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with the NEORV32. For more information take a look at the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
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The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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### Key Features
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* RISC-V-compliant `rv32i` CPU with optional `C`, `E`, `M`, `U`, `Zicsr`, `Zifencei` and `PMP` (physical memory protection) extensions
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* GCC-based toolchain ([pre-compiled rv32i and rv32e toolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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* Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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* [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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* Highly configurable CPU and processor setup
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* [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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### Design Principles
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* From zero to `main()`: Completely open source and documented.
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* Plain VHDL without technology-specific parts like attributes, macros or primitives.
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* Easy to use – working out of the box.
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* Clean synchronous design, no wacky combinatorial interfaces.
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* Be as small as possible – but with a reasonable size-performance tradeoff.
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* The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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## Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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The processor passes the official `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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| Project component | CI status | Note |
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|:--------------------------------------------------------------------------------|:----------|:---------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32) | [![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32) | [![sw doc](https://img.shields.io/badge/SW%20documentation-gh--pages-blue)](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) | [![Build Status](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) | |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_riscv_compliance) | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) | |
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### To-Do / Wish List
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* Further size and performance optimization
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* Add AXI(-Lite) bridges
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* Synthesis results (+ wrappers?) for more platforms
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* Maybe port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))
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* Use LaTeX for data sheet
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* Implement further CPU extensions:
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* Atomic operations (`A`)
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* Bitmanipulation operations (`B`), when they are "official"
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* Floating-point instructions (`F`)
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* ...
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## Features
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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[![NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Processor Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics.
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* Optional processor-internal data and instruction memories (**DMEM** / **IMEM**)
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* Optional internal **Bootloader** with UART console and automatic SPI flash boot option
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* Optional machine system timer (**MTIME**), RISC-V-compliant
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* Optional universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* Optional 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* Optional two wire serial interface controller (**TWI**), compatible to the I²C standard
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* Optional general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* Optional 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* Optional watchdog timer (**WDT**)
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* Optional PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* Optional GARO-based true random number generator (**TRNG**)
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* Optional custom functions units (**CFU0** and **CFU1**) for tightly-coupled custom co-processors
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* System configuration information memory to check hardware configuration by software (**SYSINFO**)
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### CPU Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_cpu.png)
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The CPU is [compliant](https://github.com/stnolting/neorv32_riscv_compliance) to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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**General**:
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* Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via I/D mux)
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* Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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* No hardware support of unaligned accesses - they will trigger an exception
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* Little-endian byte order
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* All reserved or unimplemented instructions will raise an illegal instruction exception
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* Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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* Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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**RV32I base instruction set** (`I` extension):
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* ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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* Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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* Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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* System instructions: `ECALL` `EBREAK` `FENCE`
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**Compressed instructions** (`C` extension):
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* ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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* Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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* Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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* System instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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* Reduced register file (only the 16 lowest registers)
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**Integer multiplication and division hardware** (`M` extension):
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* Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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* Division instructions: `DIV` `DIVU` `REM` `REMU`
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* By default, the multiplier and divider cores use an iterative bit-serial processing scheme
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* Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
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**Privileged architecture / CSR access** (`Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode)
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* CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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* System instructions: `MRET` `WFI`
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* Counter CSRs: `cycle` `cycleh` `instret` `instreth` `time` `timeh` `mcycle` `mcycleh` `minstret` `minstreth`
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* Machine CSRs: `mstatus` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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* Supported exceptions and interrupts:
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* Misaligned instruction address
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* Instruction access fault
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* Illegal instruction
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* Breakpoint (via `ebreak` instruction)
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* Load address misaligned
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* Load access fault
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* Store address misaligned
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* Store access fault
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* Environment call from M-mode (via `ecall` instruction)
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* Machine timer interrupt `mti` (via processor's MTIME unit)
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* Machine software interrupt `msi` (via external signal)
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* Machine external interrupt `mei` (via external signal)
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* Four fast interrupt requests (custom extension)
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**Privileged architecture / User mode** (`U` extension, requires `Zicsr` extension):
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* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
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**Privileged architecture / FENCE.I** (`Zifencei` extension):
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* System instructions: `FENCE.I`
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**Privileged architecture / Physical memory protection** (`PMP`, requires `Zicsr` extension):
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* Additional machine CSRs: `pmpcfg0` `pmpcfg1` `pmpaddr0` `pmpaddr1` `pmpaddr2` `pmpaddr3` `pmpaddr4` `pmpaddr5` `pmpaddr6` `pmpaddr7`
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### Non-RISC-V-Compliant Issues
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* The physical memory protection (**PMP**) only supports `NAPOT` mode, a minimal granularity of 8 bytes and only up to 8 regions
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### NEORV32-Specific CPU Extensions
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The NEORV32-specific extensions are always enabled and are indicated via the `X` bit in the `misa` CSR.
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* Four *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
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## FPGA Implementation Results
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### NEORV32 CPU
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This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
|
240 |
4 |
zero_gravi |
information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
|
241 |
26 |
zero_gravi |
of the CPU's generics is assumed (for example no PMP). No constraints were used at all.
|
242 |
2 |
zero_gravi |
|
243 |
34 |
zero_gravi |
Results generated for hardware version `1.4.4.8`.
|
244 |
2 |
zero_gravi |
|
245 |
31 |
zero_gravi |
| CPU Configuration | LEs | FFs | Memory bits | DSPs | f_max |
|
246 |
|
|
|:---------------------------------------|:----------:|:--------:|:-----------:|:----:|:--------:|
|
247 |
|
|
| `rv32i` | 983 | 438 | 2048 | 0 | ~120 MHz |
|
248 |
|
|
| `rv32i` + `u` + `Zicsr` + `Zifencei` | 1877 | 802 | 2048 | 0 | ~112 MHz |
|
249 |
|
|
| `rv32im` + `u` + `Zicsr` + `Zifencei` | 2374 | 1048 | 2048 | 0 | ~110 MHz |
|
250 |
|
|
| `rv32imc` + `u` + `Zicsr` + `Zifencei` | 2650 | 1064 | 2048 | 0 | ~110 MHz |
|
251 |
|
|
| `rv32emc` + `u` + `Zicsr` + `Zifencei` | 2680 | 1061 | 1024 | 0 | ~110 MHz |
|
252 |
2 |
zero_gravi |
|
253 |
|
|
|
254 |
23 |
zero_gravi |
### NEORV32 Processor-Internal Peripherals and Memories
|
255 |
|
|
|
256 |
34 |
zero_gravi |
Results generated for hardware version `1.4.4.8`.
|
257 |
11 |
zero_gravi |
|
258 |
25 |
zero_gravi |
| Module | Description | LEs | FFs | Memory bits | DSPs |
|
259 |
31 |
zero_gravi |
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
|
260 |
|
|
| BOOT ROM | Bootloader ROM (default 4kB) | 4 | 1 | 32 768 | 0 |
|
261 |
|
|
| BUSSWITCH | Mux for CPU I & D interfaces | 62 | 8 | 0 | 0 |
|
262 |
34 |
zero_gravi |
| CFU0 | Custom functions unit 0 | - | - | - | - |
|
263 |
|
|
| CFU1 | Custom functions unit 1 | - | - | - | - |
|
264 |
26 |
zero_gravi |
| DMEM | Processor-internal data memory (default 8kB) | 13 | 2 | 65 536 | 0 |
|
265 |
31 |
zero_gravi |
| GPIO | General purpose input/output ports | 66 | 65 | 0 | 0 |
|
266 |
|
|
| IMEM | Processor-internal instruction memory (default 16kb) | 7 | 2 | 131 072 | 0 |
|
267 |
|
|
| MTIME | Machine system timer | 268 | 166 | 0 | 0 |
|
268 |
25 |
zero_gravi |
| PWM | Pulse-width modulation controller | 72 | 69 | 0 | 0 |
|
269 |
31 |
zero_gravi |
| SPI | Serial peripheral interface | 184 | 125 | 0 | 0 |
|
270 |
|
|
| SYSINFO | System configuration information memory | 11 | 9 | 0 | 0 |
|
271 |
|
|
| TRNG | True random number generator | 132 | 105 | 0 | 0 |
|
272 |
|
|
| TWI | Two-wire interface | 74 | 44 | 0 | 0 |
|
273 |
26 |
zero_gravi |
| UART | Universal asynchronous receiver/transmitter | 175 | 132 | 0 | 0 |
|
274 |
31 |
zero_gravi |
| WDT | Watchdog timer | 58 | 45 | 0 | 0 |
|
275 |
|
|
| WISHBONE | External memory interface (`MEM_EXT_REG_STAGES` = 2) | 106 | 104 | 0 | 0 |
|
276 |
2 |
zero_gravi |
|
277 |
|
|
|
278 |
23 |
zero_gravi |
### NEORV32 Processor - Exemplary FPGA Setups
|
279 |
6 |
zero_gravi |
|
280 |
34 |
zero_gravi |
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFUs_ and no _TRNG_),
|
281 |
23 |
zero_gravi |
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
|
282 |
11 |
zero_gravi |
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
|
283 |
12 |
zero_gravi |
to FPGA pins - except for the Wishbone bus and the interrupt signals.
|
284 |
6 |
zero_gravi |
|
285 |
34 |
zero_gravi |
Results generated for hardware version `1.4.4.8`.
|
286 |
6 |
zero_gravi |
|
287 |
26 |
zero_gravi |
| Vendor | FPGA | Board | Toolchain | Strategy | CPU Configuration | LUT / LE | FF / REG | DSP | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|
288 |
|
|
|:--------|:----------------------------------|:-----------------|:---------------------------|:-------- |:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
|
289 |
31 |
zero_gravi |
| Intel | Cyclone IV `EP4CE22F17C6N` | Terasic DE0-Nano | Quartus Prime Lite 19.1 | balanced | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 4008 (18%) | 1849 (9%) | 0 (0%) | 231424 (38%) | - | - | 105 MHz |
|
290 |
|
|
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0 | Radiant 2.1 (Synplify Pro) | default | `rv32ic` + `u` + `Zicsr` + `Zifencei` | 4296 (81%) | 1611 (30%) | 0 (0%) | - | 12 (40%) | 4 (100%) | *c* 22.5 MHz |
|
291 |
|
|
| Xilinx | Artix-7 `XC7A35TICSG324-1L` | Arty A7-35T | Vivado 2019.2 | default | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2390 (11%) | 1888 (5%) | 0 (0%) | - | 8 (16%) | - | *c* 100 MHz |
|
292 |
2 |
zero_gravi |
|
293 |
23 |
zero_gravi |
**_Notes_**
|
294 |
20 |
zero_gravi |
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
|
295 |
12 |
zero_gravi |
The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
|
296 |
|
|
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
|
297 |
11 |
zero_gravi |
* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
|
298 |
|
|
bootloader to store and automatically boot an application program after reset (both tested successfully).
|
299 |
22 |
zero_gravi |
* The setups with `PMP` implement 2 regions with a minimal granularity of 32kB.
|
300 |
2 |
zero_gravi |
|
301 |
22 |
zero_gravi |
|
302 |
|
|
|
303 |
2 |
zero_gravi |
## Performance
|
304 |
|
|
|
305 |
|
|
### CoreMark Benchmark
|
306 |
|
|
|
307 |
|
|
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
|
308 |
|
|
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
|
309 |
|
|
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
|
310 |
|
|
|
311 |
34 |
zero_gravi |
Results generated for hardware version `1.4.5.4`.
|
312 |
2 |
zero_gravi |
|
313 |
|
|
~~~
|
314 |
|
|
**Configuration**
|
315 |
12 |
zero_gravi |
Hardware: 32kB IMEM, 16kB DMEM, 100MHz clock
|
316 |
|
|
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
|
317 |
32 |
zero_gravi |
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
|
318 |
|
|
Flags: default, see makefile
|
319 |
12 |
zero_gravi |
Peripherals: UART for printing the results
|
320 |
2 |
zero_gravi |
~~~
|
321 |
|
|
|
322 |
34 |
zero_gravi |
| CPU | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
|
323 |
|
|
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
|
324 |
|
|
| `rv32i` | 26 940 bytes | `-O3` | 33.89 | **0.3389** |
|
325 |
|
|
| `rv32im` | 25 772 bytes | `-O3` | 64.51 | **0.6451** |
|
326 |
|
|
| `rv32imc` | 20 524 bytes | `-O3` | 64.51 | **0.6451** |
|
327 |
|
|
| `rv32imc` + `FAST_MUL_EN` | 20 524 bytes | `-O3` | 80.00 | **0.8000** |
|
328 |
|
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 20 524 bytes | `-O3` | 83.33 | **0.8333** |
|
329 |
2 |
zero_gravi |
|
330 |
34 |
zero_gravi |
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
331 |
|
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
332 |
2 |
zero_gravi |
|
333 |
31 |
zero_gravi |
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
334 |
22 |
zero_gravi |
|
335 |
34 |
zero_gravi |
|
336 |
2 |
zero_gravi |
### Instruction Cycles
|
337 |
|
|
|
338 |
11 |
zero_gravi |
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
|
339 |
9 |
zero_gravi |
each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
|
340 |
|
|
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
|
341 |
2 |
zero_gravi |
CPU extensions.
|
342 |
|
|
|
343 |
34 |
zero_gravi |
Please note that by default the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
|
344 |
2 |
zero_gravi |
`M` extension use a bit-serial approach and require several cycles for completion.
|
345 |
|
|
|
346 |
6 |
zero_gravi |
The following table shows the performance results for successfully running 2000 CoreMark
|
347 |
9 |
zero_gravi |
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
|
348 |
12 |
zero_gravi |
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
|
349 |
19 |
zero_gravi |
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
|
350 |
2 |
zero_gravi |
|
351 |
34 |
zero_gravi |
Results generated for hardware version `1.4.5.4`.
|
352 |
2 |
zero_gravi |
|
353 |
34 |
zero_gravi |
| CPU | Required Clock Cycles | Executed Instructions | Average CPI |
|
354 |
|
|
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
|
355 |
|
|
| `rv32i` | 5 945 938 586 | 1 469 587 406 | **4.05** |
|
356 |
|
|
| `rv32im` | 3 110 282 586 | 602 225 760 | **5.16** |
|
357 |
|
|
| `rv32imc` | 3 172 969 968 | 615 388 890 | **5.16** |
|
358 |
|
|
| `rv32imc` + `FAST_MUL_EN` | 2 590 417 968 | 615 388 890 | **4.21** |
|
359 |
|
|
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` | 2 456 318 408 | 615 388 890 | **3.99** |
|
360 |
2 |
zero_gravi |
|
361 |
|
|
|
362 |
34 |
zero_gravi |
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
|
363 |
|
|
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
|
364 |
|
|
|
365 |
31 |
zero_gravi |
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
|
366 |
12 |
zero_gravi |
|
367 |
22 |
zero_gravi |
|
368 |
31 |
zero_gravi |
|
369 |
14 |
zero_gravi |
## Top Entities
|
370 |
2 |
zero_gravi |
|
371 |
34 |
zero_gravi |
The top entity of the **NEORV32 Processor** (SoC) is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd)
|
372 |
|
|
and the top entity of the **NEORV32 CPU** is [**neorv32_cpu.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd). Both
|
373 |
|
|
top entities are located in `rtl/core`.
|
374 |
2 |
zero_gravi |
|
375 |
34 |
zero_gravi |
All signals of the top entities are of type *std_ulogic* or *std_ulogic_vector*, respectively
|
376 |
|
|
(except for the processor's TWI signals, which are of type *std_logic*). Leave all unused output ports unconnected (`open`) and tie all unused
|
377 |
|
|
input ports to zero (`'0'` or `(others => '0')`, respectively).
|
378 |
14 |
zero_gravi |
|
379 |
30 |
zero_gravi |
Alternative top entities, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
|
380 |
|
|
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
|
381 |
14 |
zero_gravi |
|
382 |
34 |
zero_gravi |
Use the top's generics to configure the processor/CPU according to your needs. Each generic is initilized with the default configuration.
|
383 |
|
|
Detailed information regarding the interface signals and configuration generics can be found in
|
384 |
|
|
the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
385 |
22 |
zero_gravi |
|
386 |
26 |
zero_gravi |
### NEORV32 CPU
|
387 |
23 |
zero_gravi |
|
388 |
|
|
```vhdl
|
389 |
|
|
entity neorv32_cpu is
|
390 |
|
|
generic (
|
391 |
|
|
-- General --
|
392 |
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
|
393 |
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
|
394 |
|
|
-- RISC-V CPU Extensions --
|
395 |
|
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
396 |
|
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
397 |
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
398 |
|
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
399 |
|
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
400 |
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
401 |
|
|
-- Extension Options --
|
402 |
|
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
403 |
34 |
zero_gravi |
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
404 |
23 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
405 |
|
|
PMP_USE : boolean := false; -- implement PMP?
|
406 |
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
407 |
30 |
zero_gravi |
PMP_GRANULARITY : natural := 14 -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
408 |
23 |
zero_gravi |
);
|
409 |
|
|
port (
|
410 |
|
|
-- global control --
|
411 |
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
412 |
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
413 |
|
|
-- instruction bus interface --
|
414 |
|
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
415 |
|
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
416 |
|
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
417 |
|
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
418 |
|
|
i_bus_we_o : out std_ulogic; -- write enable
|
419 |
|
|
i_bus_re_o : out std_ulogic; -- read enable
|
420 |
|
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
421 |
|
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
422 |
|
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
423 |
|
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
424 |
|
|
-- data bus interface --
|
425 |
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
426 |
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
427 |
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
428 |
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
429 |
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
430 |
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
431 |
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
432 |
|
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
433 |
|
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
434 |
|
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
435 |
|
|
-- system time input from MTIME --
|
436 |
|
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
437 |
|
|
-- interrupts (risc-v compliant) --
|
438 |
|
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
439 |
|
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
440 |
|
|
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
|
441 |
|
|
-- fast interrupts (custom) --
|
442 |
|
|
firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
|
443 |
|
|
);
|
444 |
|
|
end neorv32_cpu;
|
445 |
|
|
```
|
446 |
|
|
|
447 |
|
|
|
448 |
26 |
zero_gravi |
### NEORV32 Processor
|
449 |
14 |
zero_gravi |
|
450 |
2 |
zero_gravi |
```vhdl
|
451 |
|
|
entity neorv32_top is
|
452 |
|
|
generic (
|
453 |
|
|
-- General --
|
454 |
12 |
zero_gravi |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
455 |
8 |
zero_gravi |
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
456 |
12 |
zero_gravi |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
457 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
458 |
14 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
459 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
460 |
14 |
zero_gravi |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
461 |
15 |
zero_gravi |
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
462 |
8 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
463 |
|
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
464 |
19 |
zero_gravi |
-- Extension Options --
|
465 |
34 |
zero_gravi |
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
466 |
|
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
467 |
15 |
zero_gravi |
-- Physical Memory Protection (PMP) --
|
468 |
34 |
zero_gravi |
PMP_USE : boolean := false; -- implement PMP?
|
469 |
|
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
|
470 |
|
|
PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64kB
|
471 |
23 |
zero_gravi |
-- Internal Instruction memory --
|
472 |
14 |
zero_gravi |
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
473 |
8 |
zero_gravi |
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
474 |
14 |
zero_gravi |
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
475 |
23 |
zero_gravi |
-- Internal Data memory --
|
476 |
8 |
zero_gravi |
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
477 |
|
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
478 |
23 |
zero_gravi |
-- External memory interface --
|
479 |
8 |
zero_gravi |
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
480 |
|
|
MEM_EXT_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
481 |
2 |
zero_gravi |
-- Processor peripherals --
|
482 |
8 |
zero_gravi |
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
483 |
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
484 |
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
485 |
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
486 |
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
487 |
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
488 |
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
489 |
|
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
490 |
34 |
zero_gravi |
IO_CFU0_USE : boolean := false; -- implement custom functions unit 0 (CFU0)?
|
491 |
|
|
IO_CFU1_USE : boolean := false -- implement custom functions unit 1 (CFU1)?
|
492 |
2 |
zero_gravi |
);
|
493 |
|
|
port (
|
494 |
|
|
-- Global control --
|
495 |
34 |
zero_gravi |
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
496 |
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
497 |
2 |
zero_gravi |
-- Wishbone bus interface (available if MEM_EXT_USE = true) --
|
498 |
34 |
zero_gravi |
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
499 |
|
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
500 |
|
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
501 |
|
|
wb_we_o : out std_ulogic; -- read/write
|
502 |
|
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
503 |
|
|
wb_stb_o : out std_ulogic; -- strobe
|
504 |
|
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
505 |
|
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
506 |
|
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
507 |
12 |
zero_gravi |
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
508 |
34 |
zero_gravi |
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
509 |
|
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
510 |
2 |
zero_gravi |
-- GPIO (available if IO_GPIO_USE = true) --
|
511 |
34 |
zero_gravi |
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
512 |
|
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
513 |
2 |
zero_gravi |
-- UART (available if IO_UART_USE = true) --
|
514 |
34 |
zero_gravi |
uart_txd_o : out std_ulogic; -- UART send data
|
515 |
|
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
516 |
2 |
zero_gravi |
-- SPI (available if IO_SPI_USE = true) --
|
517 |
34 |
zero_gravi |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
518 |
|
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
519 |
|
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
520 |
|
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
521 |
2 |
zero_gravi |
-- TWI (available if IO_TWI_USE = true) --
|
522 |
34 |
zero_gravi |
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
523 |
|
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
524 |
2 |
zero_gravi |
-- PWM (available if IO_PWM_USE = true) --
|
525 |
34 |
zero_gravi |
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
526 |
14 |
zero_gravi |
-- Interrupts --
|
527 |
34 |
zero_gravi |
mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_USE = false
|
528 |
|
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
529 |
|
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
530 |
2 |
zero_gravi |
);
|
531 |
|
|
end neorv32_top;
|
532 |
|
|
```
|
533 |
|
|
|
534 |
22 |
zero_gravi |
|
535 |
2 |
zero_gravi |
|
536 |
|
|
## Getting Started
|
537 |
|
|
|
538 |
|
|
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
|
539 |
|
|
|
540 |
31 |
zero_gravi |
[![NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
|
541 |
2 |
zero_gravi |
|
542 |
|
|
|
543 |
14 |
zero_gravi |
### Toolchain
|
544 |
2 |
zero_gravi |
|
545 |
|
|
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
|
546 |
|
|
and build the toolchain by yourself, or you can download a prebuilt one and install it.
|
547 |
|
|
|
548 |
14 |
zero_gravi |
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
|
549 |
|
|
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
|
550 |
2 |
zero_gravi |
|
551 |
23 |
zero_gravi |
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
|
552 |
14 |
zero_gravi |
Make sure to use the `ilp32` or `ilp32e` ABI.
|
553 |
2 |
zero_gravi |
|
554 |
15 |
zero_gravi |
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
|
555 |
|
|
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
|
556 |
2 |
zero_gravi |
|
557 |
|
|
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
|
558 |
|
|
|
559 |
|
|
|
560 |
22 |
zero_gravi |
### Dowload the NEORV32 Project
|
561 |
2 |
zero_gravi |
|
562 |
23 |
zero_gravi |
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
|
563 |
12 |
zero_gravi |
|
564 |
2 |
zero_gravi |
$ git clone https://github.com/stnolting/neorv32.git
|
565 |
|
|
|
566 |
23 |
zero_gravi |
Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
|
567 |
|
|
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
|
568 |
2 |
zero_gravi |
|
569 |
22 |
zero_gravi |
|
570 |
|
|
### Create a new Hardware Project
|
571 |
|
|
|
572 |
23 |
zero_gravi |
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
|
573 |
|
|
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
|
574 |
|
|
|
575 |
11 |
zero_gravi |
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in your own project or you
|
576 |
|
|
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) (from the project's
|
577 |
|
|
[`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) folder) as top entity.
|
578 |
2 |
zero_gravi |
|
579 |
33 |
zero_gravi |
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are
|
580 |
25 |
zero_gravi |
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
|
581 |
23 |
zero_gravi |
|
582 |
2 |
zero_gravi |
```vhdl
|
583 |
9 |
zero_gravi |
entity neorv32_test_setup is
|
584 |
|
|
port (
|
585 |
|
|
-- Global control --
|
586 |
|
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
587 |
|
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
588 |
|
|
-- GPIO --
|
589 |
|
|
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
|
590 |
|
|
-- UART --
|
591 |
|
|
uart_txd_o : out std_ulogic; -- UART send data
|
592 |
|
|
uart_rxd_i : in std_ulogic := '0' -- UART receive data
|
593 |
|
|
);
|
594 |
|
|
end neorv32_test_setup;
|
595 |
2 |
zero_gravi |
```
|
596 |
|
|
|
597 |
|
|
|
598 |
23 |
zero_gravi |
### Check the Toolchain
|
599 |
2 |
zero_gravi |
|
600 |
11 |
zero_gravi |
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
|
601 |
2 |
zero_gravi |
`sw/example/blink_led` and run:
|
602 |
|
|
|
603 |
|
|
neorv32/sw/example/blink_led$ make check
|
604 |
|
|
|
605 |
23 |
zero_gravi |
|
606 |
|
|
### Compiling an Example Program
|
607 |
|
|
|
608 |
9 |
zero_gravi |
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
|
609 |
|
|
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
|
610 |
23 |
zero_gravi |
*executable* `neorv32_exe.bin` in the same folder:
|
611 |
2 |
zero_gravi |
|
612 |
23 |
zero_gravi |
neorv32/sw/example/blink_led$ make clean_all exe
|
613 |
2 |
zero_gravi |
|
614 |
23 |
zero_gravi |
|
615 |
|
|
### Upload the Executable via the Bootloader
|
616 |
|
|
|
617 |
34 |
zero_gravi |
You can upload a generated executable directly from the command line using the makefile's `upload` target. Replace `/dev/ttyUSB0` with
|
618 |
|
|
the according serial port.
|
619 |
|
|
|
620 |
|
|
sw/exeample/blink_example$ make COM_PORT=/dev/ttyUSB0` upload
|
621 |
|
|
|
622 |
|
|
A more "secure" way is to use a dedicated terminal program. This allows to directly interact with the bootloader console.
|
623 |
23 |
zero_gravi |
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
|
624 |
2 |
zero_gravi |
uses the following default UART configuration:
|
625 |
|
|
|
626 |
32 |
zero_gravi |
* 19200 Baud
|
627 |
|
|
* 8 data bits
|
628 |
|
|
* 1 stop bit
|
629 |
|
|
* No parity bits
|
630 |
|
|
* No transmission / flow control protocol (raw bytes only)
|
631 |
|
|
* Newline on `\r\n` (carriage return & newline) - also for sent data
|
632 |
2 |
zero_gravi |
|
633 |
23 |
zero_gravi |
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
|
634 |
2 |
zero_gravi |
|
635 |
9 |
zero_gravi |
```
|
636 |
|
|
<< NEORV32 Bootloader >>
|
637 |
|
|
|
638 |
|
|
BLDV: Jul 6 2020
|
639 |
|
|
HWV: 1.0.1.0
|
640 |
|
|
CLK: 0x0134FD90 Hz
|
641 |
13 |
zero_gravi |
USER: 0x0001CE40
|
642 |
9 |
zero_gravi |
MISA: 0x42801104
|
643 |
27 |
zero_gravi |
PROC: 0x03FF0035
|
644 |
9 |
zero_gravi |
IMEM: 0x00010000 bytes @ 0x00000000
|
645 |
|
|
DMEM: 0x00010000 bytes @ 0x80000000
|
646 |
|
|
|
647 |
|
|
Autoboot in 8s. Press key to abort.
|
648 |
|
|
Aborted.
|
649 |
|
|
|
650 |
|
|
Available CMDs:
|
651 |
|
|
h: Help
|
652 |
|
|
r: Restart
|
653 |
|
|
u: Upload
|
654 |
|
|
s: Store to flash
|
655 |
|
|
l: Load from flash
|
656 |
|
|
e: Execute
|
657 |
|
|
CMD:> u
|
658 |
|
|
Awaiting neorv32_exe.bin... OK
|
659 |
|
|
CMD:> e
|
660 |
|
|
Booting...
|
661 |
|
|
|
662 |
|
|
Blinking LED demo program
|
663 |
|
|
```
|
664 |
2 |
zero_gravi |
|
665 |
31 |
zero_gravi |
Going further: Take a look at the _Let's Get It Started!_ chapter of the [![NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
|
666 |
2 |
zero_gravi |
|
667 |
|
|
|
668 |
|
|
|
669 |
9 |
zero_gravi |
## Contribute
|
670 |
2 |
zero_gravi |
|
671 |
9 |
zero_gravi |
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
|
672 |
23 |
zero_gravi |
to [open a new issue](https://github.com/stnolting/neorv32/issues) or directly [drop me a line](mailto:stnolting@gmail.com).
|
673 |
2 |
zero_gravi |
|
674 |
22 |
zero_gravi |
If you'd like to contribute:
|
675 |
|
|
|
676 |
23 |
zero_gravi |
1. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
|
677 |
|
|
2. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
|
678 |
|
|
3. Create a new remote for the upstream repo: `git remote add https://github.com/stnolting/neorv32`
|
679 |
|
|
3. Commit your modifications: `git commit -m "Awesome new feature!"`
|
680 |
|
|
4. Push to the branch: `git push origin awesome_new_feature_branch`
|
681 |
22 |
zero_gravi |
5. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
|
682 |
|
|
|
683 |
9 |
zero_gravi |
Please also check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md).
|
684 |
2 |
zero_gravi |
|
685 |
|
|
|
686 |
9 |
zero_gravi |
|
687 |
11 |
zero_gravi |
## Legal
|
688 |
2 |
zero_gravi |
|
689 |
12 |
zero_gravi |
This project is released under the BSD 3-Clause license. No copyright infringement intended.
|
690 |
11 |
zero_gravi |
Other implied or used projects might have different licensing - see their documentation to get more information.
|
691 |
|
|
|
692 |
|
|
#### Citation
|
693 |
|
|
|
694 |
34 |
zero_gravi |
If you are using the NEORV32 or some parts of the project in some kind of publication, please cite it as follows:
|
695 |
2 |
zero_gravi |
|
696 |
34 |
zero_gravi |
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
|
697 |
2 |
zero_gravi |
|
698 |
9 |
zero_gravi |
#### BSD 3-Clause License
|
699 |
2 |
zero_gravi |
|
700 |
|
|
Copyright (c) 2020, Stephan Nolting. All rights reserved.
|
701 |
|
|
|
702 |
|
|
Redistribution and use in source and binary forms, with or without modification, are
|
703 |
|
|
permitted provided that the following conditions are met:
|
704 |
|
|
|
705 |
|
|
1. Redistributions of source code must retain the above copyright notice, this list of
|
706 |
|
|
conditions and the following disclaimer.
|
707 |
|
|
2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
708 |
|
|
conditions and the following disclaimer in the documentation and/or other materials
|
709 |
|
|
provided with the distribution.
|
710 |
|
|
3. Neither the name of the copyright holder nor the names of its contributors may be used to
|
711 |
|
|
endorse or promote products derived from this software without specific prior written
|
712 |
|
|
permission.
|
713 |
|
|
|
714 |
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
|
715 |
|
|
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
716 |
|
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
717 |
|
|
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
718 |
|
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
719 |
|
|
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
720 |
|
|
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
721 |
|
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
|
722 |
|
|
OF THE POSSIBILITY OF SUCH DAMAGE.
|
723 |
|
|
|
724 |
|
|
|
725 |
9 |
zero_gravi |
#### Limitation of Liability for External Links
|
726 |
|
|
|
727 |
|
|
Our website contains links to the websites of third parties („external links“). As the
|
728 |
|
|
content of these websites is not under our control, we cannot assume any liability for
|
729 |
|
|
such external content. In all cases, the provider of information of the linked websites
|
730 |
|
|
is liable for the content and accuracy of the information provided. At the point in time
|
731 |
|
|
when the links were placed, no infringements of the law were recognisable to us. As soon
|
732 |
|
|
as an infringement of the law becomes known to us, we will immediately remove the
|
733 |
|
|
link in question.
|
734 |
|
|
|
735 |
|
|
|
736 |
11 |
zero_gravi |
#### Proprietary Notice
|
737 |
9 |
zero_gravi |
|
738 |
2 |
zero_gravi |
"Artix" and "Vivado" are trademarks of Xilinx Inc.
|
739 |
|
|
|
740 |
11 |
zero_gravi |
"Cyclone", "Quartus Prime", "Quartus Prime Lite" and "Avalon Bus" are trademarks of Intel Corporation.
|
741 |
2 |
zero_gravi |
|
742 |
11 |
zero_gravi |
"Artix" and "Vivado" are trademarks of Xilinx, Inc.
|
743 |
|
|
|
744 |
2 |
zero_gravi |
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
|
745 |
|
|
|
746 |
13 |
zero_gravi |
"AXI" and "AXI-Lite" are trademarks of Arm Holdings plc.
|
747 |
2 |
zero_gravi |
|
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## Acknowledgements
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[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)
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Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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--------
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This repository was created on June 23th, 2020.
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Made with :coffee: in Hannover, Germany.
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