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[![NEORV32](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_logo.png)](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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[![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22)
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[![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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* [Overview](#Overview)
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* [Status](#Status)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Top Entities](#Top-Entities)
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* [**Getting Started**](#Getting-Started)
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* [Contribute/Feedback/Questions](#ContributeFeedbackQuestions)
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* [Legal](#Legal)
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## Overview
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The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based
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on the RISC-V-compliant NEORV32 CPU. The processor is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom microcontroller.
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:label: The project’s change log is available in the [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) file in the root directory of this repository.
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To see the changes between releases visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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:books: The doxygen-based documentation of the software framework is available online at [GitHub-pages](https://stnolting.github.io/neorv32/files.html).
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:page_facing_up: For more detailed information take a look at the [NEORV32 data sheet (pdf)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Key Features
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* RISC-V 32-bit `rv32i` [**NEORV32 CPU**](#NEORV32-CPU-Features), compliant to
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  * Subset of the *Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-privileged.pdf)
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  * Subset of the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/riscv-spec.pdf)
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  * Passes the [offcial RISC-V compliance tests](#Status)
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* Configurable RISC-V-compliant CPU extensions
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  * [`A`](#Atomic-memory-access-a-extension) - atomic memory access instructions (optional)
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  * [`B`](#Bit-manipulation-instructions-B-extension) - Bit manipulation instructions (optional)
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  * [`C`](#Compressed-instructions-C-extension) - compressed instructions (16-bit) (optional)
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  * [`E`](#Embedded-CPU-version-E-extension) - embedded CPU (reduced register file size) (optional)
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  * [`I`](#Integer-base-instruction-set-I-extension) - base integer instruction set (always enabled)
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  * [`M`](#Integer-multiplication-and-division-hardware-M-extension) - integer multiplication and division hardware (optional)
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  * [`U`](#Privileged-architecture---User-mode-U-extension) - less-privileged *user mode* (optional)
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  * [`X`](#NEORV32-specific-CPU-extensions-X-extension) - NEORV32-specific extensions (always enabled)
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  * [`Zicsr`](#Privileged-architecture---CSR-access-Zicsr-extension) - control and status register access instructions (+ exception/irq system) (optional)
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  * [`Zifencei`](#Privileged-architecture---Instruction-stream-synchronization-Zifencei-extension) - instruction stream synchronization (optional)
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  * [`PMP`](#Privileged-architecture---Physical-memory-protection-PMP) - physical memory protection (optional)
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  * [`HPM`](#Privileged-architecture---Hardware-performance-monitors-HPM-extension) - hardware performance monitors (optional)
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* Full-scale RISC-V microcontroller system / **SoC** [**NEORV32 Processor**](#NEORV32-Processor-Features) with optional submodules
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  * optional embedded memories (instructions/data/bootloader, RAM/ROM) and caches
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  * timers (watch dog, RISC-V-compliant machine timer)
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  * serial interfaces (SPI, TWI, UART)
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  * general purpose IO and PWM channels
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  * external bus interface (Wishbone / [AXI4](#AXI4-Connectivity))
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  * subsystem for custom co-processors
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  * [more ...](#NEORV32-Processor-Features)
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* Software framework
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  * core libraries for high-level usage of the provided functions and peripherals
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  * application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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  * GCC-based toolchain ([pre-compiled toolchains available](https://github.com/stnolting/riscv-gcc-prebuilt))
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  * bootloader with UART interface console
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  * runtime environment
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  * several example programs
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  * [doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation: available on [GitHub pages](https://stnolting.github.io/neorv32/files.html)
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  * [FreeRTOS port](https://github.com/stnolting/neorv32/blob/master/sw/example/demo_freeRTOS) available
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* [**Full-blown data sheet**](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf)
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* Completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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* Fully synchronous design, no latches, no gated clocks
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* Small hardware footprint and high operating frequency
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### Design Principles
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 * From zero to *hello_world*: Completely open source and documented.
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 * Plain VHDL without technology-specific parts like attributes, macros or primitives.
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 * Easy to use – working out of the box.
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 * Clean synchronous design, no wacky combinatorial interfaces.
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 * Be as small as possible – but with a reasonable size-performance tradeoff.
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 * Be as RISC-V-compliant as possible.
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 * The processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 20+ MHz.
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88
 
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### Status
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The processor is [synthesizable](#FPGA-Implementation-Results) (tested on *real hardware* using Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/Synplify Pro) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the [CoreMark benchmark](#CoreMark-Benchmark).
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**RISC-V Compliance**: The processor passes the official `rv32_m/C`, `rv32_m/I`, `rv32_m/M`, `rv32_m/privilege` and `rv32_m/Zifencei`
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[RISC-V compliance](https://github.com/riscv/riscv-compliance) tests. More information regarding the NEORV32 port of the compliance framework can be found in
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[`riscv-compliance/README.md`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md).
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| Project component | CI status |
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|:----------------- |:----------|
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| [NEORV32 processor](https://github.com/stnolting/neorv32)                                             | [![Processor Check](https://github.com/stnolting/neorv32/workflows/Processor%20Check/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22Processor+Check%22) |
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| [SW Framework Documentation (online)](https://stnolting.github.io/neorv32/files.html)                 | [![Doc@GitHub-pages](https://github.com/stnolting/neorv32/workflows/Deploy%20SW%20Framework%20Documentation%20to%20GitHub-Pages/badge.svg)](https://stnolting.github.io/neorv32/files.html) |
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| [Pre-built toolchains](https://github.com/stnolting/riscv-gcc-prebuilt)                               | [![Test Toolchains](https://github.com/stnolting/riscv-gcc-prebuilt/workflows/Test%20Toolchains/badge.svg)](https://github.com/stnolting/riscv-gcc-prebuilt/actions?query=workflow%3A%22Test+Toolchains%22) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md) | [![RISC-V Compliance](https://github.com/stnolting/neorv32/workflows/RISC-V%20Compliance/badge.svg)](https://github.com/stnolting/neorv32/actions?query=workflow%3A%22RISC-V+Compliance%22) |
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### To-Do / Wish List / Help Wanted
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* Use LaTeX for data sheet
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* Further size and performance optimization
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* Further expand associativity configuration of instruction cache (4x/8x set-associativity)?
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* Add data cache?
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* Burst mode for the external memory/bus interface?
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* RISC-V `F` (using [`Zfinx`](https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc)?) CPU extension (single-precision floating point)
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* Add template (HW module + intrinsics skeleton) for custom instructions?
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* Implement further RISC-V (or custom) CPU extensions?
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* More support for FreeRTOS (like *all* traps)?
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* Port additional RTOSs (like [Zephyr](https://github.com/zephyrproject-rtos/zephyr) or [RIOT](https://www.riot-os.org))?
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* Add debugger ([RISC-V debug spec](https://github.com/riscv/riscv-debug-spec))?
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* Add encryption/decryption/hash accelerator (maybe [XTEA](https://en.wikipedia.org/wiki/XTEA))?
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* ...
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* [Ideas?](#ContributeFeedbackQuestions)
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## Features
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The full-blown data sheet of the NEORV32 Processor and CPU is available as pdf file:
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[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### NEORV32 Processor Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_processor.png)
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The NEORV32 Processor provides a full-scale microcontroller-like SoC based on the NEORV32 CPU. The setup
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is highly customizable via the processor's top generics and already provides the following *optional* modules:
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* processor-internal data and instruction memories (**DMEM** / **IMEM**) & cache (**iCACHE**)
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* bootloader (**BOOTLDROM**) with UART console and automatic application boot from SPI flash option
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* machine system timer (**MTIME**), RISC-V-compliant
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* watchdog timer (**WDT**)
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* universal asynchronous receiver and transmitter (**UART**) with simulation output option via text.io
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* 8/16/24/32-bit serial peripheral interface controller (**SPI**) with 8 dedicated chip select lines
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* two wire serial interface controller (**TWI**), with optional clock-stretching, compatible to the I²C standard
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* general purpose parallel IO port (**GPIO**), 32xOut & 32xIn, with pin-change interrupt
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* 32-bit external bus interface, Wishbone b4 compliant (**WISHBONE**), *standard* or *pipelined* handshake/transactions mode
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* wrapper for **AXI4-Lite Master Interface** (see [AXI Connectivity](#AXI4-Connectivity))
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* PWM controller with 4 channels and 8-bit duty cycle resolution (**PWM**)
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* ring-oscillator-based true random number generator (**TRNG**)
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* custom functions subsystem (**CFS**) for tightly-coupled custom co-processor extensions
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* system configuration information memory to check hardware configuration by software (**SYSINFO**, mandatory - not *optional*)
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### NEORV32 CPU Features
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The NEORV32 CPU is **compliant** to the
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[official RISC-V specifications (2.2)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications (1.12-draft)](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf)
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tested via the [official RISC-V Compliance Test Framework](https://github.com/riscv/riscv-compliance)
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(see [`riscv-compliance/README`](https://github.com/stnolting/neorv32/blob/master/riscv-compliance/README.md)).
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More information regarding the CPU including a detailed list of the instruction set and the available CSRs can be found in
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the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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#### General Features
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  * Modified Harvard architecture (separate CPU interfaces for data and instructions; NEORV32 processor: Single processor-internal bus via I/D mux)
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  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle processing scheme
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  * No hardware support of unaligned accesses - they will trigger an exception
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  * BIG-ENDIAN byte-order, processor's external memory interface allows endianness configuration to connect to system with different endianness
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  * All reserved or unimplemented instructions will raise an illegal instruction exception
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  * Privilege levels: `machine` mode, `user` mode (if enabled via `U` extension)
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  * Official [RISC-V open-source architecture ID](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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#### Atomic memory access (`A` extension)
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  * Supported instructions: `LR.W` (load-reservate) `SC.W` (store-conditional)
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#### Bit manipulation instructions (`B` extension)
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  * :warning: Extension is not officially ratified yet by the RISC-V foundation!
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  * Implies `Zbb` extension (base bit manipulation instruction set)
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  * Compatible to [v0.94-draft](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/bitmanip-draft.pdf) of the bit manipulation spec
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  * Support via intrisc library (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation))
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  * Only the `Zbb` base instructions subset is supported yet
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  * Supported instructions: `CLZ` `CTZ` `CPOP` `SEXT.B` `SEXT.H` `MIN[U]` `MAX[U]` `ANDN` `ORN` `XNOR` `ROL` `ROR` `RORI` `zext`(*pseudo-instruction* for `PACK rd, rs, zero`) `rev8`(*pseudo-instruction* for `GREVI rd, rs, -8`) `orc.b`(*pseudo-instruction* for `GORCI rd, rs, 7`)
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#### Compressed instructions (`C` extension)
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  * ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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  * Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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  * Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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  * System instructions: `C.EBREAK` (only with `Zicsr` extension)
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  * Pseudo-instructions are not listed
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#### Embedded CPU version (`E` extension)
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  * Reduced register file (only the 16 lowest registers)
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#### Integer base instruction set (`I` extension)
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  * ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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  * Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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  * Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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  * System instructions: `ECALL` `EBREAK` `FENCE`
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  * Pseudo-instructions are not listed
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#### Integer multiplication and division hardware (`M` extension)
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  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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  * Division instructions: `DIV` `DIVU` `REM` `REMU`
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  * By default, the multiplier and divider cores use an iterative bit-serial processing scheme
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  * Multiplications can be mapped to DSPs via the `FAST_MUL_EN` generic to increase performance
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#### Privileged architecture - User mode (`U` extension)
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  * Requires `Zicsr` extension
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  * Privilege levels: `M` (machine mode) + less-privileged `U` (user mode)
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#### NEORV32-specific CPU extensions (`X` extension)
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* The NEORV32-specific extensions are always enabled and are indicated via the `X` bit set in the `misa` CSR.
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* 16 *fast interrupt* request channels with according control/status bits in `mie` and `mip` and custom exception codes in `mcause`
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* `mzext` CSR to check for implemented `Z*` CPU extensions (like `Zifencei`)
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* All undefined/umimplemented/malformed/illegal instructions do raise an illegal instruction exception
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#### Privileged architecture - CSR access (`Zicsr` extension)
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  * Privilege levels: `M-mode` (Machine mode)
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  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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  * System instructions: `MRET` `WFI`
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  * Pseudo-instructions are not listed
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  * Counter CSRs: `[m]cycle[h]` `[m]instret[m]` `time[h]` `[m]hpmcounter*[h]`(3..31, configurable) `mcounteren` `mcountinhibit` `mhpmevent*`(3..31, configurable)
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  * Machine CSRs: `mstatus[h]` `misa`(read-only!) `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mvendorid` [`marchid`](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md) `mimpid` `mhartid` `mzext`(custom)
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  * Supported exceptions and interrupts:
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    * Misaligned instruction address
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    * Instruction access fault (via unacknowledged bus access after timeout)
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    * Illegal instruction
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    * Breakpoint (via `ebreak` instruction)
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    * Load address misaligned
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    * Load access fault (via unacknowledged bus access after timeout)
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    * Store address misaligned
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    * Store access fault (via unacknowledged bus access after timeout)
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    * Environment call from U-mode (via `ecall` instruction in user mode)
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    * Environment call from M-mode (via `ecall` instruction in machine mode)
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    * Machine timer interrupt `mti` (via processor's MTIME unit / external signal)
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    * Machine software interrupt `msi` (via external signal)
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    * Machine external interrupt `mei` (via external signal)
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    * Eight fast interrupt requests (custom extension)
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#### Privileged architecture - Instruction stream synchronization (`Zifencei` extension)
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  * System instructions: `FENCE.I` (among others, used to clear and reload instruction cache)
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#### Privileged architecture - Physical memory protection (`PMP`)
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  * Requires `Zicsr` extension
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  * Configurable number of regions (0..63)
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  * Additional machine CSRs: `pmpcfg*`(0..15) `pmpaddr*`(0..63)
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#### Privileged architecture - Hardware performance monitors (`HPM` extension)
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  * Requires `Zicsr` extension
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  * Configurable number of counters (0..29)
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  * Additional machine CSRs: `mhpmevent*`(3..31) `[m]hpmcounter*[h]`(3..31)
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### :warning: Non-RISC-V-Compliant Issues and Limitations
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* CPU and Processor are BIG-ENDIAN, but this should be no problem as the external memory bus interface provides big- and little-endian configurations
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* `misa` CSR is read-only - no dynamic enabling/disabling of synthesized CPU extensions during runtime; for compatibility: write accesses (in m-mode) are ignored and do not cause an exception
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* The physical memory protection (**PMP**) only supports `NAPOT` mode yet and a minimal granularity of 8 bytes
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* The `A` extension only implements `lr.w` and `sc.w` instructions yet. However, these instructions are sufficient to emulate all further AMO operations
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* The `mcause` trap code `0x80000000` (originally reserved in the RISC-V specs) is used to indicate a hardware reset (as "non-maskable interrupt")
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* The bit manipulation extension is not yet officially ratified, but is expected to stay unchanged. There is no software support in the upstream GCC RISC-V port yet. However, an intrinsic library is provided to utilize the provided bit manipulation extension from C-language code (see [`sw/example/bit_manipulation`](https://github.com/stnolting/neorv32/tree/master/sw/example/bit_manipulation)). NEORV32's `B`/`Zbb` extension is compliant to spec. version "0.94-draft".
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## FPGA Implementation Results
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### NEORV32 CPU
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This chapter shows exemplary implementation results of the NEORV32 CPU for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 20.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the CPU's generics is assumed (e.g. no physical memory protection, no hardware performance monitors).
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No constraints were used at all. The `u` and `Zifencei` extensions have a negligible impact on the hardware requirements.
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Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
303 2 zero_gravi
 
304 44 zero_gravi
| CPU Configuration                        | LEs        | FFs      | Memory bits | DSPs | f_max   |
305
|:-----------------------------------------|:----------:|:--------:|:-----------:|:----:|:-------:|
306 45 zero_gravi
| `rv32i`                                  |       1190 |      512 |        1024 |    0 | 120 MHz |
307
| `rv32i`     + `u` + `Zicsr` + `Zifencei` |       1927 |      903 |        1024 |    0 | 123 MHz |
308
| `rv32im`    + `u` + `Zicsr` + `Zifencei` |       2471 |     1148 |        1024 |    0 | 120 MHz |
309
| `rv32imc`   + `u` + `Zicsr` + `Zifencei` |       2716 |     1165 |        1024 |    0 | 120 MHz |
310
| `rv32imac`  + `u` + `Zicsr` + `Zifencei` |       2736 |     1168 |        1024 |    0 | 120 MHz |
311 47 zero_gravi
| `rv32imacb` + `u` + `Zicsr` + `Zifencei` |       3045 |     1260 |        1024 |    0 | 116 MHz |
312 2 zero_gravi
 
313 39 zero_gravi
Setups with enabled "embedded CPU extension" `E` show the same LUT and FF utilization and identical f_max. However, the size of the register file is cut in half.
314 2 zero_gravi
 
315 39 zero_gravi
 
316 23 zero_gravi
### NEORV32 Processor-Internal Peripherals and Memories
317
 
318 45 zero_gravi
Results generated for hardware version [`1.5.0.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
319 11 zero_gravi
 
320 25 zero_gravi
| Module    | Description                                          | LEs | FFs | Memory bits | DSPs |
321 31 zero_gravi
|:----------|:-----------------------------------------------------|----:|----:|------------:|-----:|
322 37 zero_gravi
| BOOT ROM  | Bootloader ROM (default 4kB)                         |   3 |   1 |      32 768 |    0 |
323 40 zero_gravi
| BUSSWITCH | Mux for CPU I & D interfaces                         |  65 |   8 |           0 |    0 |
324 45 zero_gravi
| i-CACHE   | Proc.-int. nstruction cache (default 1x4x64 bytes)   | 234 | 156 |       8 192 |    0 |
325 47 zero_gravi
| CFS       | Custom functions subsystem                           |   - |   - |           - |    - |
326 39 zero_gravi
| DMEM      | Processor-internal data memory (default 8kB)         |   6 |   2 |      65 536 |    0 |
327 40 zero_gravi
| GPIO      | General purpose input/output ports                   |  67 |  65 |           0 |    0 |
328 39 zero_gravi
| IMEM      | Processor-internal instruction memory (default 16kb) |   6 |   2 |     131 072 |    0 |
329 40 zero_gravi
| MTIME     | Machine system timer                                 | 274 | 166 |           0 |    0 |
330 39 zero_gravi
| PWM       | Pulse-width modulation controller                    |  71 |  69 |           0 |    0 |
331 40 zero_gravi
| SPI       | Serial peripheral interface                          | 138 | 124 |           0 |    0 |
332
| SYSINFO   | System configuration information memory              |  11 |  10 |           0 |    0 |
333 31 zero_gravi
| TRNG      | True random number generator                         | 132 | 105 |           0 |    0 |
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| TWI       | Two-wire interface                                   |  77 |  46 |           0 |    0 |
335
| UART      | Universal asynchronous receiver/transmitter          | 176 | 132 |           0 |    0 |
336
| WDT       | Watchdog timer                                       |  60 |  45 |           0 |    0 |
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| WISHBONE  | External memory interface                            | 129 | 104 |           0 |    0 |
338 2 zero_gravi
 
339
 
340 23 zero_gravi
### NEORV32 Processor - Exemplary FPGA Setups
341 6 zero_gravi
 
342 47 zero_gravi
Exemplary processor implementation results for different FPGA platforms. The processor setup uses *the default peripheral configuration* (like no _CFS_ and no _TRNG_),
343 23 zero_gravi
no external memory interface and only internal instruction and data memories. IMEM uses 16kB and DMEM uses 8kB memory space. The setup's top entity connects most of the
344 11 zero_gravi
processor's [top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) signals
345 40 zero_gravi
to FPGA pins - except for the Wishbone bus and the interrupt signals. The "default" strategy of each toolchain is used.
346 6 zero_gravi
 
347 40 zero_gravi
Results generated for hardware version [`1.4.9.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
348 6 zero_gravi
 
349 40 zero_gravi
| Vendor  | FPGA                              | Board            | Toolchain                  | CPU Configuration                              | LUT / LE   | FF / REG   | DSP    | Memory Bits  | BRAM / EBR | SPRAM    | Frequency     |
350
|:--------|:----------------------------------|:-----------------|:---------------------------|:-----------------------------------------------|:-----------|:-----------|:-------|:-------------|:-----------|:---------|--------------:|
351
| Intel   | Cyclone IV `EP4CE22F17C6N`        | Terasic DE0-Nano | Quartus Prime Lite 20.1    | `rv32imc` + `u` + `Zicsr` + `Zifencei`         | 3813 (17%) | 1904  (8%) | 0 (0%) | 231424 (38%) |          - |        - |       119 MHz |
352
| Lattice | iCE40 UltraPlus `iCE40UP5K-SG48I` | Upduino v2.0     | Radiant 2.1 (Synplify Pro) | `rv32ic`  + `u` + `Zicsr` + `Zifencei`         | 4397 (83%) | 1679 (31%) | 0 (0%) |            - |   12 (40%) | 4 (100%) | *c* 22.15 MHz |
353
| Xilinx  | Artix-7 `XC7A35TICSG324-1L`       | Arty A7-35T      | Vivado 2019.2              | `rv32imc` + `u` + `Zicsr` + `Zifencei` + `PMP` | 2465 (12%) | 1912  (5%) | 0 (0%) |            - |    8 (16%) |        - |   *c* 100 MHz |
354 2 zero_gravi
 
355 23 zero_gravi
**_Notes_**
356 20 zero_gravi
* The Lattice iCE40 UltraPlus setup uses the FPGA's SPRAM memory primitives for the internal IMEM and DMEM (each 64kb).
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The FPGA-specific memory components can be found in [`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up).
358
* The clock frequencies marked with a "c" are constrained clocks. The remaining ones are _f_max_ results from the place and route timing reports.
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* The Upduino and the Arty board have on-board SPI flash memories for storing the FPGA configuration. These device can also be used by the default NEORV32
360
bootloader to store and automatically boot an application program after reset (both tested successfully).
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* The setups with `PMP` implement 2 regions with a minimal granularity of 64kB.
362 42 zero_gravi
* No HPM counters are implemented.
363 2 zero_gravi
 
364 22 zero_gravi
 
365
 
366 2 zero_gravi
## Performance
367
 
368
### CoreMark Benchmark
369
 
370
The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
371
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
372
tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
373
 
374
~~~
375
**Configuration**
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Hardware:       32kB IMEM, 16kB DMEM, no caches, 100MHz clock
377 38 zero_gravi
CoreMark:       2000 iterations, MEM_METHOD is MEM_STACK
378
Compiler:       RISCV32-GCC 10.1.0 (rv32i toolchain)
379
Compiler flags: default, see makefile
380
Peripherals:    UART for printing the results
381 2 zero_gravi
~~~
382
 
383 42 zero_gravi
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
384
 
385
| CPU (including `Zicsr`)                     | Executable Size | Optimization | CoreMark Score | CoreMarks/MHz |
386 34 zero_gravi
|:--------------------------------------------|:---------------:|:------------:|:--------------:|:-------------:|
387 42 zero_gravi
| `rv32i`                                     |    28 756 bytes |        `-O3` |          36.36 |    **0.3636** |
388
| `rv32im`                                    |    27 516 bytes |        `-O3` |          68.97 |    **0.6897** |
389
| `rv32imc`                                   |    22 008 bytes |        `-O3` |          68.97 |    **0.6897** |
390
| `rv32imc` + `FAST_MUL_EN`                   |    22 008 bytes |        `-O3` |          86.96 |    **0.8696** |
391
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` |    22 008 bytes |        `-O3` |          90.91 |    **0.9091** |
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393 34 zero_gravi
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
394
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
395 2 zero_gravi
 
396 31 zero_gravi
When the `C` extension is enabled, branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
397 22 zero_gravi
 
398 34 zero_gravi
 
399 2 zero_gravi
### Instruction Cycles
400
 
401 11 zero_gravi
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme. Hence,
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each instruction requires several clock cycles to execute (2 cycles for ALU operations, ..., 40 cycles for divisions).
403
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on the available
404 42 zero_gravi
CPU extensions. *By default* the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
405 2 zero_gravi
`M` extension use a bit-serial approach and require several cycles for completion.
406
 
407 6 zero_gravi
The following table shows the performance results for successfully running 2000 CoreMark
408 9 zero_gravi
iterations, which reflects a pretty good "real-life" work load. The average CPI is computed by
409 12 zero_gravi
dividing the total number of required clock cycles (only the timed core to avoid distortion due to IO wait cycles; sampled via the `cycle[h]` CSRs)
410 19 zero_gravi
by the number of executed instructions (`instret[h]` CSRs). The executables were generated using optimization `-O3`.
411 2 zero_gravi
 
412 42 zero_gravi
Results generated for hardware version [`1.4.9.8`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
413 2 zero_gravi
 
414 42 zero_gravi
| CPU  (including `Zicsr`)                    | Required Clock Cycles | Executed Instructions | Average CPI |
415 34 zero_gravi
|:--------------------------------------------|----------------------:|----------------------:|:-----------:|
416 42 zero_gravi
| `rv32i`                                     |         5 595 750 503 |         1 466 028 607 |    **3.82** |
417
| `rv32im`                                    |         2 966 086 503 |           598 651 143 |    **4.95** |
418
| `rv32imc`                                   |         2 981 786 734 |           611 814 918 |    **4.87** |
419
| `rv32imc` + `FAST_MUL_EN`                   |         2 399 234 734 |           611 814 918 |    **3.92** |
420
| `rv32imc` + `FAST_MUL_EN` + `FAST_SHIFT_EN` |         2 265 135 174 |           611 814 948 |    **3.70** |
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422 34 zero_gravi
The `FAST_MUL_EN` configuration uses DSPs for the multiplier of the `M` extension (enabled via the `FAST_MUL_EN` generic). The `FAST_SHIFT_EN` configuration
423
uses a barrel shifter for CPU shift operations (enabled via the `FAST_SHIFT_EN` generic).
424
 
425 36 zero_gravi
When the `C` extension is enabled branches to an unaligned uncompressed instruction require additional instruction fetch cycles.
426 12 zero_gravi
 
427 22 zero_gravi
 
428 31 zero_gravi
 
429 14 zero_gravi
## Top Entities
430 2 zero_gravi
 
431 36 zero_gravi
The top entity of the **NEORV32 Processor** (SoC) is [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd).
432 2 zero_gravi
 
433 36 zero_gravi
All signals of the top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
434 34 zero_gravi
(except for the processor's TWI signals, which are of type *std_logic*). Leave all unused output ports unconnected (`open`) and tie all unused
435
input ports to zero (`'0'` or `(others => '0')`, respectively).
436 14 zero_gravi
 
437 36 zero_gravi
Use the top's generics to configure the system according to your needs. Each generic is initilized with the default configuration.
438 34 zero_gravi
Detailed information regarding the interface signals and configuration generics can be found in
439 40 zero_gravi
the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) (pdf).
440 22 zero_gravi
 
441 23 zero_gravi
 
442 36 zero_gravi
### Using the CPU in Stand-Alone Mode
443 23 zero_gravi
 
444 47 zero_gravi
If you *do not* want to use the NEORV32 processor setup, you can also use the CPU in stand-alone mode and build your own system around it.
445 36 zero_gravi
The top entity of the stand-alone **NEORV32 CPU** is [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd).
446
Note that the CPU uses a proprietary interface for accessing data and instruction memory. More information can be found in the
447 40 zero_gravi
[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
448 14 zero_gravi
 
449 47 zero_gravi
:information_source: It is recommended to use the processor setup even if you only want to use the CPU. Simply disable all the processor-internal modules via the generics
450
and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default
451
bootloader and software framework. From this base you can start building your own processor system.
452 2 zero_gravi
 
453 36 zero_gravi
 
454
### Alternative Top Entities
455
 
456
*Alternative top entities*, like the simplified ["hello world" test setup](#Create-a-new-Hardware-Project) or CPU/Processor
457
wrappers with resolved port signal types (i.e. *std_logic*), can be found in [`rtl/top_templates`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates).
458
 
459
 
460 35 zero_gravi
### AXI4 Connectivity
461 22 zero_gravi
 
462 35 zero_gravi
Via the [`rtl/top_templates/neorv32_top_axi4lite.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_top_axi4lite.vhd)
463
wrapper the NEORV32 provides an **AXI4-Lite** compatible master interface. This wrapper instantiates the default
464
[NEORV32 processor top entitiy](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) and implements a Wishbone to AXI4-Lite bridge.
465 2 zero_gravi
 
466 35 zero_gravi
The AXI4-Lite interface has been tested using Xilinx Vivado 19.2 block designer:
467
 
468
![AXI-SoC](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_axi_soc.png)
469
 
470
The processor was packed as custom IP using `neorv32_top_axi4lite.vhd` as top entity. The AXI interface is automatically detected by the packager.
471
All remaining IO interfaces are available as custom signals. The configuration generics are available via the "customize IP" dialog.
472
In the figure above the resulting IP block is named "neorv32_top_axi4lite_v1_0".
473
*(Note: Use Syntheiss option "global" when generating the block design to maintain the internal TWI tri-state drivers.)*
474
 
475
The setup uses an AXI interconnect to attach two block RAMs to the processor. Since the processor in this example is configured *without* IMEM and DMEM,
476
the attached block RAMs are used for storing instructions and data: the first RAM is used as instruction memory
477
and is mapped to address `0x00000000 - 0x00003fff` (16kB), the second RAM is used as data memory and is mapped to address `0x80000000 - 0x80001fff` (8kB).
478
 
479
 
480
 
481 2 zero_gravi
## Getting Started
482
 
483
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
484
 
485 40 zero_gravi
[:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
486 2 zero_gravi
 
487
 
488 14 zero_gravi
### Toolchain
489 2 zero_gravi
 
490
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
491
and build the toolchain by yourself, or you can download a prebuilt one and install it.
492
 
493 23 zero_gravi
To build the toolchain by yourself, follow the official [build instructions](https://github.com/riscv/riscv-gnu-toolchain).
494 14 zero_gravi
Make sure to use the `ilp32` or `ilp32e` ABI.
495 2 zero_gravi
 
496 15 zero_gravi
**Alternatively**, you can download a prebuilt toolchain. I have uploaded the toolchains I am using to GitHub. These toolchains
497 40 zero_gravi
were compiled on a 64-bit x86 Ubuntu 20.04 LTS (Ubuntu on Windows, actually). Download the toolchain of choice:
498 46 zero_gravi
[:octocat: github.com/stnolting/riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt)
499 2 zero_gravi
 
500 45 zero_gravi
You can also use the toolchains provided by [SiFive](https://github.com/sifive/freedom-tools/releases). These are 64-bit toolchains that can also emit 32-bit
501
RISC-V code. They were compiled for more sophisticated machines (`imac`) so the according hardware extensions are *mandatory*
502 2 zero_gravi
 
503 45 zero_gravi
:warning: Keep in mind that – for instance – a `rv32imc` toolchain only provides library code compiled with compressed and
504
`mul`/`div` instructions! Hence, this code cannot be executed (without emulation) on an architecture without these extensions!
505
 
506
 
507 22 zero_gravi
### Dowload the NEORV32 Project
508 2 zero_gravi
 
509 23 zero_gravi
Get the sources of the NEORV32 Processor project. The simplest way is using `git clone` (suggested for easy project updates via `git pull`):
510 12 zero_gravi
 
511 2 zero_gravi
    $ git clone https://github.com/stnolting/neorv32.git
512
 
513 23 zero_gravi
Alternatively, you can either download a specific [release](https://github.com/stnolting/neorv32/releases) or get the most recent version
514
of this project as [`*.zip` file](https://github.com/stnolting/neorv32/archive/master.zip).
515 2 zero_gravi
 
516 22 zero_gravi
 
517
### Create a new Hardware Project
518
 
519 23 zero_gravi
Create a new project with your FPGA design tool of choice. Add all the `*.vhd` files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
520
folder to this project. Make sure to add these files to a **new design library** called `neorv32`.
521
 
522 40 zero_gravi
You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) or one of its
523 36 zero_gravi
[wrappers](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates) in your own project. If you just want to try out the processor,
524
you can use the simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity.
525 2 zero_gravi
 
526 40 zero_gravi
![neorv32 test setup](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_test_setup.png)
527
 
528
 
529 33 zero_gravi
This test setup instantiates the processor and implements most of the peripherals and some ISA extensions. Only the UART lines, clock, reset and some GPIO output signals are
530 25 zero_gravi
propagated as actual entity signals. Basically, it is a FPGA "hello world" example:
531 23 zero_gravi
 
532 2 zero_gravi
```vhdl
533 9 zero_gravi
  entity neorv32_test_setup is
534
    port (
535
      -- Global control --
536
      clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
537
      rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
538
      -- GPIO --
539
      gpio_o     : out std_ulogic_vector(7 downto 0); -- parallel output
540
      -- UART --
541
      uart_txd_o : out std_ulogic; -- UART send data
542
      uart_rxd_i : in  std_ulogic := '0' -- UART receive data
543
    );
544
  end neorv32_test_setup;
545 2 zero_gravi
```
546
 
547
 
548 23 zero_gravi
### Check the Toolchain
549 2 zero_gravi
 
550 11 zero_gravi
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain navigate to an example project like
551 2 zero_gravi
`sw/example/blink_led` and run:
552
 
553
    neorv32/sw/example/blink_led$ make check
554
 
555 23 zero_gravi
 
556
### Compiling an Example Program
557
 
558 9 zero_gravi
The NEORV32 project includes some [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) from
559
which you can start your own application. Simply compile one of these projects. This will create a NEORV32
560 23 zero_gravi
*executable* `neorv32_exe.bin` in the same folder:
561 2 zero_gravi
 
562 23 zero_gravi
    neorv32/sw/example/blink_led$ make clean_all exe
563 2 zero_gravi
 
564 23 zero_gravi
 
565
### Upload the Executable via the Bootloader
566
 
567 34 zero_gravi
You can upload a generated executable directly from the command line using the makefile's `upload` target. Replace `/dev/ttyUSB0` with
568
the according serial port.
569
 
570
    sw/exeample/blink_example$ make COM_PORT=/dev/ttyUSB0` upload
571
 
572
A more "secure" way is to use a dedicated terminal program. This allows to directly interact with the bootloader console.
573 23 zero_gravi
Connect your FPGA board via UART to your computer and open the according port to interface with the NEORV32 bootloader. The bootloader
574 2 zero_gravi
uses the following default UART configuration:
575
 
576 32 zero_gravi
* 19200 Baud
577
* 8 data bits
578
* 1 stop bit
579
* No parity bits
580
* No transmission / flow control protocol (raw bytes only)
581
* Newline on `\r\n` (carriage return & newline) - also for sent data
582 2 zero_gravi
 
583 23 zero_gravi
Use the bootloader console to upload the `neorv32_exe.bin` executable and run your application image.
584 2 zero_gravi
 
585 9 zero_gravi
```
586 43 zero_gravi
<< NEORV32 Bootloader >>
587
 
588
BLDV: Nov  7 2020
589
HWV:  0x01040606
590
CLK:  0x0134FD90 Hz
591
USER: 0x0001CE40
592
MISA: 0x42801104
593
PROC: 0x03FF0035
594
IMEM: 0x00010000 bytes @ 0x00000000
595
DMEM: 0x00010000 bytes @ 0x80000000
596
 
597
Autoboot in 8s. Press key to abort.
598
Aborted.
599
 
600
Available CMDs:
601
 h: Help
602
 r: Restart
603
 u: Upload
604
 s: Store to flash
605
 l: Load from flash
606
 e: Execute
607
CMD:> u
608
Awaiting neorv32_exe.bin... OK
609
CMD:> e
610
Booting...
611
 
612
Blinking LED demo program
613 9 zero_gravi
```
614 2 zero_gravi
 
615 40 zero_gravi
Going further: Take a look at the _Let's Get It Started!_ chapter of the [:page_facing_up: NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
616 2 zero_gravi
 
617
 
618
 
619 40 zero_gravi
## Contribute/Feedback/Questions
620 2 zero_gravi
 
621 9 zero_gravi
I'm always thankful for help! So if you have any questions, bug reports, ideas or if you want to give some kind of feedback, feel free
622 40 zero_gravi
to [:bulb: open a new issue](https://github.com/stnolting/neorv32/issues), start a new [:sparkles: discussion on GitHub](https://github.com/stnolting/neorv32/discussions)
623
or directly [:e-mail: drop me a line](mailto:stnolting@gmail.com).
624 2 zero_gravi
 
625 40 zero_gravi
If you'd like to directly contribute to this repository:
626 22 zero_gravi
 
627 40 zero_gravi
0. :star: this repository ;)
628
1. Check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md)
629
2. [Fork](https://github.com/stnolting/neorv32/fork) this repository and clone the fork
630
3. Create a feature branch in your fork: `git checkout -b awesome_new_feature_branch`
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4. Create a new remote for the upstream repo: `git remote add upstream https://github.com/stnolting/neorv32`
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5. Commit your modifications: `git commit -m "Awesome new feature!"`
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6. Push to the branch: `git push origin awesome_new_feature_branch`
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7. Create a new [pull request](https://github.com/stnolting/neorv32/pulls)
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## Legal
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This project is released under the BSD 3-Clause license. No copyright infringement intended.
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Other implied or used projects might have different licensing - see their documentation to get more information.
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#### Citing
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If you are using the NEORV32 or some parts of the project in some kind of publication, please cite it as follows:
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> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
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#### BSD 3-Clause License
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Copyright (c) 2021, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are
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permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of
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conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
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conditions and the following disclaimer in the documentation and/or other materials
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provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
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endorse or promote products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
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OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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OF THE POSSIBILITY OF SUCH DAMAGE.
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#### Limitation of Liability for External Links
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Our website contains links to the websites of third parties ("external links"). As the
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content of these websites is not under our control, we cannot assume any liability for
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such external content. In all cases, the provider of information of the linked websites
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is liable for the content and accuracy of the information provided. At the point in time
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when the links were placed, no infringements of the law were recognisable to us. As soon
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as an infringement of the law becomes known to us, we will immediately remove the
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link in question.
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#### Proprietary  Notice
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"Artix" and "Vivado" are trademarks of Xilinx Inc.
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"Cyclone" and "Quartus Prime Lite" are trademarks of Intel Corporation.
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"iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
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"AXI", "AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
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## Acknowledgements
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[![RISC-V](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/riscv_logo.png)](https://riscv.org/)
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[RISC-V](https://riscv.org/) - Instruction Sets Want To Be Free!
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Continous integration provided by [:octocat: GitHub Actions](https://github.com/features/actions) and powered by [GHDL](https://github.com/ghdl/ghdl).
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![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
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This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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--------
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Made with :coffee: in Hannover, Germany :eu:

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