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# [The NEORV32 Processor](https://github.com/stnolting/neorv32)
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[![Build Status](https://travis-ci.com/stnolting/neorv32.svg?branch=master)](https://travis-ci.com/stnolting/neorv32)
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[![license](https://img.shields.io/github/license/stnolting/neorv32)](https://github.com/stnolting/neorv32/blob/master/LICENSE)
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[![release](https://img.shields.io/github/v/release/stnolting/neorv32)](https://github.com/stnolting/neorv32/releases)
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[![issues](https://img.shields.io/github/issues/stnolting/neorv32)](https://github.com/stnolting/neorv32/issues)
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[![pull requests](https://img.shields.io/github/issues-pr/stnolting/neorv32)](https://github.com/stnolting/neorv32/pulls)
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[![last commit](https://img.shields.io/github/last-commit/stnolting/neorv32)](https://github.com/stnolting/neorv32/commits/master)
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## Table of Content
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* [Introduction](#Introduction)
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* [Features](#Features)
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* [FPGA Implementation Results](#FPGA-Implementation-Results)
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* [Performance](#Performance)
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* [Top Entity](#Top-Entity)
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* [**Getting Started**](#Getting-Started)
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* [Contact](#Contact)
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* [Legal](#Legal)
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## Introduction
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The NEORV32 is a customizable mikrocontroller-like processor system based on a RISC-V `rv32i` or `rv32e` CPU with optional
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`M`, `C` and `Zicsr` extensions. The CPU was built from scratch and is compliant to the **Unprivileged
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ISA Specification Version 2.1** and a subset of the **Privileged Architecture Specification Version 1.12**. The NEORV32 is intended
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as auxiliary processor within a larger SoC designs or as stand-alone custom microcontroller.
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The processor provides common peripherals and interfaces like input and output ports, serial interfaces for UART, I²C and SPI,
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interrupt controller, timers and embedded memories. External memories, peripherals and custom IP can be attached via a
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Wishbone-based external memory interface. All optional features beyond the base CPU can be enabled configured via VHDL generics.
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This project comes with a complete software ecosystem that features core libraries for high-level usage of the
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provided functions and peripherals, application makefiles and example programs. All software source files
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provide a doxygen-based documentary.
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The project is intended to work "out of the box". Just synthesize the test setup from this project, upload
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it to your FPGA board of choice and start playing with the NEORV32. If you do not want to [compile the GCC toolchains](https://github.com/riscv/riscv-gnu-toolchain)
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by yourself, you can also download [pre-compiled toolchain](https://github.com/stnolting/riscv_gcc_prebuilt) for Linux.
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For more information take a look a the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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### Design Principles
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 * From zero to main(): Completely open source and documented.
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 * Plain VHDL without technology-specific parts like attributes, macros or primitives.
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 * Easy to use – working out of the box.
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 * Clean synchronous design, no wacky combinatorial interfaces.
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 * The processor has to fit in a Lattice iCE40 UltraPlus 5k FPGA running at 20+ MHz.
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57
### Status
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The processor is synthesizable (tested with Intel Quartus Prime, Xilinx Vivado and Lattice Radiant/LSE) and can successfully execute
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all the [provided example programs](https://github.com/stnolting/neorv32/tree/master/sw/example) including the CoreMark benchmark.
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The processor passes the official `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr` [RISC-V compliance tests](https://github.com/riscv/riscv-compliance).
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|                                                                                 |        |
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|:--------------------------------------------------------------------------------|:-------|
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| [Pre-build toolchain](https://github.com/stnolting/riscv_gcc_prebuilt)          | [![Build Test](https://travis-ci.com/stnolting/riscv_gcc_prebuilt.svg?branch=master)](https://travis-ci.com/stnolting/riscv_gcc_prebuilt) |
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| [RISC-V compliance test](https://github.com/stnolting/neorv32_compliance_test)  | [![Build Status](https://travis-ci.com/stnolting/neorv32_riscv_compliance.svg?branch=master)](https://travis-ci.com/stnolting/neorv32_riscv_compliance) |
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#### Limitations to be fixed
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* No exception is triggered in `E`-mode when using registers above `x15` yet
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74
 
75
#### To-Do / Wish List
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- Port Dhrystone benchmark
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- Implement atomic operations (`A` extension)
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- Implement `Zifence` extension
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- Implement co-processor for single-precision floating-point operations (`F` extension)
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- Implement user mode (`U` extension)
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- Make a 64-bit branch
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- Maybe port an RTOS (like [freeRTOS](https://www.freertos.org/) or [RIOT](https://www.riot-os.org/))
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## Features
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![neorv32 Overview](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/neorv32_overview.png)
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91
### Processor Features
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93
  - RISC-V-compliant `rv32i` or `rv32e` CPU with optional `C`, `E`, `M` and `Zicsr` extensions
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  - GCC-based toolchain ([pre-compiled rv32i and rv32 etoolchains available](https://github.com/stnolting/riscv_gcc_prebuilt))
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  - Application compilation based on [GNU makefiles](https://github.com/stnolting/neorv32/blob/master/sw/example/blink_led/makefile)
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  - [Doxygen-based](https://github.com/stnolting/neorv32/blob/master/docs/doxygen_makefile_sw) documentation of the software framework
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  - Completely described in behavioral, platform-independent VHDL – no primitives, macros, etc.
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  - Fully synchronous design, no latches, no gated clocks
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  - Small hardware footprint and high operating frequency
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  - Highly customizable processor configuration
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  - Optional processor-internal data and instruction memories (DMEM/IMEM)
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  - _Optional_ internal bootloader with UART console and automatic SPI flash boot option
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  - _Optional_ machine system timer (MTIME), RISC-V-compliant
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  - _Optional_ universal asynchronous receiver and transmitter (UART)
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  - _Optional_ 8/16/24/32-bit serial peripheral interface controller (SPI) with 8 dedicated chip select lines
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  - _Optional_ two wire serial interface controller (TWI), compatible to the I²C standard
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  - _Optional_ general purpose parallel IO port (GPIO), 16xOut & 16xIn, with pin-change interrupt
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  - _Optional_ 32-bit external bus interface, Wishbone b4 compliant (WISHBONE)
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  - _Optional_ watchdog timer (WDT)
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  - _Optional_ PWM controller with 4 channels and 8-bit duty cycle resolution (PWM)
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  - _Optional_ GARO-based true random number generator (TRNG)
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  - _Optional_ core-local interrupt controller with 8 channels (CLIC)
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  - _Optional_ dummy device (DEVNULL) (can be used for *fast* simulation console output)
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116
### CPU Features
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The CPU is compliant to the [official RISC-V specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf) including a subset of the
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[RISC-V privileged architecture specifications](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/riscv-spec.pdf).
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**RV32I base instruction set** (`I` extension):
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  * ALU instructions: `LUI` `AUIPC` `ADDI` `SLTI` `SLTIU` `XORI` `ORI` `ANDI` `SLLI` `SRLI` `SRAI` `ADD` `SUB` `SLL` `SLT` `SLTU` `XOR` `SRL` `SRA` `OR` `AND`
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  * Jump and branch instructions: `JAL` `JALR` `BEQ` `BNE` `BLT` `BGE` `BLTU` `BGEU`
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  * Memory instructions: `LB` `LH` `LW` `LBU` `LHU` `SB` `SH` `SW`
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**Compressed instructions** (`C` extension):
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  * ALU instructions: `C.ADDI4SPN` `C.ADDI` `C.ADD` `C.ADDI16SP` `C.LI` `C.LUI` `C.SLLI` `C.SRLI` `C.SRAI` `C.ANDI` `C.SUB` `C.XOR` `C.OR` `C.AND` `C.MV` `C.NOP`
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  * Jump and branch instructions: `C.J` `C.JAL` `C.JR` `C.JALR` `C.BEQZ` `C.BNEZ`
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  * Memory instructions: `C.LW` `C.SW` `C.LWSP` `C.SWSP`
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  * Misc instructions: `C.EBREAK` (only with `Zicsr` extension)
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**Embedded CPU version** (`E` extension):
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  * Reduced register file (only the 16 lowest registers)
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  * No performance counter CSRs
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**Integer multiplication and division hardware** (`M` extension):
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  * Multiplication instructions: `MUL` `MULH` `MULHSU` `MULHU`
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  * Division instructions: `DIV` `DIVU` `REM` `REMU`
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**Privileged architecture** (`Zicsr` extension):
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  * Privilege levels: `M-mode` (Machine mode)
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  * CSR access instructions: `CSRRW` `CSRRS` `CSRRC` `CSRRWI` `CSRRSI` `CSRRCI`
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  * System instructions: `ECALL` `EBREAK` `MRET` `WFI`
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  * Counter CSRs: `cycle` `cycleh` `time` `timeh` `instret` `instreth` `mcycle` `mcycleh` `minstret` `minstreth`
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  * Machine CSRs: `mstatus` `misa` `mie` `mtvec` `mscratch` `mepc` `mcause` `mtval` `mip` `mimpid` `mhartid`
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  * Custom CSRs: `mfeatures` `mclock` `mispacebase` `mdspacebase` `mispacesize` `mdspacesize`
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  * Supported exceptions and interrupts:
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    * Misaligned instruction address
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    * Instruction access fault
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    * Illegal instruction
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    * Breakpoint (via `ebreak` instruction)
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    * Load address misaligned
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    * Load access fault
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    * Store address misaligned
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    * Store access fault
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    * Environment call from M-mode (via `ecall` instruction)
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    * Machine software instrrupt
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    * Machine timer interrupt (via `MTIME` unit)
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    * Machine external interrupt (via `CLIC` unit)
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**General**:
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  * No hardware support of unaligned accesses - they will trigger and exception
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  * Two stages in-order pipeline (FETCH, EXECUTE); each stage uses a multi-cycle execution
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More information including a detailed list of the available CSRs can be found in
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the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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## FPGA Implementation Results
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This chapter shows exemplary implementation results of the NEORV32 processor for an **Intel Cyclone IV EP4CE22F17C6N FPGA** on
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a DE0-nano board. The design was synthesized using **Intel Quartus Prime Lite 19.1** ("balanced implementation"). The timing
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information is derived from the Timing Analyzer / Slow 1200mV 0C Model. If not otherwise specified, the default configuration
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of the processor's generics is assumed. No constraints were used.
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Results generated for hardware version: `1.0.0.0`
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179
### CPU
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| CPU Configuration   | LEs        | FFs      | Memory bits | DSPs   | f_max   |
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|:--------------------|:----------:|:--------:|:-----------:|:------:|:-------:|
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| `rv32i`             |       1027 |      474 |       2048  | 0 (0%) | 111 MHz |
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| `rv32i` + `Zicsr`   |       1721 |      868 |       2048  | 0 (0%) | 104 MHz |
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| `rv32im` + `Zicsr`  |       2298 |     1115 |       2048  | 0 (0%) | 103 MHz |
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| `rv32imc` + `Zicsr` |       2557 |     1138 |       2048  | 0 (0%) | 103 MHz |
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| `rv32emc` + `Zicsr` |       2342 |     1005 |       1024  | 0 (0%) | 100 MHz |
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### Processor-Internal Peripherals and Memories
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| Module   | Description                                     | LEs | FFs | Memory bits | DSPs |
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|:---------|:------------------------------------------------|:---:|:---:|:-----------:|:----:|
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| BOOT ROM | Bootloader ROM (4kB)                            |   3 |   1 |      32 768 |    0 |
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| DEVNULL  | Dummy device                                    |   3 |   1 |           0 |    0 |
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| DMEM     | Processor-internal data memory (8kB)            |  12 |   2 |      65 536 |    0 |
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| GPIO     | General purpose input/output ports              |  38 |  33 |           0 |    0 |
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| IMEM     | Processor-internal instruction memory (16kb)    |   7 |   2 |     131 072 |    0 |
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| MTIME    | Machine system timer                            | 270 | 167 |           0 |    0 |
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| PWM      | Pulse-width modulation controller               |  76 |  69 |           0 |    0 |
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| SPI      | Serial peripheral interface                     | 206 | 125 |           0 |    0 |
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| TRNG     | True random number generator                    | 104 |  93 |           0 |    0 |
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| TWI      | Two-wire interface                              |  78 |  44 |           0 |    0 |
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| UART     | Universal asynchronous receiver/transmitter     | 151 | 108 |           0 |    0 |
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| WDT      | Watchdog timer                                  |  57 |  45 |           0 |    0 |
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### CPU + Peripheral
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The following table shows the implementation results for an _Intel Cyclone IV EP4CE22F17C6N_ FPGA.
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The design was synthesized using Intel Quartus Prime Lite 19.1 (“balanced implementation”).
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IMEM uses 16kB and DMEM uses 8kB memory space.
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| CPU Configuration   | LEs        | REGs      | DSPs   | Memory Bits  | f_max   |
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|:--------------------|:----------:|:---------:|:------:|:------------:|:-------:|
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| `rv32imc` + `Zicsr` | 3724 (17%) | 1899 (9%) | 0 (0%) | 231424 (38%) | 103 MHz |
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### Lattice iCE40 UltraPlus 5k
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The following table shows the hardware utilization for a [iCE40 UP5K](http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus) FPGA.
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The setup uses all provided peripherals, all CPU extensions (except for the `E` extension), no external memory interface and internal
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instruction and data memories (each 64kB) based on SPRAM primitives. The FPGA-specific memory components can be found in the
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[`rtl/fpga_specific`](https://github.com/stnolting/neorv32/blob/master/rtl/fpga_specific/lattice_ice40up) folder.
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Place & route reports generated with **Lattice Radiant 2.1** using Lattice LSE. The clock frequency
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is constrained and generated via the PLL from the internal HF oscillator running at 12 MHz.
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| CPU Configuration   | LUTs       | REGs       | DSPs   | SPRAM    | EBR      | f         |
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|:--------------------|:----------:|:----------:|:------:|:--------:|:--------:|:---------:|
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| `rv32imc` + `Zicsr` | 4985 (94%) | 1982 (38%) | 0 (0%) | 4 (100%) | 12 (40%) | 20.25 MHz |
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## Performance
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234
### CoreMark Benchmark
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The [CoreMark CPU benchmark](https://www.eembc.org/coremark) was executed on the NEORV32 and is available in the
237
[sw/example/coremark](https://github.com/stnolting/neorv32/blob/master/sw/example/coremark) project folder. This benchmark
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tests the capabilities of a CPU itself rather than the functions provided by the whole system / SoC.
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Results generated for hardware version: `1.0.0.0`
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242
~~~
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**Configuration**
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Hardware:         32kB IMEM, 16kb DMEM, 100MHz clock
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CoreMark:         2000 iterations, MEM_METHOD is MEM_STACK
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CPU extensions:   `rv32i` or `rv32im` or `rv32imc`
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Used peripherals: MTIME for time measurement, UART for printing the results
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~~~
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| __Configuration__ | __Optimization__ | __Executable Size__ | __CoreMark Score__ | __CoreMarks/MHz__ |
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|:------------------|:----------------:|:-------------------:|:------------------:|:-----------------:|
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| `rv32i`           |      `-Os`       |     18 044 bytes    |       21.98        |       0.21        |
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| `rv32i`           |      `-O2`       |     20 388 bytes    |        25          |       0.25        |
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| `rv32im`          |      `-Os`       |     16 980 bytes    |        40          |       0.40        |
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| `rv32im`          |      `-O2`       |     19 436 bytes    |       51.28        |       0.51        |
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| `rv32imc`         |      `-Os`       |     13 076 bytes    |       39.22        |       0.39        |
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| `rv32imc`         |      `-O2`       |     15 208 bytes    |        50          |       0.50        |
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### Instruction Cycles
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The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of several
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consecutive micro operations. Hence, each instruction requires several clock cycles to execute. The average CPI
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(cycles per instruction) depends on the instruction mix of a specific applications and also on the available
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CPU extensions.
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Please note that the CPU-internal shifter (e.g. for the `SLL` instruction) as well as the multiplier and divider of the
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`M` extension use a bit-serial approach and require several cycles for completion.
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The following table shows the performance results for successfully running 2000 CoreMark
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iterations. The average CPI is computed by dividing the total number of required clock cycles (all of CoreMark
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– not only the timed core) by the number of executed instructions (`instret[h]` CSRs). The executables
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were generated using optimization `-O2`.
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| CPU / Toolchain Config. | Required Clock Cycles | Executed Instructions | Average CPI |
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|:------------------------|----------------------:|----------------------:|:-----------:|
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| `rv32i`                 |        19 355 607 369 |         2 995 064 579 |     6.5     |
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| `rv32im`                |         5 809 384 583 |           867 377 291 |     6.7     |
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| `rv32imc`               |         5 560 220 723 |           825 898 407 |     6.7     |
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## Top Entity
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The top entity of the processor is [**neorv32_top.vhd**](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd) (from the `rtl/core` folder).
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Just instantiate this file in your project and you are ready to go! All signals of this top entity are of type *std_ulogic* or *std_ulogic_vector*, respectively
287
(except for the TWI signals, which are of type *std_logic*).
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Use the generics to configure the processor according to your needs. Each generics is initilized with the default configuration.
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Detailed information regarding the signals and configuration generics can be found in the [NEORV32 documentary](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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292
```vhdl
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entity neorv32_top is
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  generic (
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    -- General --
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    CLOCK_FREQUENCY           : natural := 0;       -- clock frequency of clk_i in Hz
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    HART_ID                   : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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    BOOTLOADER_USE            : boolean := true;    -- implement processor-internal bootloader?
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    CSR_COUNTERS_USE          : boolean := true;   -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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    -- RISC-V CPU Extensions --
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    CPU_EXTENSION_RISCV_C     : boolean := false;   -- implement compressed extension?
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    CPU_EXTENSION_RISCV_E     : boolean := false;   -- implement embedded RF extension?
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    CPU_EXTENSION_RISCV_M     : boolean := false;   -- implement muld/div extension?
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    CPU_EXTENSION_RISCV_Zicsr : boolean := true;    -- implement CSR system?
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    -- Memory configuration: Instruction memory --
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    MEM_ISPACE_BASE           : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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    MEM_ISPACE_SIZE           : natural := 16*1024; -- total size of instruction memory space in byte
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    MEM_INT_IMEM_USE          : boolean := true;    -- implement processor-internal instruction memory
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    MEM_INT_IMEM_SIZE         : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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    MEM_INT_IMEM_ROM          : boolean := false;   -- implement processor-internal instruction memory as ROM
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    -- Memory configuration: Data memory --
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    MEM_DSPACE_BASE           : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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    MEM_DSPACE_SIZE           : natural := 8*1024;  -- total size of data memory space in byte
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    MEM_INT_DMEM_USE          : boolean := true;    -- implement processor-internal data memory
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    MEM_INT_DMEM_SIZE         : natural := 8*1024;  -- size of processor-internal data memory in bytes
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    -- Memory configuration: External memory interface --
317
    MEM_EXT_USE               : boolean := false;   -- implement external memory bus interface?
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    MEM_EXT_REG_STAGES        : natural := 2;       -- number of interface register stages (0,1,2)
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    MEM_EXT_TIMEOUT           : natural := 15;      -- cycles after which a valid bus access will timeout (>=1)
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    -- Processor peripherals --
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    IO_GPIO_USE               : boolean := true;    -- implement general purpose input/output port unit (GPIO)?
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    IO_MTIME_USE              : boolean := true;    -- implement machine system timer (MTIME)?
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    IO_UART_USE               : boolean := true;    -- implement universal asynchronous receiver/transmitter (UART)?
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    IO_SPI_USE                : boolean := true;    -- implement serial peripheral interface (SPI)?
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    IO_TWI_USE                : boolean := true;    -- implement two-wire interface (TWI)?
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    IO_PWM_USE                : boolean := true;    -- implement pulse-width modulation unit (PWM)?
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    IO_WDT_USE                : boolean := true;    -- implement watch dog timer (WDT)?
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    IO_CLIC_USE               : boolean := true;    -- implement core local interrupt controller (CLIC)?
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    IO_TRNG_USE               : boolean := false;   -- implement true random number generator (TRNG)?
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    IO_DEVNULL_USE            : boolean := true     -- implement dummy device (DEVNULL)?
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  );
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  port (
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    -- Global control --
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    clk_i        : in  std_ulogic := '0'; -- global clock, rising edge
335
    rstn_i       : in  std_ulogic := '0'; -- global reset, low-active, async
336
    -- Wishbone bus interface (available if MEM_EXT_USE = true) --
337
    wb_adr_o     : out std_ulogic_vector(31 downto 0); -- address
338
    wb_dat_i     : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
339
    wb_dat_o     : out std_ulogic_vector(31 downto 0); -- write data
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    wb_we_o      : out std_ulogic; -- read/write
341
    wb_sel_o     : out std_ulogic_vector(03 downto 0); -- byte enable
342
    wb_stb_o     : out std_ulogic; -- strobe
343
    wb_cyc_o     : out std_ulogic; -- valid cycle
344
    wb_ack_i     : in  std_ulogic := '0'; -- transfer acknowledge
345
    wb_err_i     : in  std_ulogic := '0'; -- transfer error
346
    -- GPIO (available if IO_GPIO_USE = true) --
347
    gpio_o       : out std_ulogic_vector(15 downto 0); -- parallel output
348
    gpio_i       : in  std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
349
    -- UART (available if IO_UART_USE = true) --
350
    uart_txd_o   : out std_ulogic; -- UART send data
351
    uart_rxd_i   : in  std_ulogic := '0'; -- UART receive data
352
    -- SPI (available if IO_SPI_USE = true) --
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    spi_sck_o    : out std_ulogic; -- serial clock line
354
    spi_sdo_o    : out std_ulogic; -- serial data line out
355
    spi_sdi_i    : in  std_ulogic := '0'; -- serial data line in
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    spi_csn_o    : out std_ulogic_vector(07 downto 0); -- SPI CS
357
    -- TWI (available if IO_TWI_USE = true) --
358
    twi_sda_io   : inout std_logic := 'H'; -- twi serial data line
359
    twi_scl_io   : inout std_logic := 'H'; -- twi serial clock line
360
    -- PWM (available if IO_PWM_USE = true) --
361
    pwm_o        : out std_ulogic_vector(03 downto 0); -- pwm channels
362
    -- Interrupts (available if IO_CLIC_USE = true) --
363
    ext_irq_i    : in  std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
364
    ext_ack_o    : out std_ulogic_vector(01 downto 0)  -- external interrupt request acknowledge
365
  );
366
end neorv32_top;
367
```
368
 
369
 
370
 
371
## Getting Started
372
 
373
This overview is just a short excerpt from the *Let's Get It Started* section of the NEORV32 documentary:
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375
[![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf)
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377
 
378
### Building the Toolchain
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380
At first you need the **RISC-V GCC toolchain**. You can either [download the sources](https://github.com/riscv/riscv-gnu-toolchain)
381
and build the toolchain by yourself, or you can download a prebuilt one and install it.
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383
To build the toolchain by yourself, get the sources from the official [RISCV-GNU-TOOLCHAIN](https://github.com/riscv/riscv-gnu-toolchain) github page:
384
 
385
    $ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
386
 
387
Download and install the prerequisite standard packages:
388
 
389
    $ sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
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391
To build the Linux cross-compiler, pick an install path. If you choose, say, `/opt/riscv`, then add `/opt/riscv/bin` to your `PATH` environment variable.
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393
    $ export PATH:$PATH:/opt/riscv/bin
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395
Then, simply run the following commands in the RISC-V GNU toolchain source folder (for the `rv32i` toolchain):
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397
    riscv-gnu-toolchain$ ./configure --prefix=/opt/riscv --with-arch=rv32i –with-abi=ilp32
398
    riscv-gnu-toolchain$ make
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400
After a while (hours!) you will get `riscv32-unknown-elf-gcc` and all of its friends in your `/opt/riscv/bin` folder.
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403
### Using a Prebuilt Toolchain
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405
Alternatively, you can download a prebuilt toolchain. I have uploaded the toolchain I am using to GitHub. This toolchain
406
has been compiled on a 64-bit x86 Ubuntu (Ubuntu on Windows). Download the toolchain of choice:
407
 
408
[https://github.com/stnolting/riscv_gcc_prebuilt](https://github.com/stnolting/riscv_gcc_prebuilt)
409
 
410
 
411
### Dowload the Project and Create a Hardware Project
412
 
413
Now its time to get the most recent version the NEORV32 Processor project from GitHub. Clone the NEORV32 repository using
414
`git` from the command line (suggested for easy project updates via `git pull`):
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416
    $ git clone https://github.com/stnolting/neorv32.git
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Create a new HW project with your FPGA design tool of choice. Add all files from the [`rtl/core`](https://github.com/stnolting/neorv32/blob/master/rtl)
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folder to this project and add them to a **new library** called `neorv32`.
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You can either instantiate the [processor's top entity](https://github.com/stnolting/neorv32#top-entity) in you own project, or you
422
can use a simple [test setup](https://github.com/stnolting/neorv32/blob/master/rtl/top_templates/neorv32_test_setup.vhd) as top entity. This test
423
setup instantiates the processor, implements most of the peripherals and the basic ISA. Only the UART, clock, reset and some GPIO output sginals are
424
propagated:
425
 
426
```vhdl
427
entity neorv32_test_setup is
428
  port (
429
    -- Global control --
430
    clk_i      : in  std_ulogic := '0'; -- global clock, rising edge
431
    rstn_i     : in  std_ulogic := '0'; -- global reset, low-active, async
432
    -- GPIO --
433
    gpio_o     : out std_ulogic_vector(7 downto 0); -- parallel output
434
    -- UART --
435
    uart_txd_o : out std_ulogic; -- UART send data
436
    uart_rxd_i : in  std_ulogic := '0' -- UART receive data
437
  );
438
end neorv32_test_setup;
439
```
440
 
441
This test setup is intended as quick and easy "hello world" test setup to get into the NEORV32.
442
 
443
 
444
### Compiling and Uploading One of the Example Projects
445
 
446
Make sure `GNU Make` and a native `GCC` compiler are installed. To test the installation of the RISC-V toolchain, navigate to an example project like
447
`sw/example/blink_led` and run:
448
 
449
    neorv32/sw/example/blink_led$ make check
450
 
451
The NEORV32 project includes some example programs from which you can start your own application:
452
[SW example projects](https://github.com/stnolting/neorv32/tree/master/sw/example)
453
 
454
Simply compile one of these projects. This will create a NEORV32 executable `neorv32_exe.bin` in the same folder.
455
 
456
    neorv32/sw/example/blink_led$ make clean_all compile
457
 
458
Connect your FPGA board via UART to you computer and open the according port to interface with the NEORV32 bootloader. The bootloader
459
uses the following default UART configuration:
460
 
461
- 19200 Baud
462
- 8 data bits
463
- 1 stop bit
464
- No parity bits
465
- No transmission / flow control protocol (raw bytes only)
466
- Newline on `\r\n` (carriage return & newline)
467
 
468
Use the bootloader console to upload and execute your application image.
469
 
470
Going further: Take a look at the [![NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/PDF_32.png) NEORV32 datasheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf).
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472
 
473
 
474
## Contact
475
 
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If you have any questions, bug reports, ideas or if you are facing problems with the NEORV32 or want to give some kind of feedback, open a
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[new issue](https://github.com/stnolting/neorv32/issues) or directly drop me a line:
478
 
479
  stnolting@gmail.com
480
 
481
 
482
 
483
## Citation
484
 
485
If you are using the NEORV32 Processor in some kind of publication, please cite it as follows:
486
 
487
> S. Nolting, "The NEORV32 Processor", github.com/stnolting/neorv32
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490
 
491
## Legal
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This is a hobby project released under the BSD 3-Clause license. No copyright infringement intended.
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Other implied/used projects might have different licensing - see their documentation to get more information.
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496
**BSD 3-Clause License**
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498
Copyright (c) 2020, Stephan Nolting. All rights reserved.
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500
Redistribution and use in source and binary forms, with or without modification, are
501
permitted provided that the following conditions are met:
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503
1. Redistributions of source code must retain the above copyright notice, this list of
504
conditions and the following disclaimer.
505
2. Redistributions in binary form must reproduce the above copyright notice, this list of
506
conditions and the following disclaimer in the documentation and/or other materials
507
provided with the distribution.
508
3. Neither the name of the copyright holder nor the names of its contributors may be used to
509
endorse or promote products derived from this software without specific prior written
510
permission.
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512
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
513
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
514
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
515
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
516
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
517
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
518
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
519
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
520
OF THE POSSIBILITY OF SUCH DAMAGE.
521
 
522
 
523
"Windows" is a trademark of Microsoft Corporation.
524
 
525
"Artix" and "Vivado" are trademarks of Xilinx Inc.
526
 
527
"Cyclone", "Quartus Prime" and "Avalon Bus" are trademarks of Intel Corporation.
528
 
529
"iCE40", "UltraPlus" and "Lattice Radiant" are trademarks of Lattice Semiconductor Corporation.
530
 
531
"AXI4" and "AXI4-Lite" are trademarks of Arm Holdings plc.
532
 
533
 
534
[![Continous Integration provided by Travis CI](https://travis-ci.com/images/logos/TravisCI-Full-Color.png)](https://travis-ci.com/stnolting/neorv32)
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536
Continous integration provided by [Travis CI](https://travis-ci.com/stnolting/neorv32) and powered by [GHDL](https://github.com/ghdl/ghdl).
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538
 
539
![Open Source Hardware Logo https://www.oshwa.org](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/figures/oshw_logo.png)
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541
This project is not affiliated with or endorsed by the Open Source Initiative (https://www.oshwa.org / https://opensource.org).
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543
 
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Made with :coffee: in Hannover, Germany.

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