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:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.6.4
:doctype: book
:sectnums:
:stem:
:reproducible:
:listing-caption: Listing
:toclevels: 4
:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
:favicon: img/icon.png

Line No.	Rev	Author	Line
1	61	zero_gravi	`:author: Dipl.-Ing. Stephan Nolting`
2			`:email: stnolting@gmail.com`
3	65	zero_gravi	`:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb`
4	61	zero_gravi	`:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.`
5	68	zero_gravi	`:revnumber: v1.6.4`
6	61	zero_gravi	`:doctype: book`
7			`:sectnums:`
8			`:stem:`
9			`:reproducible:`
10			`:listing-caption: Listing`
11			`:toclevels: 4`
12			`:title-logo-image: neorv32_logo_dark.png[pdfwidth=6.25in,align=center]`
13			`:favicon: img/icon.png`

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[/] [neorv32/] [trunk/] [docs/] [attrs.adoc] - Blame information for rev 68