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<<<
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:sectnums:
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=== Control and Status Registers (CSRs)
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The following table shows a summary of all available CSRs. The address field defines the CSR address for
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the CSR access instructions. The *[ASM]* name can be used for (inline) assembly code and is directly
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understood by the assembler/compiler. The *[C]* names are defined by the NEORV32 core library and can be
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used as immediate in plain C code. The *R/W* column shows whether the CSR can be read and/or written.
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The NEORV32-specific CSRs are mapped to the official "custom CSRs" CSR address space.
10
 
11
[IMPORTANT]
12
The CSRs, the CSR-related instructions as well as the complete exception/interrupt processing
13
system are only available when the `CPU_EXTENSION_RISCV_Zicsr` generic is _true_.
14
 
15
[IMPORTANT]
16
When trying to write to a read-only CSR (like the `time` CSR) or when trying to access a nonexistent
17
CSR or when trying to access a machine-mode CSR from less-privileged user-mode an
18
illegal instruction exception is raised.
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20
[NOTE]
21
CSR reset value: Please note that most of the CSRs do *NOT* provide a dedicated reset. Hence,
22
these CSRs are not initialized by a hardware reset and keep an *UNDEFINED* value until they are
23
explicitly initialized by the software (normally, this is already done by the NEORV32-specific
24
`crt0.S` start-up code). For more information see section <<_cpu_hardware_reset>>.
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26
**CSR Listing**
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28
The description of each single CSR provides the following summary:
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30
.CSR description
31
[cols="4,27,>7"]
32
[frame="topbot",grid="none"]
33
|======
34
| _Address_ | _Description_ | _ASM alias_
35
3+| Reset value: _CSR content after hardware reset_ (also see <<_cpu_hardware_reset>>)
36
3+| _Detailed description_
37
|======
38
 
39
.Not Implemented CSRs / CSR Bits
40
[IMPORTANT]
41
All CSR bits that are unused / not implemented / not shown are _hardwired to zero_. All CSRs that are not
42
implemented at all (and are not "disabled" using certain configuration generics) will trigger an exception on
43
access. The CSR that are implemented within the NEORV32 might cause an exception if they are disabled.
44
See the according CSR description for more information.
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46
.Debug Mode CSRs
47
[IMPORTANT]
48
The _debug mode_ CSRs are not listed here since they are only accessible in debug mode and not during normal CPU operation.
49
See section <<_cpu_debug_mode_csrs>>.
50
 
51
 
52
<<<
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// ####################################################################################################################
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**CSR Listing Notes**
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56
CSRs with the following notes ...
57
 
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* `X`: _custom_ - have or are a custom CPU-specific extension (that is allowed by the RISC-V specs)
59
* `R`: _read-only_ - are read-only (in contrast to the originally specified r/w capability)
60
* `C`: _constrained_ - have a constrained compatibility, not all specified bits are implemented
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62
.NEORV32 Control and Status Registers (CSRs)
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[cols="<4,<7,<10,^3,<11,^3"]
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[options="header"]
65
|=======================
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| Address | Name [ASM] | Name [C] | R/W | Function | Note
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6+^| **<<_floating_point_csrs>>**
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| 0x001   | <<_fflags>>     | _CSR_FFLAGS_     | r/w | Floating-point accrued exceptions |
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| 0x002   | <<_frm>>        | _CSR_FRM_        | r/w | Floating-point dynamic rounding mode |
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| 0x003   | <<_fcsr>>       | _CSR_FCSR_       | r/w | Floating-point control and status (`frm` + `fflags`) |
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6+^| **<<_machine_trap_setup>>**
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| 0x300   | <<_mstatus>>    | _CSR_MSTATUS_    | r/w | Machine status register - low word | `C`
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| 0x301   | <<_misa>>       | _CSR_MISA_       | r/- | Machine CPU ISA and extensions | `R`
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| 0x304   | <<_mie>>        | _CSR_MIE_        | r/w | Machine interrupt enable register | `X`
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| 0x305   | <<_mtvec>>      | _CSR_MTVEC_      | r/w | Machine trap-handler base address (for ALL traps) |
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| 0x306   | <<_mcounteren>> | _CSR_MCOUNTEREN_ | r/w | Machine counter-enable register | `C`
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| 0x310   | <<_mstatush>>   | _CSR_MSTATUSH_   | r/- | Machine status register - high word | `C`
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6+^| **<<_machine_trap_handling>>**
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| 0x340   | <<_mscratch>>   | _CSR_MSCRATCH_   | r/w | Machine scratch register |
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| 0x341   | <<_mepc>>       | _CSR_MEPC_       | r/w | Machine exception program counter |
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| 0x342   | <<_mcause>>     | _CSR_MCAUSE_     | r/w | Machine trap cause | `X`
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| 0x343   | <<_mtval>>      | _CSR_MTVAL_      | r/- | Machine bad address or instruction | `R`
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| 0x344   | <<_mip>>        | _CSR_MIP_        | r/- | Machine interrupt pending register | `XR`
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6+^| **<<_machine_physical_memory_protection>>**
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| 0x3a0 .. 0x3af | <<_pmpcfg, `pmpcfg0`>> .. <<_pmpcfg, `pmpcfg15`>>     | _CSR_PMPCFG0_ .. _CSR_PMPCFG15_   | r/w | Physical memory protection config. for region 0..63 | `C`
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| 0x3b0 .. 0x3ef | <<_pmpaddr, `pmpaddr0`>> .. <<_pmpaddr, `pmpaddr63`>> | _CSR_PMPADDR0_ .. _CSR_PMPADDR63_ | r/w | Physical memory protection addr. register region 0..63 |
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6+^| **<<_machine_counters_and_timers>>**
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| 0xb00   | <<_mcycleh, `mcycle`>>      | _CSR_MCYCLE_     | r/w | Machine cycle counter low word |
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| 0xb02   | <<_minstreth, `minstret`>> | _CSR_MINSTRET_   | r/w | Machine instruction-retired counter low word |
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| 0xb80   | <<_mcycleh>>                | _CSR_MCYCLE_     | r/w | Machine cycle counter high word |
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| 0xb82   | <<_minstreth>>              | _CSR_MINSTRET_   | r/w | Machine instruction-retired counter high word |
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| 0xc00   | <<_cycleh, `cycle`>>        | _CSR_CYCLE_      | r/- | Cycle counter low word |
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| 0xc01   | <<_timeh, `time`>>          | _CSR_TIME_       | r/- | System time (from MTIME) low word |
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| 0xc02   | <<_instreth, `instret`>>    | _CSR_INSTRET_    | r/- | Instruction-retired counter low word |
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| 0xc80   | <<_cycleh>>                 | _CSR_CYCLEH_     | r/- | Cycle counter high word |
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| 0xc81   | <<_timeh>>                  | _CSR_TIMEH_      | r/- | System time (from MTIME) high word |
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| 0xc82   | <<_instreth>>               | _CSR_INSTRETH_   | r/- | Instruction-retired counter high word |
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6+^| **<<_hardware_performance_monitors_hpm>>**
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| 0x323 .. 0x33f | <<_mhpmevent, `mhpmevent3`>> .. <<_mhpmevent, `mhpmevent31`>>             | _CSR_MHPMEVENT3_ .. _CSR_MHPMEVENT31_       | r/w | Machine performance-monitoring event selector 3..31 | `X`
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| 0xb03 .. 0xb1f | <<_mhpmcounterh, `mhpmcounter3`>> .. <<_mhpmcounterh, `mhpmcounter31`>>   | _CSR_MHPMCOUNTER3_ .. _CSR_MHPMCOUNTER31_   | r/w | Machine performance-monitoring counter 3..31 low word |
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| 0xb83 .. 0xb9f | <<_mhpmcounterh, `mhpmcounter3h`>> .. <<_mhpmcounterh, `mhpmcounter31h`>> | _CSR_MHPMCOUNTER3H_ .. _CSR_MHPMCOUNTER31H_ | r/w | Machine performance-monitoring counter 3..31 high word |
102
6+^| **<<_machine_counter_setup>>**
103
| 0x320   | <<_mcountinhibit>> | _CSR_MCOUNTINHIBIT_ | r/w | Machine counter-enable register |
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6+^| **<<_machine_information_registers>>**
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| 0xf11   | <<_mvendorid>>  | _CSR_MVENDORID_  | r/- | Vendor ID |
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| 0xf12   | <<_marchid>>    | _CSR_MARCHID_    | r/- | Architecture ID |
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| 0xf13   | <<_mimpid>>     | _CSR_MIMPID_     | r/- | Machine implementation ID / version |
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| 0xf14   | <<_mhartid>>    | _CSR_MHARTID_    | r/- | Machine thread ID |
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| 0xf15   | <<_mconfigptr>> | _CSR_MCONFIGPTR_ | r/- | Machine configuration pointer register |
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|=======================
111
 
112
 
113
 
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<<<
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// ####################################################################################################################
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:sectnums:
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==== Floating-Point CSRs
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119
These CSRs are available if the `Zfinx` extensions is enabled (`CPU_EXTENSION_RISCV_Zfinx` is _true_).
120
Otherwise any access to the floating-point CSRs will raise an illegal instruction exception.
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122
 
123
:sectnums!:
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===== **`fflags`**
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126
[cols="4,27,>7"]
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[frame="topbot",grid="none"]
128
|======
129
| 0x001 | **Floating-point accrued exceptions** | `fflags`
130
3+| Reset value: _UNDEFINED_
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3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
132
exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
133
See the RISC-V ISA spec for more information.
134
|======
135
 
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:sectnums!:
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===== **`frm`**
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140
[cols="4,27,>7"]
141
[frame="topbot",grid="none"]
142
|======
143
| 0x002 | **Floating-point dynamic rounding mode** | `frm`
144
3+| Reset value: _UNDEFINED_
145
3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
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the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
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ISA spec for more information.
148
|======
149
 
150
 
151
:sectnums!:
152
===== **`fcsr`**
153
 
154
[cols="4,27,>7"]
155
[frame="topbot",grid="none"]
156
|======
157
| 0x003 | **Floating-point control and status register** | `fcsr`
158
3+| Reset value: _UNDEFINED_
159
3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
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`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
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RISC-V ISA spec for more information.
162
|======
163
 
164
 
165
<<<
166
// ####################################################################################################################
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:sectnums:
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==== Machine Trap Setup
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:sectnums!:
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===== **`mstatus`**
172
 
173
[cols="4,27,>7"]
174
[frame="topbot",grid="none"]
175
|======
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| 0x300 | **Machine status register** | `mstatus`
177
3+| Reset value: _0x00000000_
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3+| The `mstatus` CSR is compatible to the RISC-V specifications. It shows the CPU's current execution state.
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The following bits are implemented (all remaining bits are always zero and are read-only).
180
|======
181
 
182
.Machine status register
183
[cols="^1,<3,^1,<5"]
184
[options="header",grid="rows"]
185
|=======================
186
| Bit   | Name [C] | R/W | Function
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| 31    | _CSR_MSTATUS_SD_ | r/- | Read-only bit that is set if the FS field is not all-zero (state _OFF_)
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| 21    | _CSR_MSTATUS_TW_ | r/w | Timeout wait: raise illegal instruction exception if `WFI` instruction is executed outside of M-mode when set
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| 12:11 | _CSR_MSTATUS_MPP_H_ : _CSR_MSTATUS_MPP_L_ | r/w | Previous machine privilege level, 11 = machine (M) level, 00 = user (U) level
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| 7     | _CSR_MSTATUS_MPIE_ | r/w | Previous machine global interrupt enable flag state
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| 3     | _CSR_MSTATUS_MIE_  | r/w | Machine global interrupt enable flag
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|=======================
193
 
194
When entering an exception/interrupt, the `MIE` flag is copied to `MPIE` and cleared afterwards. When leaving
195
the exception/interrupt (via the `mret` instruction), `MPIE` is copied back to `MIE`.
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197
 
198
:sectnums!:
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===== **`misa`**
200
 
201
[cols="4,27,>7"]
202
[frame="topbot",grid="none"]
203
|======
204
| 0x301 | **ISA and extensions** | `misa`
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3+| Reset value: _configuration dependant_
206
3+| The `misa` CSR gives information about the actual CPU features. The lowest 26 bits show the implemented
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CPU extensions. The following bits are implemented (all remaining bits are always zero and are read-only).
208
|======
209
 
210
[IMPORTANT]
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The `misa` CSR is not fully RISC-V-compatible as it is read-only. Hence, implemented CPU
212
extensions cannot be switch on/off during runtime. For compatibility reasons any write access to this
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CSR is simply ignored and will NOT cause an illegal instruction exception.
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215
.Machine ISA and extension register
216
[cols="^1,<3,^1,<5"]
217
[options="header",grid="rows"]
218
|=======================
219
| Bit   | Name [C] | R/W | Function
220
| 31:30 | _CSR_MISA_MXL_HI_EXT_ : _CSR_MISA_MXL_LO_EXT_ | r/- | 32-bit architecture indicator (always _01_)
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| 23    | _CSR_MISA_X_EXT_ | r/- | `X` extension bit is always set to indicate custom non-standard extensions
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| 20    | _CSR_MISA_U_EXT_ | r/- | `U` CPU extension (user mode) available, set when _CPU_EXTENSION_RISCV_U_ enabled
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| 12    | _CSR_MISA_M_EXT_ | r/- | `M` CPU extension (mul/div) available, set when _CPU_EXTENSION_RISCV_M_ enabled
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| 8     | _CSR_MISA_I_EXT_ | r/- | `I` CPU base ISA, cleared when _CPU_EXTENSION_RISCV_E_ enabled
225
| 4     | _CSR_MISA_E_EXT_ | r/- | `E` CPU extension (embedded) available, set when _CPU_EXTENSION_RISCV_E_ enabled
226
| 2     | _CSR_MISA_C_EXT_ | r/- | `C` CPU extension (compressed instruction) available, set when _CPU_EXTENSION_RISCV_C_ enabled
227
| 0     | _CSR_MISA_A_EXT_ | r/- | `A` CPU extension (atomic memory access) available, set when _CPU_EXTENSION_RISCV_A_ enabled
228
|=======================
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230
[TIP]
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Information regarding the implemented RISC-V `Z*` _sub-extensions_ (like `Zicsr` or `Zfinx`) can be found
232
in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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234
 
235
:sectnums!:
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===== **`mie`**
237
 
238
[cols="4,27,>7"]
239
[frame="topbot",grid="none"]
240
|======
241
| 0x304 | **Machine interrupt-enable register** | `mie`
242
3+| Reset value: _UNDEFINED_
243
3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
244
interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
245
globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
246
(all remaining bits are always zero and are read-only):
247
|======
248
 
249
.Machine ISA and extension register
250
[cols="^1,<3,^1,<5"]
251
[options="header",grid="rows"]
252
|=======================
253
| Bit   | Name [C] | R/W | Function
254
| 31:16 | _CSR_MIE_FIRQ15E_ : _CSR_MIE_FIRQ0E_ | r/w | Fast interrupt channel 15..0 enable
255
| 11    | _CSR_MIE_MEIE_ | r/w | Machine _external_ interrupt enable
256
| 7     | _CSR_MIE_MTIE_ | r/w | Machine _timer_ interrupt enable (from _MTIME_)
257
| 3     | _CSR_MIE_MSIE_ | r/w | Machine _software_ interrupt enable
258
|=======================
259
 
260
 
261
:sectnums!:
262
===== **`mtvec`**
263
 
264
[cols="4,27,>7"]
265
[frame="topbot",grid="none"]
266
|======
267
| 0x305 | **Machine trap-handler base address** | `mtvec`
268
3+| Reset value: _UNDEFINED_
269
3+| The `mtvec` CSR is compatible to the RISC-V specifications. It stores the base address for ALL machine
270
traps. Thus, it defines the main entry point for exception/interrupt handling regardless of the actual trap
271
source. The lowest two bits of this register are always zero and cannot be modified (= fixed address mode).
272
|======
273
 
274
.Machine trap-handler base address
275
[cols="^1,^1,<8"]
276
[options="header",grid="rows"]
277
|=======================
278
| Bit  | R/W | Function
279
| 31:2 | r/w | 4-byte aligned base address of trap base handler
280
| 1:0  | r/- | Always zero
281
|=======================
282
 
283
 
284
:sectnums!:
285
===== **`mcounteren`**
286
 
287
[cols="4,27,>7"]
288
[frame="topbot",grid="none"]
289
|======
290
| 0x306 | **Machine counter enable** | `mcounteren`
291
3+| Reset value: _UNDEFINED_
292
3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
293
counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
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if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
295
exception is raised. If user mode in not implemented (_CPU_EXTENSION_RISCV_U_ = _false_) all bits of the
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`mcounteren` CSR are tied to zero.
297
|======
298
 
299
.Machine counter enable register
300
[cols="^1,<3,^1,<5"]
301
[options="header",grid="rows"]
302
|=======================
303
| Bit   | Name [C] | R/W | Function
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| 31:16 | `0`                 | r/- | Always zero: user-level code is **not** allowed to read HPM counters
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| 2     | _CSR_MCOUNTEREN_IR_ | r/w | User-level code is allowed to read `cycle[h]` CSRs when set
306
| 1     | _CSR_MCOUNTEREN_TM_ | r/w | User-level code is allowed to read `time[h]` CSRs when set
307
| 0     | _CSR_MCOUNTEREN_CY_ | r/w | User-level code is allowed to read `instret[h]` CSRs when set
308
|=======================
309
 
310
 
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:sectnums!:
312
===== **`mstatush`**
313
 
314
[cols="4,27,>7"]
315
[frame="topbot",grid="none"]
316
|======
317
| 0x310 | **Machine status register - high word** | `mstatush`
318
3+| Reset value: _0x00000000_
319
3+| The `mstatush` CSR is compatible to the RISC-V specifications. In combination with <<_mstatus>> it shows additional
320
execution state information. The NEORV32 `mstatush` CSR is read-only and all bits are hardwired to zero.
321
|======
322
 
323
[NOTE]
324
The NEORV32 `mstatush` CSR is not a physical register. All write access are ignored and all read accesses will always
325
return zero. However, any access will not raise an illegal instruction exception. The CSR address is implemented
326
in order to comply with the RISC-V privilege architecture specs.
327
 
328
 
329
 
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<<<
331
// ####################################################################################################################
332
:sectnums:
333
==== Machine Trap Handling
334
 
335
:sectnums!:
336
===== **`mscratch`**
337
 
338
[cols="4,27,>7"]
339
[frame="topbot",grid="none"]
340
|======
341
| 0x340 | **Scratch register for machine trap handlers** | `mscratch`
342
3+| Reset value: _UNDEFINED_
343
3+| The `mscratch` CSR is compatible to the RISC-V specifications. It is a general purpose scratch register that
344
can be used by the exception/interrupt handler. The content pf this register after reset is undefined.
345
|======
346
 
347
:sectnums!:
348
===== **`mepc`**
349
 
350
[cols="4,27,>7"]
351
[frame="topbot",grid="none"]
352
|======
353
| 0x341 | **Machine exception program counter** | `mepc`
354
3+| Reset value: _UNDEFINED_
355
3+| The `mepc` CSR is compatible to the RISC-V specifications. For exceptions (like an illegal instruction) this
356
register provides the address of the exception-causing instruction. For Interrupt (like a machine timer
357
interrupt) this register provides the address of the next not-yet-executed instruction.
358
|======
359
 
360
:sectnums!:
361
===== **`mcause`**
362
 
363
[cols="4,27,>7"]
364
[frame="topbot",grid="none"]
365
|======
366
| 0x342 | **Machine trap cause** | `mcause`
367
3+| Reset value: _UNDEFINED_
368
3+| The `mcause` CSR is compatible to the RISC-V specifications. It show the cause ID for a taken exception.
369
|======
370
 
371
.Machine trap cause register
372
[cols="^1,^1,<8"]
373
[options="header",grid="rows"]
374
|=======================
375
| Bit  | R/W | Function
376
| 31   | r/w | `1` if the trap is caused by an interrupt (`0` if the trap is caused by an exception)
377
| 30:5 | r/- | _Reserved_, read as zero
378
| 4:0  | r/w | Trap ID, see <<_neorv32_trap_listing>>
379
|=======================
380
 
381
:sectnums!:
382
===== **`mtval`**
383
 
384
[cols="4,27,>7"]
385
[frame="topbot",grid="none"]
386
|======
387
| 0x343 | **Machine bad address or instruction** | `mtval`
388
3+| Reset value: _UNDEFINED_
389
3+| The `mtval` CSR is compatible to the RISC-V specifications. When a trap is triggered, the CSR shows either
390
the faulting address (for misaligned/faulting load/stores/fetch) or the faulting instruction itself (for illegal
391
instructions). For interrupts the CSR is set to zero.
392
|======
393
 
394
.Machine bad address or instruction register
395
[cols="^5,^5"]
396
[options="header",grid="rows"]
397
|=======================
398
| Trap cause | `mtval` content
399
| misaligned instruction fetch address or instruction fetch access fault | address of faulting instruction fetch
400
| breakpoint | program counter (= address) of faulting instruction itself
401
| misaligned load address, load access fault, misaligned store address or store access fault | program counter (= address) of faulting instruction itself
402
| illegal instruction | actual instruction word of faulting instruction
403
| anything else including interrupts | _0x00000000_ (always zero)
404
|=======================
405
 
406
[IMPORTAN]
407
The NEORV32 `mtval` CSR is read-only. A write access will raise an illegal instruction exception.
408
 
409
:sectnums!:
410
===== **`mip`**
411
 
412
[cols="4,27,>7"]
413
[frame="topbot",grid="none"]
414
|======
415
| 0x344 | **Machine interrupt Pending** | `mip`
416
3+| Reset value: _0x00000000_
417
3+| The `mip` CSR is _partly_ compatible to the RISC-V specifications and also provides custom extensions. It shows currently pending interrupts. Since this register is
418
read-only, pending interrupt can only be cleared by disabling and re-enabling the according `mie` CSr bit. Writing to this CSR will
419
raise an illegal instruction exception. The following CSR bits are implemented (all remaining bits are always zero and are read-only).
420
|======
421
 
422
.Machine interrupt pending register
423
[cols="^1,<3,^1,<5"]
424
[options="header",grid="rows"]
425
|=======================
426
| Bit | Name [C] | R/W | Function
427
| 31:16 | _CSR_MIP_FIRQ15P_ : _CSR_MIP_FIRQ0P_ | r/- | fast interrupt channel 15..0 pending
428
| 11    | _CSR_MIP_MEIP_ | r/- | machine _external_ interrupt pending
429
| 7     | _CSR_MIP_MTIP_ | r/- | machine _timer_ interrupt pending
430
| 3     | _CSR_MIP_MSIP_ | r/- | machine _software_ interrupt pending
431
|=======================
432
 
433
 
434
<<<
435
// ####################################################################################################################
436
:sectnums:
437
==== Machine Physical Memory Protection
438
 
439
The available physical memory protection logic is configured via the _PMP_NUM_REGIONS_ and
440
_PMP_MIN_GRANULARITY_ top entity generics. _PMP_NUM_REGIONS_ defines the number of implemented
441
protection regions and thus, the availability of the according `pmpcfg*` and `pmpaddr*` CSRs.
442
 
443
[TIP]
444
If trying to access an PMP-related CSR beyond _PMP_NUM_REGIONS_ **no illegal instruction
445
exception** is triggered. The according CSRs are read-only (writes are ignored) and always return zero.
446
 
447
[IMPORTANT]
448
The RISC-V-compatible NEORV32 physical memory protection only implements the _NAPOT_
449
(naturally aligned power-of-two region) mode with a minimal region granularity of 8 bytes.
450
 
451
 
452
:sectnums!:
453
===== **`pmpcfg`**
454
 
455
[cols="4,27,>7"]
456
[frame="topbot",grid="none"]
457
|======
458
| 0x3a0 - 0x3af| **Physical memory protection configuration registers** | `pmpcfg0` - `pmpcfg15`
459
3+| Reset value: _0x00000000_
460
3+| The `pmpcfg*` CSRs are compatible to the RISC-V specifications. They are used to configure the protected
461
regions, where each `pmpcfg*` CSR provides configuration bits for four regions. The following bits (for the
462
first PMP configuration entry) are implemented (all remaining bits are always zero and are read-only):
463
|======
464
 
465
.Physical memory protection configuration register entry
466
[cols="^1,^3,^1,<11"]
467
[options="header",grid="rows"]
468
|=======================
469
| Bit | RISC-V name | R/W | Function
470
| 7   | _L_ | r/w | lock bit, can be set – but not be cleared again (only via CPU reset)
471
| 6:5 | -   | r/- | reserved, read as zero
472
| 4:3 | _A_ | r/w | mode configuration; only OFF (`00`) and NAPOT (`11`) are supported
473
| 2   | _X_ | r/w | execute permission
474
| 1   | _W_ | r/w | write permission
475
| 0   | _R_ | r/w | read permission
476
|=======================
477
 
478
 
479
:sectnums!:
480
===== **`pmpaddr`**
481
 
482
[cols="4,27,>7"]
483
[frame="topbot",grid="none"]
484
|======
485
| 0x3b0 - 0x3ef| **Physical memory protection configuration registers** | `pmpaddr0` - `pmpaddr63`
486
3+| Reset value: _UNDEFINED_
487
3+| The `pmpaddr*` CSRs are compatible to the RISC-V specifications. They are used to configure the base
488
address and the region size.
489
|======
490
 
491
[NOTE]
492
When configuring PMP make sure to set `pmpaddr*` before activating the according region via
493
`pmpcfg*`. When changing the PMP configuration, deactivate the according region via `pmpcfg*`
494
before modifying `pmpaddr*`.
495
 
496
 
497
<<<
498
// ####################################################################################################################
499
:sectnums:
500
==== (Machine) Counters and Timers
501
 
502
[IMPORTANT]
503 61 zero_gravi
The <<_cpu_cnt_width>> generic defines the total size of the CPU's <<_cycleh>> and <<_instreth>>
504
/ <<_mcycleh>> and <<_minstreth>>
505 60 zero_gravi
counter CSRs (low and high words combined); the time CSRs are not affected by this generic. Any
506 61 zero_gravi
configuration with <<_cpu_cnt_width>> less than 64 is not RISC-V compliant.
507 60 zero_gravi
 
508
[IMPORTANT]
509
If _CPU_CNT_WIDTH_ is less than 64 (the default value) and greater than or equal 32, the according
510
MSBs of `[m]cycleh` and `[m]instreth` are read-only and always read as zero. This configuration
511 63 zero_gravi
will also set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
512 61 zero_gravi
 +
513 60 zero_gravi
If _CPU_CNT_WIDTH_ is less than 32 and greater than 0, the `[m]cycleh` and `[m]instreth` do not
514
exist and any access will raise an illegal instruction exception. Furthermore, the according MSBs of
515
`[m]cycle` and `[m]instret` are read-only and always read as zero. This configuration will also
516 63 zero_gravi
set the _SYSINFO_CPU_ZXSCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register. +
517 61 zero_gravi
 +
518
If _CPU_CNT_WIDTH_ is 0, <<_cycleh>> and <<_instreth>> / <<_mcycleh>> and <<_minstreth>> do not
519 60 zero_gravi
exist and any access will raise an illegal instruction exception. This configuration will also set the
520 63 zero_gravi
_SYSINFO_CPU_ZXNOCNT_ flag in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
521 60 zero_gravi
 
522
 
523
:sectnums!:
524
===== **`cycle[h]`**
525
 
526
[cols="4,27,>7"]
527
[frame="topbot",grid="none"]
528
|======
529
| 0xc00 | **Cycle counter - low word** | `cycle`
530
| 0xc80 | **Cycle counter - high word** | `cycleh`
531
3+| Reset value: _UNDEFINED_
532
3+| The `cycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
533
counter. The `cycle[h]` CSR is a read-only shadowed copy of the `mcycle[h]` CSR.
534
|======
535
 
536
 
537
:sectnums!:
538
===== **`time[h]`**
539
 
540
[cols="4,27,>7"]
541
[frame="topbot",grid="none"]
542
|======
543
| 0xc01 | **System time - low word** | `time`
544
| 0xc81 | **System time - high word** | `timeh`
545
3+| Reset value: _UNDEFINED_
546
3+| The `time[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit system
547
time. The system time is either generated by the processor-internal _MTIME_ system timer unit (if _IO_MTIME_EN_ = _true_) or can be provided by an
548
external timer unit via the processor's `mtime_i` signal (if _IO_MTIME_EN_ = _false_).
549
CSR is read-only. Change the system time via the _MTIME_ unit.
550
|======
551
 
552
 
553
:sectnums!:
554
===== **`instret[h]`**
555
 
556
[cols="4,27,>7"]
557
[frame="topbot",grid="none"]
558
|======
559
| 0xc02 | **Instructions-retired counter - low word** | `instret`
560
| 0xc82 | **Instructions-retired counter - high word** | `instreth`
561
3+| Reset value: _UNDEFINED_
562
3+| The `instret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
563
instructions counter. The `instret[h]` CSR is a read-only shadowed copy of the `minstret[h]` CSR.
564
|======
565
 
566
 
567
:sectnums!:
568
===== **`mcycle[h]`**
569
 
570
[cols="4,27,>7"]
571
[frame="topbot",grid="none"]
572
|======
573
| 0xb00 | **Machine cycle counter - low word** | `mcycle`
574
| 0xb80 | **Machine cycle counter - high word** | `mcycleh`
575
3+| Reset value: _UNDEFINED_
576
3+| The `mcycle[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit cycle
577
counter. The `mcycle[h]` CSR can also be written when in machine mode and is copied to the `cycle[h]` CSR.
578
|======
579
 
580
 
581
:sectnums!:
582
===== **`minstret[h]`**
583
 
584
[cols="4,27,>7"]
585
[frame="topbot",grid="none"]
586
|======
587
| 0xb02 | **Machine instructions-retired counter - low word** | `minstret`
588
| 0xb82 | **Machine instructions-retired counter - high word** | `minstreth`
589
3+| Reset value: _UNDEFINED_
590
3+| The `minstret[h]` CSR is compatible to the RISC-V specifications. It shows the lower/upper 32-bit of the 64-bit retired
591
instructions counter. The `minstret[h]` CSR also be written when in machine mode and is copied to the `instret[h]` CSR.
592
|======
593
 
594
 
595
 
596
<<<
597
// ####################################################################################################################
598
:sectnums:
599
==== Hardware Performance Monitors (HPM)
600
 
601 61 zero_gravi
The available hardware performance logic is configured via the <<_hpm_num_cnts>> top entity generic,
602
which defines the number of implemented performance monitors and thus, the availability of the
603
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
604 60 zero_gravi
 
605 61 zero_gravi
[IMPORTANT]
606
The HPM system only implements machine-mode access. Hence, `hpmcounter*[h]` CSR are not implemented
607
and any access (even) from machine mode will raise an exception. Furthermore, the according bits of <<_mcounteren>>
608
used to configure user-mode access to `hpmcounter*[h]` are hard-wired to zero.
609 60 zero_gravi
 
610 61 zero_gravi
The total counter size of the HPMs can be configured before synthesis via the <<_hpm_cnt_width>> generic (0..64-bit).
611
 
612 60 zero_gravi
[TIP]
613 61 zero_gravi
If trying to access an HPM-related CSR beyond <<_hpm_num_cnts>> **no illegal instruction exception is
614 60 zero_gravi
triggered**. The according CSRs are read-only (writes are ignored) and always return zero.
615
 
616
[NOTE]
617
The total LSB-aligned HPM counter size (low word CSR + high word CSR) is defined via the
618 61 zero_gravi
<<_hpm_num_cnts>> generic (0..64-bit). If <<_hpm_num_cnts>> is less than 64, all unused MSB-aligned
619 60 zero_gravi
bits are hardwired to zero.
620
 
621
 
622
:sectnums!:
623
===== **`mhpmevent`**
624
 
625
[cols="4,27,>7"]
626
[frame="topbot",grid="none"]
627
|======
628
| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
629
3+| Reset value: _UNDEFINED_
630
3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The configuration of these CSR define
631 62 zero_gravi
the architectural events that cause the according `mhpmcounter*[h]` counters to increment. All available events are
632 60 zero_gravi
listed in the table below. If more than one event is selected, the according counter will increment if any of
633
the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
634
cycle even if more than one event is observed. If the CPU is in sleep mode, no HPM counter will increment
635
at all.
636
|======
637
 
638
The available hardware performance logic is configured via the _HPM_NUM_CNTS_ top entity generic.
639
_HPM_NUM_CNTS_ defines the number of implemented performance monitors and thus, the availability of the
640 62 zero_gravi
according `mhpmcounter*[h]` and `mhpmevent*` CSRs.
641 60 zero_gravi
 
642
.HPM event selector
643
[cols="^1,<3,^1,<5"]
644
[options="header",grid="rows"]
645
|=======================
646 61 zero_gravi
| Bit | Name [C]               | R/W | Event
647
| 0   | _HPMCNT_EVENT_CY_      | r/w | active clock cycle (not in sleep)
648
| 1   | -                      | r/- | _not implemented, always read as zero_
649
| 2   | _HPMCNT_EVENT_IR_      | r/w | retired instruction
650
| 3   | _HPMCNT_EVENT_CIR_     | r/w | retired compressed instruction
651 60 zero_gravi
| 4   | _HPMCNT_EVENT_WAIT_IF_ | r/w | instruction fetch memory wait cycle (if more than 1 cycle memory latency)
652
| 5   | _HPMCNT_EVENT_WAIT_II_ | r/w | instruction issue pipeline wait cycle (if more than 1 cycle latency), caused by pipelines flushes (like taken branches)
653
| 6   | _HPMCNT_EVENT_WAIT_MC_ | r/w | multi-cycle ALU operation wait cycle
654 61 zero_gravi
| 7   | _HPMCNT_EVENT_LOAD_    | r/w | load operation
655
| 8   | _HPMCNT_EVENT_STORE_   | r/w | store operation
656 60 zero_gravi
| 9   | _HPMCNT_EVENT_WAIT_LS_ | r/w | load/store memory wait cycle (if more than 1 cycle memory latency)
657 61 zero_gravi
| 10  | _HPMCNT_EVENT_JUMP_    | r/w | unconditional jump
658
| 11  | _HPMCNT_EVENT_BRANCH_  | r/w | conditional branch (taken or not taken)
659 60 zero_gravi
| 12  | _HPMCNT_EVENT_TBRANCH_ | r/w | taken conditional branch
660 61 zero_gravi
| 13  | _HPMCNT_EVENT_TRAP_    | r/w | entered trap
661 60 zero_gravi
| 14  | _HPMCNT_EVENT_ILLEGAL_ | r/w | illegal instruction exception
662
|=======================
663
 
664
 
665
:sectnums!:
666
===== **`mhpmcounter[h]`**
667
 
668
[cols="4,27,>7"]
669
[frame="topbot",grid="none"]
670
|======
671
| 0xb03 - 0xb1f | **Machine hardware performance monitor - counter low** | `mhpmcounter3` - `mhpmcounter31`
672
| 0xb83 - 0xb9f | **Machine hardware performance monitor - counter high** | `mhpmcounter3h` - `mhpmcounter31h`
673
3+| Reset value: _UNDEFINED_
674
3+| The `mhpmcounter*[h]` CSRs are compatible to the RISC-V specifications. These CSRs provide the lower/upper 32-
675 61 zero_gravi
bit of arbitrary event counters. The event(s) that trigger an increment of theses counters are selected via the according
676
`mhpmevent*` CSRs bits.
677 60 zero_gravi
|======
678
 
679
 
680
<<<
681
// ####################################################################################################################
682
:sectnums:
683
==== Machine Counter Setup
684
 
685
:sectnums!:
686
===== **`mcountinhibit`**
687
 
688
[cols="4,27,>7"]
689
[frame="topbot",grid="none"]
690
|======
691
| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
692
3+| Reset value: _UNDEFINED_
693
3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
694
counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
695
according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are
696
always zero and are read-only).
697
|======
698
 
699
.Machine counter-inhibit register
700
[cols="^1,<3,^1,<5"]
701
[options="header",grid="rows"]
702
|=======================
703
| Bit  | Name [C] | R/W | Event
704
| 0    | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]instret[h]` CSRs will auto-increment with each committed instruction when set
705
| 2    | _CSR_MCOUNTINHIBIT_IR_ | r/w | the `[m]cycle[h]` CSRs will auto-increment with each clock cycle (if CPU is not in sleep state) when set
706 62 zero_gravi
| 3:31 | _CSR_MCOUNTINHIBIT_HPM3_ _: _CSR_MCOUNTINHIBIT_HPM31_ | r/w | the `mhpmcount*[h]` CSRs will auto-increment according to the configured `mhpmevent*` selector
707 60 zero_gravi
|=======================
708
 
709
 
710
<<<
711
// ####################################################################################################################
712
:sectnums:
713
==== Machine Information Registers
714
 
715 62 zero_gravi
[NOTE]
716
All machine information registers can only be accessed in machine mode and are read-only.
717 60 zero_gravi
 
718
:sectnums!:
719
===== **`mvendorid`**
720
 
721
[cols="4,27,>7"]
722
[frame="topbot",grid="none"]
723
|======
724
| 0xf11 | **Machine vendor ID** | `mvendorid`
725
3+| Reset value: _0x00000000_
726
3+| The `mvendorid` CSR is compatible to the RISC-V specifications. It is read-only and always reads zero.
727
|======
728
 
729
 
730
:sectnums!:
731
===== **`marchid`**
732
 
733
[cols="4,27,>7"]
734
[frame="topbot",grid="none"]
735
|======
736
| 0xf12 | **Machine architecture ID** | `marchid`
737
3+| Reset value: _0x00000013_
738
3+| The `marchid` CSR is compatible to the RISC-V specifications. It is read-only and shows the NEORV32
739
official _RISC-V open-source architecture ID_ (decimal: 19, 32-bit hexadecimal: 0x00000013).
740
|======
741
 
742
 
743
:sectnums!:
744
===== **`mimpid`**
745
 
746
[cols="4,27,>7"]
747
[frame="topbot",grid="none"]
748
|======
749
| 0xf13 | **Machine implementation ID** | `mimpid`
750
3+| Reset value: _HW version number_
751
3+| The `mimpid` CSR is compatible to the RISC-V specifications. It is read-only and shows the version of the
752
NEORV32 as BCD-coded number (example: `mimpid` = _0x01020312_ → 01.02.03.12 → version 1.2.3.12).
753
|======
754
 
755
 
756
:sectnums!:
757
===== **`mhartid`**
758
 
759
[cols="4,27,>7"]
760
[frame="topbot",grid="none"]
761
|======
762
| 0xf14 | **Machine hardware thread ID** | `mhartid`
763
3+| Reset value: _HW_THREAD_ID_ generic
764
3+| The `mhartid` CSR is compatible to the RISC-V specifications. It is read-only and shows the core's hart ID,
765
which is assigned via the CPU's _HW_THREAD_ID_ generic.
766
|======
767
 
768
 
769 62 zero_gravi
:sectnums!:
770
===== **`mconfigptr`**
771 60 zero_gravi
 
772 62 zero_gravi
[cols="4,27,>7"]
773
[frame="topbot",grid="none"]
774
|======
775
| 0xf15 | **Machine configuration pointer register** | `mconfigptr`
776
3+| Reset value: `0x00000000`
777
3+| This register holds a physical address (if not zero) that points to the base address of an architecture configuration structure.
778
Software can traverse this data structure to discover information about the harts, the platform, and their configuration.
779
**NOTE: Not assigned yet.**
780
|======

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