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= The NEORV32 RISC-V Processor: Datasheet
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:author: Dipl.-Ing. Stephan Nolting
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:email: stnolting@gmail.com
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:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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:revnumber: v1.5.6.0
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:doctype: book
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:sectnums:
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:icons: image
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:iconsdir: ../icons
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:imagesdir: ../figures
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:stem:
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:reproducible:
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:listing-caption: Listing
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:toc: macro
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:toclevels: 4
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:title-logo-image: image:neorv32_logo_dark.png[pdfwidth=6.25in,align=center]
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// Uncomment next line to set page size (default is A4)
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//:pdf-page-size: Letter
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<<<
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// ####################################################################################################################
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.**Documentation**
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[TIP]
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The online documentation of the project (a.k.a. the **data sheet**) is available on GitHub-pages: https://stnolting.github.io/neorv32/ +
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The online documentation of the **software framework** is also available on GitHub-pages: https://stnolting.github.io/neorv32/sw/files.html
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<<<
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// ####################################################################################################################
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toc::[]
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include::content.adoc[]
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