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:sectnums:
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== Overview
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The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source
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RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom / customizable microcontroller.
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The system is highly configurable and provides optional common peripherals like embedded memories,
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timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like
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memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
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compatible on-chip debugger accessible via JTAG.
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The software framework of the processor comes with application makefiles, software libraries for all CPU
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and processor features, a bootloader, a runtime environment and several example programs – including a port
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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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[TIP]
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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that provides hands-on tutorial to get you started.
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[TIP]
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The project's change log is available in https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md[CHANGELOG.md]
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in the root directory of the NEORV32 repository. Please also check out the <<_legal>> section.
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**Structure**
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* <<_neorv32_processor_soc>>
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* <<_neorv32_central_processing_unit_cpu>>
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* <<_on_chip_debugger_ocd>>
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* <<_software_framework>>
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[TIP]
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Links in this document are <<_overview,highlighted>>.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Rationale
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**Why did you make this?**
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I am fascinated by processor and CPU architecture design: it is the magic frontier where software meets hardware.
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This project has started as something like a _journey_ into this magic realm to understand how things actually work
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down on this very low level.
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But there is more! When I started to dive into the emerging RISC-V ecosystem I felt overwhelmed by the complexity.
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As a beginner it is hard to get an overview - especially when you want to setup a minimal platform to tinker with:
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Which core to use? How to get the right toolchain? What features do I need? How does the booting work? How do I
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create an actual executable? How to get that into the hardware? How to customize things? **_Where to start???_**
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So this project aims to provides a _simple to understand_ and _easy to use_ yet _powerful_ and _flexible_ platform
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that targets FPGA and RISC-V beginners as well as advanced users. Join me and us on this journey! 🙃
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**Why a _soft_-core processor?**
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As a matter of fact soft-core processors _cannot_ compete with discrete or FPGA hard-macro processors in terms
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of performance, energy and size. But they do fill a niche in FPGA design space. For example, soft-core processors
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allow to implement the _control flow part_ of certain applications (like communication protocol handling) using
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software like plain C. This provides high flexibility as software can be easily changed, re-compiled and
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re-uploaded again.
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Furthermore, the concept of flexibility applies to all aspects of a soft-core processor. The user can add
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_exactly_ the features that are required by the application: additional memories, custom interfaces, specialized
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IP and even user-defined instructions.
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**Why RISC-V?**
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[quote, RISC-V International, https://riscv.org/about/]
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____
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RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.
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____
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I love the idea of open-source. **Knowledge can help best if it is freely available.**
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While open-source has already become quite popular in _software_, hardware projects still need to catch up.
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Admittedly, there has been quite a development, but mainly in terms of _platforms_ and _applications_ (so
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schematics, PCBs, etc.). Although processors and CPUs are the heart of almost every digital system, having a true
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open-source silicon is still a rarity. RISC-V aims to change that. Even it is _just one approach_, it helps paving
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the road for future development.
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Furthermore, I welcome the community aspect of RISC-V. The ISA and everything beyond is developed with direct
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contact to the community: this includes businesses and professionals but also hobbyist, amateurs and people
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that are just curious. Everyone can join discussions and contribute to RISC-V in their very own way.
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Finally, I really like the RISC-V ISA itself. It aims to be a clean, orthogonal and "intuitive" ISA that
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resembles with the basic concepts of _RISC_: simple yet effective.
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**Yet another RISC-V core? What makes it special?**
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The NEORV32 is not based on another RISC-V core. It was build entirely from ground up (just following the official
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ISA specs) having a different design goal in mind. The project does not intend to replace certain RISC-V cores or
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just beat existing ones like https://github.com/SpinalHDL/VexRiscv[VexRISC] in terms of performance or
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https://github.com/olofk/serv[SERV] in terms of size.
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
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// ####################################################################################################################
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:sectnums:
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=== Project Key Features
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* open-source and documented; including user guides to get started
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* completely described in behavioral, platform-independent VHDL (yet platform-optimized modules are provided)
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* fully synchronous design, no latches, no gated clocks
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* small hardware footprint and high operating frequency for easy integration
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* **NEORV32 CPU**: 32-bit `rv32i` RISC-V CPU
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** RISC-V compatibility: passes the official architecture tests
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** base architecture + privileged architecture (optional) + ISA extensions (optional)
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** rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
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** aims to support <<_full_virtualization>> capabilities (CPU _and_ SoC) to increase execution safety
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** official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]
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* **NEORV32 Processor (SoC)**: highly-configurable full-scale microcontroller-like processor system
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** based on the NEORV32 CPU
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** optional serial interfaces (UARTs, TWI, SPI)
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** optional timers and counters (WDT, MTIME)
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** optional general purpose IO and PWM and native NeoPixel (c) compatible smart LED interface
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** optional embedded memories / caches for data, instructions and bootloader
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** optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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** on-chip debugger compatible with OpenOCD and gdb
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* **Software framework**
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** GCC-based toolchain - prebuilt toolchains available; application compilation based on GNU makefiles
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** internal bootloader with serial user interface
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** core libraries for high-level usage of the provided functions and peripherals
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** runtime environment and several example programs
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** doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
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** FreeRTOS port + demos available
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[TIP]
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For more in-depth details regarding the feature provided by he hardware see the according sections:
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<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Project Folder Structure
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...................................
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neorv32                - Project home folder
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├docs                  - Project documentation
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│├datasheet            - .adoc sources for NEORV32 data sheet
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│├doxygen_build        - Software framework documentation (generated by doxygen)
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│├figures              - Figures and logos
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│├icons                - Misc. symbols
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│├references           - Data sheets and RISC-V specs.
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│└src_adoc             - AsciiDoc sources for this document
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├rtl                   - VHDL sources
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│├core                 - Core sources of the CPU & SoC
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│├processor_templates  - Pre-configured SoC wrappers
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│├system_integration   - System wrappers for advanced connectivity
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│└test_setups          - Minimal test setup "SoCs" used in the User Guide
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├setups                - Example setups for various FPGAs, boards and toolchains
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│└...
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├sim                   - Simulation files (see User Guide)
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└sw                    - Software framework
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 ├bootloader           - Sources and scripts for the NEORV32 internal bootloader
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 ├common               - Linker script and crt0.S start-up code
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 ├example              - Various example programs
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 │└...
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 ├isa-test
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 │├riscv-arch-test     - RISC-V spec. compatibility test framework (submodule)
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 │└port-neorv32        - Port files for the official RISC-V architecture tests
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 ├ocd_firmware         - source code for on-chip debugger's "park loop"
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 ├openocd              - OpenOCD on-chip debugger configuration files
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 ├image_gen            - Helper program to generate NEORV32 executables
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 └lib                  - Processor core library
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  ├include             - Header files (*.h)
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  └source              - Source files (*.c)
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...................................
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<<<
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// ####################################################################################################################
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:sectnums:
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=== VHDL File Hierarchy
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All necessary VHDL hardware description files are located in the project's `rtl/core folder`. The top entity
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of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.
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[IMPORTANT]
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All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
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files, like alternative top entities, can be assigned to any library.
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...................................
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neorv32_top.vhd                  - NEORV32 Processor top entity
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├neorv32_fifo.vhd                - General purpose FIFO component
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├neorv32_package.vhd             - Processor/CPU main VHDL package file
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├neorv32_cpu.vhd                 - NEORV32 CPU top entity
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│├neorv32_cpu_alu.vhd            - Arithmetic/logic unit
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││├neorv32_cpu_cp_bitmanip.vhd   - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_fpu.vhd        - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_muldiv.vhd     - Mul/Div co-processor (M extension)
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││└neorv32_cpu_cp_shifter.vhd    - Bit-shift co-processor
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│├neorv32_cpu_bus.vhd            - Bus interface + physical memory protection
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│├neorv32_cpu_control.vhd        - CPU control, exception/IRQ system and CSRs
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││└neorv32_cpu_decompressor.vhd  - Compressed instructions decoder
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│└neorv32_cpu_regfile.vhd        - Data register file
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├neorv32_boot_rom.vhd            - Bootloader ROM
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│└neorv32_bootloader_image.vhd   - Bootloader boot ROM memory image
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├neorv32_busswitch.vhd           - Processor bus switch for CPU buses (I&D)
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├neorv32_bus_keeper.vhd          - Processor-internal bus monitor
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├neorv32_cfs.vhd                 - Custom functions subsystem
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├neorv32_debug_dm.vhd            - on-chip debugger: debug module
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├neorv32_debug_dtm.vhd           - on-chip debugger: debug transfer module
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├neorv32_dmem.vhd                - Processor-internal data memory
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├neorv32_gpio.vhd                - General purpose input/output port unit
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├neorv32_icache.vhd              - Processor-internal instruction cache
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├neorv32_imem.vhd                - Processor-internal instruction memory
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│└neor32_application_image.vhd   - IMEM application initialization image
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├neorv32_mtime.vhd               - Machine system timer
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├neorv32_neoled.vhd              - NeoPixel (TM) compatible smart LED interface
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├neorv32_pwm.vhd                 - Pulse-width modulation controller
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├neorv32_spi.vhd                 - Serial peripheral interface controller
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├neorv32_sysinfo.vhd             - System configuration information memory
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├neorv32_trng.vhd                - True random number generator
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├neorv32_twi.vhd                 - Two wire serial interface controller
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├neorv32_uart.vhd                - Universal async. receiver/transmitter
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├neorv32_wdt.vhd                 - Watchdog timer
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├neorv32_wishbone.vhd            - External (Wishbone) bus interface
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└neorv32_xirq.vhd                - External interrupt controller
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...................................
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<<<
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// ####################################################################################################################
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:sectnums:
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=== FPGA Implementation Results
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This chapter shows _exemplary_ implementation results of the NEORV32 CPU and NEORV32 Processor.
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:sectnums:
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==== CPU
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[cols="<2,<8"]
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[grid="topbot"]
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|=======================
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| Hardware version: | `1.5.7.10`
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| Top entity:       | `rtl/core/neorv32_cpu.vhd`
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|=======================
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[cols="<5,>1,>1,>1,>1,>1"]
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[options="header",grid="rows"]
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|=======================
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| CPU                                        | LEs  | FFs  | MEM bits | DSPs | _f~max~_
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| `rv32i`                                    |  806 |  359 |     1024 |    0 | 125 MHz
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| `rv32i_Zicsr`                              | 1729 |  813 |     1024 |    0 | 124 MHz
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| `rv32im_Zicsr`                             | 2269 | 1055 |     1024 |    0 | 124 MHz
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| `rv32imc_Zicsr`                            | 2501 | 1070 |     1024 |    0 | 124 MHz
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| `rv32imac_Zicsr`                           | 2511 | 1074 |     1024 |    0 | 124 MHz
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| `rv32imacu_Zicsr`                          | 2521 | 1079 |     1024 |    0 | 124 MHz
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| `rv32imacu_Zicsr_Zifencei`                 | 2522 | 1079 |     1024 |    0 | 122 MHz
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| `rv32imacu_Zicsr_Zifencei_Zfinx`           | 3807 | 1731 |     1024 |    7 | 116 MHz
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| `rv32imacu_Zicsr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 |     1024 |    7 | 116 MHz
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|=======================
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[NOTE]
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No HPM counters and no PMP regions were implemented for generating these results.
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[TIP]
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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:sectnums:
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==== Processor Modules
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[cols="<2,<8"]
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[grid="topbot"]
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|=======================
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| Hardware version: | `1.5.7.15`
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| Top entity:       | `rtl/core/neorv32_top.vhd`
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|=======================
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.Hardware utilization by the processor modules (mandatory core modules in **bold**)
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[cols="<2,<8,>1,>1,>2,>1"]
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[options="header",grid="rows"]
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|=======================
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| Module        | Description                                           | LEs | FFs | MEM bits | DSPs
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| Boot ROM      | Bootloader ROM (4kB)                                  |   2 |   1 |    32768 |    0
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| **BUSKEEPER** | Processor-internal bus monitor                        |   9 |   6 |        0 |    0
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| **BUSSWITCH** | Bus mux for CPU instr. and data interface             |  63 |   8 |        0 |    0
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| CFS           | Custom functions subsystemfootnote:[Resource utilization depends on actually implemented custom functionality.] | - | - | - | -
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| DMEM          | Processor-internal data memory (8kB)                  |  19 |   2 |    65536 |    0
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| DM            | On-chip debugger - debug module                       | 493 | 240 |        0 |    0
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| DTM           | On-chip debugger - debug transfer module (JTAG)       | 254 | 218 |        0 |    0
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| GPIO          | General purpose input/output ports                    | 134 | 161 |        0 |    0
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| iCACHE        | Instruction cache (1x4 blocks, 256 bytes per block)   | 2 21| 156 |     8192 |    0
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| IMEM          | Processor-internal instruction memory (16kB)          |  13 |   2 |   131072 |    0
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| MTIME         | Machine system timer                                  | 319 | 167 |        0 |    0
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| NEOLED        | Smart LED Interface (NeoPixel/WS28128) [FIFO_depth=1] | 226 | 182 |        0 |    0
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| SLINK         | Stream link interface (2xRX, 2xTX, FIFO_depth=1)      | 208 | 181 |        0 |    0
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| PWM           | Pulse_width modulation controller (4 channels)        |  71 |  69 |        0 |    0
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| SPI           | Serial peripheral interface                           | 148 | 127 |        0 |    0
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| **SYSINFO**   | System configuration information memory               |  14 |  11 |        0 |    0
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| TRNG          | True random number generator                          |  89 |  76 |        0 |    0
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| TWI           | Two-wire interface                                    |  77 |  43 |        0 |    0
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| UART0/1       | Universal asynchronous receiver/transmitter 0/1       | 183 | 132 |        0 |    0
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| WDT           | Watchdog timer                                        |  53 |  43 |        0 |    0
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| WISHBONE      | External memory interface                             | 114 | 110 |        0 |    0
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| XIRQ          | External interrupt controller (32 channels)           | 241 | 201 |        0 |    0
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|=======================
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<<<
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:sectnums:
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==== Exemplary Setups
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Check out the `setups` folder (@GitHub: https://github.com/stnolting/neorv32/tree/master/setups),
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which provides several demo setups for various FPGA boards and toolchains.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== CPU Performance
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The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].
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This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole
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system. The according sources can be found in the `sw/example/coremark` folder.
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.Dhrystone
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[TIP]
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A _simple_ port of the Dhrystone benchmark is also available in `sw/example/dhrystone`.
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The resulting CoreMark score is defined as CoreMark iterations per second.
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The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is
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defined as CoreMark score divided by the CPU's clock frequency in MHz.
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.Configuration
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[cols="<2,<8"]
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[grid="topbot"]
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|=======================
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| HW version:     | `1.5.7.10`
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| Hardware:       | 32kB int. IMEM, 16kB int. DMEM, no caches, 100MHz clock
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| CoreMark:       | 2000 iterations, MEM_METHOD is MEM_STACK
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| Compiler:       | RISCV32-GCC 10.2.0
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| Compiler flags: | default, see makefile
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|=======================
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.CoreMark results
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[cols="<4,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| CPU                                            | CoreMark Score | CoreMarks/Mhz | Average CPI
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| _small_ (`rv32i_Zicsr`)                        |          33.89 | **0.3389**    | **4.04**
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| _medium_ (`rv32imc_Zicsr`)                     |          62.50 | **0.6250**    | **5.34**
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| _performance_(`rv32imc_Zicsr` + perf. options) |          95.23 | **0.9523**    | **3.54**
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|=======================
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[NOTE]
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The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.
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[NOTE]
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The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of
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several consecutive micro operations.
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[NOTE]
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The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on
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the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles
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(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions
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(`[m]instret[h]` CSRs).
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[TIP]
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More information regarding the execution time of each implemented instruction can be found in
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chapter <<_instruction_timing>>.

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