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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
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interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8
 
9
image::neorv32_processor.png[align=center]
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11
**Key Features**
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13
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
29
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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37
The following table shows all interface ports of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively.
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40
[TIP]
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A wrapper for the NEORV32 Processor setup providing resolved port signals can be found in
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`rtl/templates/processor/neorv32_ProcessorTop_stdlogic.vhd`.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 4 | out | pulse-width modulated channels
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **<<_processor_interrupts, External Interrupts>>**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **<<_processor_interrupts, CPU Interrupts>>**
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| `nm_irq_i`    | 1 | in | non-maskable interrupt
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V)
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V)
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|=======================
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance.
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134
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the `misa` and
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`mzext` (see <<_machine_trap_setup>> and <<_neorv32_specific_custom_csrs>>) CSRs and via the memory-mapped _SYSINFO_ module (see <<_system_configuration_information_memory_sysinfo>>),
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respectively.
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139
[TIP]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry **will not be synthesized at all**.
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Hence, the disabled modules do not increase area and power requirements and do not impact the timing.
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[TIP]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
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<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | 0
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | true
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
188
 
189
 
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:sectnums!:
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===== _USER_CODE_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **USER_CODE** | _std_ulogic_vector(31 downto 0)_ | x"00000000"
197
3+| Custom user code that can be read by software via the _SYSINFO_ module.
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|======
199
 
200
 
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:sectnums!:
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===== _HW_THREAD_ID_
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204
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
207
| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Can be read via the `mhartid` CSR. Hart IDs must be unique within a system.
209
|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement on-chip debugger (OCD). See chapter <<_on_chip_debugger_ocd>>.
220
|======
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223
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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227
See section <<_instruction_sets_and_extensions>> for more information.
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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233
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
240
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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245
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
249
3+| Implement compressed instructions (16-bit) when _true_.
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See section <<_c_compressed_instructions>>.
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|======
252
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
260
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_.
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See section <<_e_embedded_cpu>>.
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|======
264
 
265
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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269
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement integer multiplication and division instructions when _true_.
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See section <<_m_integer_multiplication_and_division>>.
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|======
276
 
277
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_U_
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281
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
285
3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>>.
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|======
288
 
289
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
292
 
293
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
296
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
298
See section <<_zfinx_single_precision_floating_point_operations>>.
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|======
300
 
301
 
302
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicsr_
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305
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
308
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
309
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
310
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
311
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>>.
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|======
314
 
315
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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319
[cols="4,4,2"]
320
[frame="all",grid="none"]
321
|======
322
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for i-cache flushes).
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See section <<_zifencei_instruction_stream_synchronization>>.
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|======
327
 
328
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zmmul_
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332
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
336
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extensions of the `M` extension.
337
See section <<_zmmul_integer_multiplication>>.
338
|======
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340
 
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// ####################################################################################################################
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:sectnums:
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==== Extension Options
344
 
345
See section <<_instruction_sets_and_extensions>> for more information.
346
 
347
 
348
:sectnums!:
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===== _FAST_MUL_EN_
350
 
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **FAST_MUL_EN** | _boolean_ | false
355
3+| When this generic is enabled, the multiplier of the `M` extension is realized using DSPs blocks instead of an
356
iterative bit-serial approach. This generic is only relevant when the multiplier and divider CPU extension is
357
enabled (<<_cpu_extension_riscv_m>> is _true_).
358
|======
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:sectnums!:
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===== _FAST_SHIFT_EN_
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364
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
367
| **FAST_SHIFT_EN** | _boolean_ | false
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3+| When this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
369
more hardware resources). If it is set _false_ the CPU uses a serial shifter that only performs a single bit shift per cycle
370
(small but slow).
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|======
372
 
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374
:sectnums!:
375
===== _CPU_CNT_WIDTH_
376
 
377
[cols="4,4,2"]
378
[frame="all",grid="none"]
379
|======
380
| **CPU_CNT_WIDTH** | _natural_ | 0
381
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
382
The maximum value is 64, the minimal is 0. See
383
section <<_machine_counters_and_timers>> for more information. Note: Configurations with <<_cpu_cnt_width>>
384
less than 64 are not RISC-V compliant.
385
|======
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387
 
388
// ####################################################################################################################
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:sectnums:
390
==== Physical Memory Protection (PMP)
391
 
392
See section <<_pmp_physical_memory_protection>> for more information.
393
 
394
 
395
:sectnums!:
396
===== _PMP_NUM_REGIONS_
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398
[cols="4,4,2"]
399
[frame="all",grid="none"]
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|======
401
| **PMP_NUM_REGIONS** | _natural_ | 0
402
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
403
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _CSR_MZEXT_PMP_ flag
404
in the <<_mzext>> CSR.
405
|======
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408
:sectnums!:
409
===== _PMP_MIN_GRANULARITY_
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411
[cols="4,4,2"]
412
[frame="all",grid="none"]
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|======
414
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
415
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
416
|======
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419
// ####################################################################################################################
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:sectnums:
421
==== Hardware Performance Monitors (HPM)
422
 
423
See section <<_hpm_hardware_performance_monitors>> for more information.
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426
:sectnums!:
427
===== _HPM_NUM_CNTS_
428
 
429
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
432
| **HPM_NUM_CNTS** | _natural_ | 0
433
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
434
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _CSR_MZEXT_HPM_ flag
435
in the <<_mzext>> CSR.
436
|======
437
 
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439
:sectnums!:
440
===== _HPM_CNT_WIDTH_
441
 
442
[cols="4,4,2"]
443
[frame="all",grid="none"]
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|======
445
| **HPM_CNT_WIDTH** | _natural_ | 40
446
3+| This generic defines the total LSB-aligned size of each HPM counter (size(`[m]hpmcounter*h`) +
447
size(`[m]hpmcounter*`)). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
448
unused MSB-aligned counter bits are hardwired to zero.
449
|======
450
 
451
 
452
// ####################################################################################################################
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:sectnums:
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==== Internal Instruction Memory
455
 
456
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
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459
:sectnums!:
460
===== _MEM_INT_IMEM_EN_
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462
[cols="4,4,2"]
463
[frame="all",grid="none"]
464
|======
465
| **MEM_INT_IMEM_EN** | _boolean_ | true
466
3+| Implement processor internal instruction memory (IMEM) when _true_.
467
|======
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470
:sectnums!:
471
===== _MEM_INT_IMEM_SIZE_
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473
[cols="4,4,2"]
474
[frame="all",grid="none"]
475
|======
476
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
477
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when _MEM_INT_IMEM_EN_ is _false_.
478
|======
479
 
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481
// ####################################################################################################################
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:sectnums:
483
==== Internal Data Memory
484
 
485
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
486
 
487
 
488
:sectnums!:
489
===== _MEM_INT_DMEM_EN_
490
 
491
[cols="4,4,2"]
492
[frame="all",grid="none"]
493
|======
494
| **MEM_INT_DMEM_EN** | _boolean_ | true
495
3+| Implement processor internal data memory (DMEM) when _true_.
496
|======
497
 
498
 
499
:sectnums!:
500
===== _MEM_INT_DMEM_SIZE_
501
 
502
[cols="4,4,2"]
503
[frame="all",grid="none"]
504
|======
505
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
506
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when _MEM_INT_DMEM_EN_ is _false_.
507
|======
508
 
509
 
510
// ####################################################################################################################
511
:sectnums:
512
==== Internal Cache Memory
513
 
514
See section <<_processor_internal_instruction_cache_icache>> for more information.
515
 
516
 
517
:sectnums!:
518
===== _ICACHE_EN_
519
 
520
[cols="4,4,2"]
521
[frame="all",grid="none"]
522
|======
523
| **ICACHE_EN** | _boolean_ | false
524
3+| Implement processor internal instruction cache when _true_.
525
|======
526
 
527
 
528
:sectnums!:
529
===== _ICACHE_NUM_BLOCK_
530
 
531
[cols="4,4,2"]
532
[frame="all",grid="none"]
533
|======
534
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
535
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
536
effect when _ICACHE_DMEM_EN_ is false.
537
|======
538
 
539
 
540
:sectnums!:
541
===== _ICACHE_BLOCK_SIZE_
542
 
543
[cols="4,4,2"]
544
[frame="all",grid="none"]
545
|======
546
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
547
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
548
_ICACHE_EN_ is _false_.
549
|======
550
 
551
 
552
:sectnums!:
553
===== _ICACHE_ASSOCIATIVITY_
554
 
555
[cols="4,4,2"]
556
[frame="all",grid="none"]
557
|======
558
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
559
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
560
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when _ICACHE_EN_ is _false_.
561
|======
562
 
563
 
564
// ####################################################################################################################
565
:sectnums:
566
==== External Memory Interface
567
 
568
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
569
 
570
 
571
:sectnums!:
572
===== _MEM_EXT_EN_
573
 
574
[cols="4,4,2"]
575
[frame="all",grid="none"]
576
|======
577
| **MEM_EXT_EN** | _boolean_ | false
578
3+| Implement external bus interface (WISHBONE) when _true_.
579
|======
580
 
581
 
582
:sectnums!:
583
===== _MEM_EXT_TIMEOUT_
584
 
585
[cols="4,4,2"]
586
[frame="all",grid="none"]
587
|======
588
| **MEM_EXT_TIMEOUT** | _natural_ | 255
589 61 zero_gravi
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
590 60 zero_gravi
|======
591
 
592
 
593
// ####################################################################################################################
594
:sectnums:
595 61 zero_gravi
==== Stream Link Interface
596
 
597
See section <<_stream_link_interface_slink>> for more information.
598
 
599
 
600
:sectnums!:
601
===== _SLINK_NUM_TX_
602
 
603
[cols="4,4,2"]
604
[frame="all",grid="none"]
605
|======
606
| **SLINK_NUM_TX** | _natural_ | 0
607
3+| Number of TX (send) links to implement. Valid values are 0..8.
608
|======
609
 
610
 
611
:sectnums!:
612
===== _SLINK_NUM_RX_
613
 
614
[cols="4,4,2"]
615
[frame="all",grid="none"]
616
|======
617
| **SLINK_NUM_RX** | _natural_ | 0
618
3+| Number of RX (receive) links to implement. Valid values are 0..8.
619
|======
620
 
621
 
622
:sectnums!:
623
===== _SLINK_TX_FIFO_
624
 
625
[cols="4,4,2"]
626
[frame="all",grid="none"]
627
|======
628
| **SLINK_TX_FIFO** | _natural_ | 1
629
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
630
|======
631
 
632
 
633
:sectnums!:
634
===== _SLINK_RX_FIFO_
635
 
636
[cols="4,4,2"]
637
[frame="all",grid="none"]
638
|======
639
| **SLINK_RX_FIFO** | _natural_ | 1
640
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
641
|======
642
 
643
 
644
// ####################################################################################################################
645
:sectnums:
646
==== External Interrupt Controller
647
 
648
See section <<_external_interrupt_controller_xirq>> for more information.
649
 
650
 
651
:sectnums!:
652
===== _XIRQ_NUM_CH_
653
 
654
[cols="4,4,2"]
655
[frame="all",grid="none"]
656
|======
657
| **XIRQ_NUM_CH** | _natural_ | 0
658
3+| Number of external interrupt channels o implement. Valid values are 0..32.
659
|======
660
 
661
 
662
:sectnums!:
663
===== _XIRQ_TRIGGER_TYPE_
664
 
665
[cols="4,4,2"]
666
[frame="all",grid="none"]
667
|======
668
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
669
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
670
_XIRQ_TRIGGER_POLARITY_ generic is used to specify the actual level (high/low) or edge (falling/rising).
671
|======
672
 
673
 
674
:sectnums!:
675
===== _XIRQ_TRIGGER_POLARITY_
676
 
677
[cols="4,4,2"]
678
[frame="all",grid="none"]
679
|======
680
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
681
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
682
'1' = high-level/rising-edge. _XIRQ_TRIGGER_TYPE_ generic is used to specify the actual type (level or edge).
683
|======
684
 
685
 
686
// ####################################################################################################################
687
:sectnums:
688 60 zero_gravi
==== Processor Peripheral/IO Modules
689
 
690
See section <<_processor_internal_modules>> for more information.
691
 
692
 
693
:sectnums!:
694
===== _IO_GPIO_EN_
695
 
696
[cols="4,4,2"]
697
[frame="all",grid="none"]
698
|======
699
| **IO_GPIO_EN** | _boolean_ | true
700
3+| Implement general purpose input/output port unit (GPIO) when _true_.
701
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
702
|======
703
 
704
 
705
:sectnums!:
706
===== _IO_MTIME_EN_
707
 
708
[cols="4,4,2"]
709
[frame="all",grid="none"]
710
|======
711
| **IO_MTIME_EN** | _boolean_ | true
712
3+| Implement machine system timer (MTIME) when _true_.
713
See section <<_machine_system_timer_mtime>> for more information.
714
|======
715
 
716
 
717
:sectnums!:
718
===== _IO_UART0_EN_
719
 
720
[cols="4,4,2"]
721
[frame="all",grid="none"]
722
|======
723
| **IO_UART0_EN** | _boolean_ | true
724
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
725
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
726
more information.
727
|======
728
 
729
 
730
:sectnums!:
731
===== _IO_UART1_EN_
732
 
733
[cols="4,4,2"]
734
[frame="all",grid="none"]
735
|======
736
| **IO_UART1_EN** | _boolean_ | true
737 61 zero_gravi
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
738 60 zero_gravi
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
739
|======
740
 
741
 
742
:sectnums!:
743
===== _IO_SPI_EN_
744
 
745
[cols="4,4,2"]
746
[frame="all",grid="none"]
747
|======
748
| **IO_SPI_EN** | _boolean_ | true
749
3+| Implement serial peripheral interface controller (SPI) when _true_.
750
See section <<_serial_peripheral_interface_controller_spi>> for more information.
751
|======
752
 
753
 
754
:sectnums!:
755
===== _IO_TWI_EN_
756
 
757
[cols="4,4,2"]
758
[frame="all",grid="none"]
759
|======
760
| **IO_TWI_EN** | _boolean_ | true
761
3+| Implement two-wire interface controller (TWI) when _true_.
762
See section <<_two_wire_serial_interface_controller_twi>> for
763
more information.
764
|======
765
 
766
 
767
:sectnums!:
768
===== _IO_PWM_NUM_CH_
769
 
770
[cols="4,4,2"]
771
[frame="all",grid="none"]
772
|======
773
| **IO_PWM_NUM_CH** | _natural_ | 4
774
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
775
See section <<_pulse_width_modulation_controller_pwm>> for more information.
776
|======
777
 
778
 
779
:sectnums!:
780
===== _IO_WDT_EN_
781
 
782
[cols="4,4,2"]
783
[frame="all",grid="none"]
784
|======
785
| **IO_WDT_EN** | _boolean_ | true
786
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
787
information.
788
|======
789
 
790
 
791
:sectnums!:
792
===== _IO_TRNG_EN_
793
 
794
[cols="4,4,2"]
795
[frame="all",grid="none"]
796
|======
797
| **IO_TRNG_EN** | _boolean_ | false
798
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
799
|======
800
 
801
 
802
:sectnums!:
803
===== _IO_CFS_EN_
804
 
805
[cols="4,4,2"]
806
[frame="all",grid="none"]
807
|======
808
| **IO_CFS_EN** | _boolean_ | false
809
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
810
|======
811
 
812
 
813
:sectnums!:
814
===== _IO_CFS_CONFIG_
815
 
816
[cols="4,4,2"]
817
[frame="all",grid="none"]
818
|======
819
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
820
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
821
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
822
|======
823
 
824
 
825
:sectnums!:
826
===== _IO_CFS_IN_SIZE_
827
 
828
[cols="4,4,2"]
829
[frame="all",grid="none"]
830
|======
831
| **IO_CFS_IN_SIZE** | _positive_ | 32
832
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
833
|======
834
 
835
 
836
:sectnums!:
837
===== _IO_CFS_OUT_SIZE_
838
 
839
[cols="4,4,2"]
840
[frame="all",grid="none"]
841
|======
842
| **IO_CFS_OUT_SIZE** | _positive_ | 32
843
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
844
|======
845
 
846
 
847
:sectnums!:
848
===== _IO_NEOLED_EN_
849
 
850
[cols="4,4,2"]
851
[frame="all",grid="none"]
852
|======
853
| **IO_NEOLED_EN** | _boolean_ | true
854
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
855
See section <<_smart_led_interface_neoled>> for more information.
856
|======
857
 
858
 
859
<<<
860
// ####################################################################################################################
861
:sectnums:
862
=== Processor Interrupts
863
 
864 61 zero_gravi
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
865 60 zero_gravi
 
866
 
867 61 zero_gravi
:sectnums:
868
==== RISC-V Standard Interrupts
869
 
870 60 zero_gravi
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
871 61 zero_gravi
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
872
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
873
<<_traps_exceptions_and_interrupts>> for more information.
874 60 zero_gravi
 
875 61 zero_gravi
[cols="<3,^2,<11"]
876
[options="header",grid="rows"]
877
|=======================
878
| Top signal | Width | Description
879
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
880
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
881
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
882
|=======================
883 60 zero_gravi
 
884 61 zero_gravi
[NOTE]
885
These IRQs trigger on high-level.
886
 
887
 
888
:sectnums:
889
==== Non-Maskable Interrupt
890
 
891
[cols="<3,^2,<11"]
892
[options="header",grid="rows"]
893
|=======================
894
| Top signal | Width | Description
895
| `nm_irq_i` | 1 | Non-maskable interrupt.
896
|=======================
897
 
898
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
899
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
900
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
901
 
902
[NOTE]
903
This IRQ triggers on high-level.
904
 
905
 
906
:sectnums:
907
==== Platform External Interrupts
908
 
909
[cols="<3,^2,<11"]
910
[options="header",grid="rows"]
911
|=======================
912
| Top signal | Width | Description
913
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
914
|=======================
915
 
916
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
917
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
918
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
919
 
920
[NOTE]
921
The trigger for these interrupt can be defines via generics. See section
922
<<_external_interrupt_controller_xirq>> for more information.
923
 
924
 
925
:sectnums:
926
==== NEORV32-Specific Fast Interrupt Requests
927
 
928 60 zero_gravi
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
929 61 zero_gravi
(`FIRQ0` – `FIRQ15`). These are used for _processor-internal_ modules only (for example for the communication
930
interfaces to signal "available incoming data" or "ready to send new data").
931 60 zero_gravi
 
932 61 zero_gravi
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
933
the according FIRQ priority; 0 = highest, 15 = lowest):
934 60 zero_gravi
 
935
.NEORV32 fast interrupt channel mapping
936
[cols="^1,<2,<7"]
937
[options="header",grid="rows"]
938
|=======================
939
| Channel | Source | Description
940 61 zero_gravi
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
941
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
942
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
943
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
944
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
945
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
946
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
947
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
948
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
949
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
950
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data received
951
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data send
952
| 12:15   | - | _reserved_, cannot fire
953 60 zero_gravi
|=======================
954
 
955
 
956
 
957
<<<
958
// ####################################################################################################################
959
:sectnums:
960
=== Address Space
961
 
962 61 zero_gravi
The NEORV32 Processor provides 32-bit physical addresses accessing up to 4GB of address space.
963
By default, this address space is divided into four main regions:
964 60 zero_gravi
 
965 61 zero_gravi
1. **Instruction address space** – for instructions (=code) and constants. A configurable section of this address space is used by
966
internal and/or external _instruction memory_ (IMEM).
967
2. **Data address space** – for application runtime data (heap, stack, etc.). A configurable section of this address space is used by
968
internal and/or external _data memory_ (DMEM).
969
3. **Bootloader address space**. A _fixed_ section of this address space is used by
970
internal _bootloader memory_ (BOOTLDROM).
971
4. **IO/peripheral address space** – for the processor-internal IO/peripheral devices (e.g., UART).
972 60 zero_gravi
 
973
[TIP]
974
These four memory regions are handled by the linker when compiling a NEORV32 executable.
975
See section <<_executable_image_format>> for more information.
976
 
977 61 zero_gravi
.NEORV32 processor - address space (default configuration)
978
image::address_space.png[900]
979 60 zero_gravi
 
980
 
981
:sectnums:
982
==== CPU Data and Instruction Access
983
 
984
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
985
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
986
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
987
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
988
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
989
setup a modified von-Neumann architecture.
990
 
991
.Processor-internal bus architecture
992
image::neorv32_bus.png[1300]
993
 
994
[NOTE]
995
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
996
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
997
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
998
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
999
accesses.
1000
 
1001
[IMPORTANT]
1002
Please note that all processor-internal components including the peripheral/IO devices can also be
1003
accessed from programs running in less-privileged user mode. For example, if the system relies on
1004
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1005
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1006
PMP system (see <<_machine_physical_memory_protection>>).
1007
 
1008 61 zero_gravi
 
1009 60 zero_gravi
:sectnums:
1010 61 zero_gravi
==== Address Space Layout
1011
 
1012
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1013
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1014
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1015
`rtl/core/neorv32_package.vhd`:
1016
 
1017
[source,vhdl]
1018
----
1019
-- Architecture Configuration ----------------------------------------------------
1020
-- ----------------------------------------------------------------------------------
1021
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1022
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1023
----
1024
 
1025
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1026
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1027
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1028
are _aligned_ to a 4-byte boundary.
1029
 
1030
[NOTE]
1031
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1032
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1033
applications – even if the bootloader or all IO devices are not implemented - without modifying the core's
1034
hardware sources.
1035
 
1036
 
1037
:sectnums:
1038 60 zero_gravi
==== Physical Memory Attributes
1039
 
1040 61 zero_gravi
The processor setup defines fixed attributes for the four processor-internal address space regions.
1041
Accessing a memory region in a way that violates any of these attributes will raise an according
1042
access exception..
1043 60 zero_gravi
 
1044
* `r` – read access (from CPU data access interface, e.g. via "load")
1045
* `w` – write access (from CPU data access interface, e.g. via "store")
1046
* `x` – execute access (from CPU instruction fetch interface)
1047
* `a` – atomic access (from CPU data access interface)
1048
* `8` – byte (8-bit)-accessible (when writing)
1049
* `16` – half-word (16-bit)-accessible (when writing)
1050
* `32` – word (32-bit)-accessible (when writing)
1051
 
1052 61 zero_gravi
[NOTE]
1053
Read accesses (i.e. loads) can always access data in word, half-word and byte quantities (requiring an accordingly aligned address).
1054 60 zero_gravi
 
1055
[cols="^1,^2,^2,^3,^2"]
1056
[options="header",grid="rows"]
1057
|=======================
1058
| # | Region | Base address | Size | Attributes
1059
| 4 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
1060
| 3 | bootloader ROM        | 0xffff0000 | up to 32kB| `r/x/a`
1061
| 2 | DMEM                  | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
1062
| 1 | IMEM                  | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
1063
|=======================
1064
 
1065 61 zero_gravi
[TIP]
1066
The following table shows the provided physical memory attributes of each region. Additional attributes (for example
1067
controlling certain right for specific address space regions) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
1068 60 zero_gravi
 
1069
 
1070
:sectnums:
1071 61 zero_gravi
==== Memory Configuration
1072 60 zero_gravi
 
1073 61 zero_gravi
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1074
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1075
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1076
the internal ones. The figure below show some exemplary memory configurations.
1077 60 zero_gravi
 
1078 61 zero_gravi
.Exemplary memory configurations
1079
image::neorv32_memory_configurations.png[800]
1080 60 zero_gravi
 
1081 61 zero_gravi
:sectnums!:
1082
===== Internal Memories
1083
 
1084
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1085
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1086
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1087
 
1088 60 zero_gravi
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1089
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1090
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1091
implemented.
1092
 
1093 61 zero_gravi
[TIP]
1094
The default processor setup uses only _internal_ memories.
1095 60 zero_gravi
 
1096 61 zero_gravi
[NOTE]
1097
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1098
a "dead address space" between it and the DMEM. This provides an additional safety feature
1099
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1100
any access to the "dead address space" in between will raise an exception that can be caught
1101
by the runtime environment.
1102 60 zero_gravi
 
1103 61 zero_gravi
:sectnums!:
1104
===== External Memories
1105
 
1106
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1107
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1108
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1109
 
1110
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1111
via the processor's bus interface to external components:
1112
 
1113 60 zero_gravi
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1114
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1115
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1116
 
1117 61 zero_gravi
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1118
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1119
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1120
memory system.
1121 60 zero_gravi
 
1122 61 zero_gravi
[NOTE]
1123
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1124
the internal peripheral address space will trigger a bus access fault exception.
1125 60 zero_gravi
 
1126
 
1127 61 zero_gravi
:sectnums:
1128
==== Boot Configuration
1129
 
1130
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1131
The figure below shows the exemplary concepts for the two most common boot scenarios.
1132
 
1133
.NEORV32 boot configurations
1134
image::neorv32_boot_configurations.png[800]
1135
 
1136
[NOTE]
1137
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1138
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1139
 
1140
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1141
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1142
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1143
 
1144
[NOTE]
1145
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1146
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1147
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1148
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1149
store it to external _data_ memory and transfers CPU control to that.
1150
 
1151
:sectnums!:
1152
===== Indirect Boot
1153
 
1154
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
1155
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1156
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1157
 
1158
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
1159
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
1160
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1161
RAM so the bootloader can write the actual executable to it.
1162
 
1163
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1164
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1165
write the executable to the processor-external memory.
1166
 
1167
:sectnums!:
1168
===== Direct Boot
1169
 
1170
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
1171
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1172
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
1173
in order to provide an executable _in_ memory.
1174
 
1175
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1176
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
1177
 
1178
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1179
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
1180
 
1181
 
1182
 
1183 60 zero_gravi
<<<
1184
// ####################################################################################################################
1185
:sectnums:
1186
=== Processor-Internal Modules
1187
 
1188
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1189
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1190
system implements an internal reset generator and a global clock generator/divider.
1191
 
1192
**Internal Reset Generator**
1193
 
1194
Most processor-internal modules – except for the CPU and the watchdog timer – do not have a dedicated
1195
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1196
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1197
modules to ensure a clean system reset state.
1198
 
1199
The hardware reset signal of the processor can either be
1200
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1201
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1202
clock cycles.
1203
 
1204
**Internal Clock Divider**
1205
 
1206
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1207
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1208
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1209
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1210
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1211
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1212
power.
1213
 
1214
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1215
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1216
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1217
from the top entity's `clk_i` signal.
1218
 
1219
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1220
[grid="rows"]
1221
|=======================
1222
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1223
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1224
|=======================
1225
 
1226
**Peripheral / IO Devices**
1227
 
1228
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1229
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1230
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1231
library abstract the specific memory layout for the user.
1232
 
1233
[IMPORTANT]
1234
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
1235
load/store access fault exception is triggered.
1236
 
1237
[IMPORTANT]
1238
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1239
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1240
Processor-internal memories as well as modules connected to the external memory interface can still
1241
be written with a byte-wide granularity.
1242
 
1243
[TIP]
1244
You should use the provided core software library to interact with the peripheral devices. This
1245
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1246
register and register bit accesses.
1247
 
1248
[TIP]
1249
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1250
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1251
application start-up code `crt0.S`.
1252
 
1253
**Nomenclature for the Peripheral / IO Devices Listing**
1254
 
1255
Each peripheral device chapter features a register map showing accessible control and data registers of the
1256
according device including the implemented control and status bits. You can directly interact with these
1257
registers/bits via the provided _C-code defines_. These defines are set in the main processor core library
1258
include file `sw/lib/include/neorv32.h`. The registers and/or register bits, which can be accessed
1259
directly using plain C-code, are marked with a "[C]".
1260
 
1261
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1262
available:
1263
 
1264
* `r/w` registers / bits can be read and written
1265
* `r/-` registers / bits are read-only; any write access to them has no effect
1266
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1267
 
1268
[TIP]
1269
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1270
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1271
write zero to them to keep compatible with future extension.
1272
 
1273
[TIP]
1274
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1275
written. When reading data from a write-only register the result is undefined.
1276
 
1277
 
1278
include::soc_imem.adoc[]
1279
 
1280
include::soc_dmem.adoc[]
1281
 
1282
include::soc_bootrom.adoc[]
1283
 
1284
include::soc_icache.adoc[]
1285
 
1286
include::soc_wishbone.adoc[]
1287
 
1288 61 zero_gravi
include::soc_slink.adoc[]
1289
 
1290 60 zero_gravi
include::soc_gpio.adoc[]
1291
 
1292
include::soc_wdt.adoc[]
1293
 
1294
include::soc_mtime.adoc[]
1295
 
1296
include::soc_uart.adoc[]
1297
 
1298
include::soc_spi.adoc[]
1299
 
1300
include::soc_twi.adoc[]
1301
 
1302
include::soc_pwm.adoc[]
1303
 
1304
include::soc_trng.adoc[]
1305
 
1306
include::soc_cfs.adoc[]
1307
 
1308
include::soc_neoled.adoc[]
1309
 
1310 61 zero_gravi
include::soc_xirq.adoc[]
1311
 
1312 60 zero_gravi
include::soc_sysinfo.adoc[]
1313
 
1314
 

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