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// ####################################################################################################################
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:sectnums:
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| 4 |
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== NEORV32 Processor (SoC)
|
| 5 |
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|
|
| 6 |
|
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The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
|
| 7 |
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interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
|
| 8 |
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|
| 9 |
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image::neorv32_processor.png[align=center]
|
| 10 |
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| 11 |
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**Key Features**
|
| 12 |
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|
| 13 |
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* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
|
| 14 |
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
|
| 15 |
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
|
| 16 |
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
|
| 17 |
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
|
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
|
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
|
| 20 |
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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| 21 |
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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| 23 |
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
|
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
|
| 25 |
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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| 26 |
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
| 38 |
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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|
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[IMPORTAN]
|
| 41 |
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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| 42 |
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
| 43 |
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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| 44 |
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since all control signals have defined level.
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| 46 |
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[cols="<3,^2,^2,<11"]
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| 47 |
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
|
| 50 |
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4+^| **Global Control**
|
| 51 |
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
|
| 52 |
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
|
| 53 |
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
|
| 54 |
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| `jtag_trst_i` | 1 | in | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
|
| 55 |
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| `jtag_tck_i` | 1 | in | serial clock
|
| 56 |
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| `jtag_tdi_i` | 1 | in | serial data input
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| 57 |
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| `jtag_tdo_o` | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
|
| 58 |
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| `jtag_tms_i` | 1 | in | mode select
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| 59 |
60 |
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
|
| 60 |
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| `wb_tag_o` | 3 | out | tag (access type identifier)
|
| 61 |
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| `wb_adr_o` | 32 | out | destination address
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| 62 |
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| `wb_dat_i` | 32 | in | write data
|
| 63 |
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| `wb_dat_o` | 32 | out | read data
|
| 64 |
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| `wb_we_o` | 1 | out | write enable ('0' = read transfer)
|
| 65 |
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| `wb_sel_o` | 4 | out | byte enable
|
| 66 |
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| `wb_stb_o` | 1 | out | strobe
|
| 67 |
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| `wb_cyc_o` | 1 | out | valid cycle
|
| 68 |
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| `wb_lock_o`| 1 | out | exclusive access request
|
| 69 |
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| `wb_ack_i` | 1 | in | transfer acknowledge
|
| 70 |
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| `wb_err_i` | 1 | in | transfer error
|
| 71 |
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4+^| **Advanced Memory Control Signals**
|
| 72 |
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| `fence_o` | 1 | out | indicates an executed _fence_ instruction
|
| 73 |
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
|
| 74 |
61 |
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
|
| 75 |
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
|
| 76 |
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| `slink_tx_val_o` | 8 | out | TX link _n_ data valid
|
| 77 |
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| `slink_tx_rdy_i` | 8 | in | TX link _n_ allowed to send
|
| 78 |
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| `slink_rx_dat_i` | 8x32 | in | RX link _n_ data
|
| 79 |
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| `slink_rx_val_i` | 8 | in | RX link _n_ data valid
|
| 80 |
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| `slink_rx_rdy_o` | 8 | out | RX link _n_ ready to receive
|
| 81 |
60 |
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
|
| 82 |
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| `gpio_o` | 64 | out | general purpose parallel output
|
| 83 |
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| `gpio_i` | 64 | in | general purpose parallel input
|
| 84 |
60 |
zero_gravi |
4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
|
| 85 |
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
|
| 86 |
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
|
| 87 |
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
|
| 88 |
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
|
| 89 |
|
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
|
| 90 |
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
|
| 91 |
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
|
| 92 |
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
|
| 93 |
|
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
|
| 94 |
|
|
4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
|
| 95 |
|
|
| `spi_sck_o` | 1 | out | SPI controller clock line
|
| 96 |
|
|
| `spi_sdo_o` | 1 | out | SPI serial data output
|
| 97 |
|
|
| `spi_sdi_i` | 1 | in | SPI serial data input
|
| 98 |
|
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
|
| 99 |
|
|
4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
|
| 100 |
|
|
| `twi_sda_io` | 1 | inout | TWI serial data line
|
| 101 |
|
|
| `twi_scl_io` | 1 | inout | TWI serial clock line
|
| 102 |
|
|
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
|
| 103 |
|
|
| `cfs_in_i` | 32 | in | custom CFS input signal conduit
|
| 104 |
|
|
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
|
| 105 |
|
|
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
|
| 106 |
|
|
| `pwm_o` | 4 | out | pulse-width modulated channels
|
| 107 |
|
|
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
|
| 108 |
|
|
| `neoled_o` | 1 | out | asynchronous serial data output
|
| 109 |
|
|
4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
|
| 110 |
|
|
| `mtime_i` | 64 | in | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
|
| 111 |
|
|
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
|
| 112 |
61 |
zero_gravi |
4+^| **<<_processor_interrupts, External Interrupts>>**
|
| 113 |
|
|
| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
|
| 114 |
|
|
4+^| **<<_processor_interrupts, CPU Interrupts>>**
|
| 115 |
62 |
zero_gravi |
| `nm_irq_i` | 1 | in | non-maskable interrupt, rising-edge-triggered
|
| 116 |
|
|
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), rising-edge-triggered
|
| 117 |
|
|
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V), rising-edge-triggered
|
| 118 |
|
|
| `mext_irq_i` | 1 | in | machine external interrupt (RISC-V), rising-edge-triggered
|
| 119 |
60 |
zero_gravi |
|=======================
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
<<<
|
| 123 |
|
|
// ####################################################################################################################
|
| 124 |
|
|
:sectnums:
|
| 125 |
|
|
=== Processor Top Entity - Generics
|
| 126 |
|
|
|
| 127 |
|
|
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
|
| 128 |
|
|
The generic name is shown in orange, followed by the type in printed in black and concluded by the default
|
| 129 |
|
|
value printed in light gray.
|
| 130 |
|
|
|
| 131 |
|
|
[TIP]
|
| 132 |
|
|
The NEORV32 generics allow to configure the system according to your needs. The generics are
|
| 133 |
|
|
used to control implementation of certain CPU extensions and peripheral modules and even allow to
|
| 134 |
|
|
optimize the system for certain design goals like minimal area or maximum performance.
|
| 135 |
|
|
|
| 136 |
|
|
[TIP]
|
| 137 |
|
|
Privileged software can determine the actual CPU and processor configuration via the `misa` and
|
| 138 |
|
|
`mzext` (see <<_machine_trap_setup>> and <<_neorv32_specific_custom_csrs>>) CSRs and via the memory-mapped _SYSINFO_ module (see <<_system_configuration_information_memory_sysinfo>>),
|
| 139 |
|
|
respectively.
|
| 140 |
|
|
|
| 141 |
|
|
[TIP]
|
| 142 |
|
|
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry **will not be synthesized at all**.
|
| 143 |
|
|
Hence, the disabled modules do not increase area and power requirements and do not impact the timing.
|
| 144 |
|
|
|
| 145 |
61 |
zero_gravi |
[TIP]
|
| 146 |
|
|
Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
|
| 147 |
|
|
during synthesis/simulation if an invalid combination has been detected.
|
| 148 |
60 |
zero_gravi |
|
| 149 |
61 |
zero_gravi |
**Generic Description**
|
| 150 |
60 |
zero_gravi |
|
| 151 |
61 |
zero_gravi |
The description of each generic provides the following summary:
|
| 152 |
|
|
|
| 153 |
60 |
zero_gravi |
.Generic description
|
| 154 |
|
|
[cols="4,4,2"]
|
| 155 |
|
|
[frame="all",grid="none"]
|
| 156 |
|
|
|======
|
| 157 |
61 |
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| _Generic name_ | _type_ | _default value_
|
| 158 |
60 |
zero_gravi |
3+| _Description_
|
| 159 |
|
|
|======
|
| 160 |
|
|
|
| 161 |
|
|
<<<
|
| 162 |
|
|
// ####################################################################################################################
|
| 163 |
|
|
:sectnums:
|
| 164 |
|
|
==== General
|
| 165 |
|
|
|
| 166 |
|
|
See section <<_system_configuration_information_memory_sysinfo>> for more information.
|
| 167 |
|
|
|
| 168 |
|
|
:sectnums!:
|
| 169 |
|
|
===== _CLOCK_FREQUENCY_
|
| 170 |
|
|
|
| 171 |
|
|
[cols="4,4,2"]
|
| 172 |
|
|
[frame="all",grid="none"]
|
| 173 |
|
|
|======
|
| 174 |
62 |
zero_gravi |
| **CLOCK_FREQUENCY** | _natural_ | _none_
|
| 175 |
60 |
zero_gravi |
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
| 176 |
|
|
|======
|
| 177 |
|
|
|
| 178 |
|
|
|
| 179 |
|
|
:sectnums!:
|
| 180 |
61 |
zero_gravi |
===== _INT_BOOTLOADER_EN_
|
| 181 |
60 |
zero_gravi |
|
| 182 |
|
|
[cols="4,4,2"]
|
| 183 |
|
|
[frame="all",grid="none"]
|
| 184 |
|
|
|======
|
| 185 |
62 |
zero_gravi |
| **INT_BOOTLOADER_EN** | _boolean_ | false
|
| 186 |
61 |
zero_gravi |
3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
|
| 187 |
|
|
This will also change the processor's boot address from the beginning of the instruction memory address space (default =
|
| 188 |
|
|
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
| 189 |
60 |
zero_gravi |
|======
|
| 190 |
|
|
|
| 191 |
|
|
|
| 192 |
|
|
:sectnums!:
|
| 193 |
|
|
===== _USER_CODE_
|
| 194 |
|
|
|
| 195 |
|
|
[cols="4,4,2"]
|
| 196 |
|
|
[frame="all",grid="none"]
|
| 197 |
|
|
|======
|
| 198 |
|
|
| **USER_CODE** | _std_ulogic_vector(31 downto 0)_ | x"00000000"
|
| 199 |
|
|
3+| Custom user code that can be read by software via the _SYSINFO_ module.
|
| 200 |
|
|
|======
|
| 201 |
|
|
|
| 202 |
|
|
|
| 203 |
|
|
:sectnums!:
|
| 204 |
|
|
===== _HW_THREAD_ID_
|
| 205 |
|
|
|
| 206 |
|
|
[cols="4,4,2"]
|
| 207 |
|
|
[frame="all",grid="none"]
|
| 208 |
|
|
|======
|
| 209 |
|
|
| **HW_THREAD_ID** | _natural_ | 0
|
| 210 |
|
|
3+| The hart ID of the CPU. Can be read via the `mhartid` CSR. Hart IDs must be unique within a system.
|
| 211 |
|
|
|======
|
| 212 |
|
|
|
| 213 |
|
|
|
| 214 |
|
|
:sectnums!:
|
| 215 |
|
|
===== _ON_CHIP_DEBUGGER_EN_
|
| 216 |
|
|
|
| 217 |
|
|
[cols="4,4,2"]
|
| 218 |
|
|
[frame="all",grid="none"]
|
| 219 |
|
|
|======
|
| 220 |
|
|
| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
|
| 221 |
|
|
3+| Implement on-chip debugger (OCD). See chapter <<_on_chip_debugger_ocd>>.
|
| 222 |
|
|
|======
|
| 223 |
|
|
|
| 224 |
|
|
|
| 225 |
|
|
// ####################################################################################################################
|
| 226 |
|
|
:sectnums:
|
| 227 |
|
|
==== RISC-V CPU Extensions
|
| 228 |
|
|
|
| 229 |
|
|
See section <<_instruction_sets_and_extensions>> for more information.
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
:sectnums!:
|
| 233 |
|
|
===== _CPU_EXTENSION_RISCV_A_
|
| 234 |
|
|
|
| 235 |
|
|
[cols="4,4,2"]
|
| 236 |
|
|
[frame="all",grid="none"]
|
| 237 |
|
|
|======
|
| 238 |
|
|
| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
|
| 239 |
|
|
3+| Implement atomic memory access operations when _true_.
|
| 240 |
61 |
zero_gravi |
See section <<_a_atomic_memory_access>>.
|
| 241 |
60 |
zero_gravi |
|======
|
| 242 |
|
|
|
| 243 |
|
|
|
| 244 |
|
|
:sectnums!:
|
| 245 |
|
|
===== _CPU_EXTENSION_RISCV_C_
|
| 246 |
|
|
|
| 247 |
|
|
[cols="4,4,2"]
|
| 248 |
|
|
[frame="all",grid="none"]
|
| 249 |
|
|
|======
|
| 250 |
|
|
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
|
| 251 |
|
|
3+| Implement compressed instructions (16-bit) when _true_.
|
| 252 |
61 |
zero_gravi |
See section <<_c_compressed_instructions>>.
|
| 253 |
60 |
zero_gravi |
|======
|
| 254 |
|
|
|
| 255 |
|
|
|
| 256 |
|
|
:sectnums!:
|
| 257 |
|
|
===== _CPU_EXTENSION_RISCV_E_
|
| 258 |
|
|
|
| 259 |
|
|
[cols="4,4,2"]
|
| 260 |
|
|
[frame="all",grid="none"]
|
| 261 |
|
|
|======
|
| 262 |
|
|
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
|
| 263 |
|
|
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_.
|
| 264 |
61 |
zero_gravi |
See section <<_e_embedded_cpu>>.
|
| 265 |
60 |
zero_gravi |
|======
|
| 266 |
|
|
|
| 267 |
|
|
|
| 268 |
|
|
:sectnums!:
|
| 269 |
|
|
===== _CPU_EXTENSION_RISCV_M_
|
| 270 |
|
|
|
| 271 |
|
|
[cols="4,4,2"]
|
| 272 |
|
|
[frame="all",grid="none"]
|
| 273 |
|
|
|======
|
| 274 |
|
|
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
|
| 275 |
|
|
3+| Implement integer multiplication and division instructions when _true_.
|
| 276 |
61 |
zero_gravi |
See section <<_m_integer_multiplication_and_division>>.
|
| 277 |
60 |
zero_gravi |
|======
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
:sectnums!:
|
| 281 |
|
|
===== _CPU_EXTENSION_RISCV_U_
|
| 282 |
|
|
|
| 283 |
|
|
[cols="4,4,2"]
|
| 284 |
|
|
[frame="all",grid="none"]
|
| 285 |
|
|
|======
|
| 286 |
|
|
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
|
| 287 |
|
|
3+| Implement less-privileged user mode when _true_.
|
| 288 |
61 |
zero_gravi |
See section <<_u_less_privileged_user_mode>>.
|
| 289 |
60 |
zero_gravi |
|======
|
| 290 |
|
|
|
| 291 |
|
|
|
| 292 |
|
|
:sectnums!:
|
| 293 |
|
|
===== _CPU_EXTENSION_RISCV_Zfinx_
|
| 294 |
|
|
|
| 295 |
|
|
[cols="4,4,2"]
|
| 296 |
|
|
[frame="all",grid="none"]
|
| 297 |
|
|
|======
|
| 298 |
|
|
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
|
| 299 |
61 |
zero_gravi |
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
|
| 300 |
|
|
See section <<_zfinx_single_precision_floating_point_operations>>.
|
| 301 |
60 |
zero_gravi |
|======
|
| 302 |
|
|
|
| 303 |
|
|
|
| 304 |
|
|
:sectnums!:
|
| 305 |
|
|
===== _CPU_EXTENSION_RISCV_Zicsr_
|
| 306 |
|
|
|
| 307 |
|
|
[cols="4,4,2"]
|
| 308 |
|
|
[frame="all",grid="none"]
|
| 309 |
|
|
|======
|
| 310 |
|
|
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
|
| 311 |
|
|
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
|
| 312 |
|
|
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
|
| 313 |
|
|
no machine information will be available.
|
| 314 |
61 |
zero_gravi |
See section <<_zicsr_control_and_status_register_access_privileged_architecture>>.
|
| 315 |
60 |
zero_gravi |
|======
|
| 316 |
|
|
|
| 317 |
|
|
|
| 318 |
|
|
:sectnums!:
|
| 319 |
|
|
===== _CPU_EXTENSION_RISCV_Zifencei_
|
| 320 |
|
|
|
| 321 |
|
|
[cols="4,4,2"]
|
| 322 |
|
|
[frame="all",grid="none"]
|
| 323 |
|
|
|======
|
| 324 |
|
|
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
|
| 325 |
61 |
zero_gravi |
3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
|
| 326 |
60 |
zero_gravi |
for self-modifying code (and/or for i-cache flushes).
|
| 327 |
61 |
zero_gravi |
See section <<_zifencei_instruction_stream_synchronization>>.
|
| 328 |
60 |
zero_gravi |
|======
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
61 |
zero_gravi |
:sectnums!:
|
| 332 |
|
|
===== _CPU_EXTENSION_RISCV_Zmmul_
|
| 333 |
|
|
|
| 334 |
|
|
[cols="4,4,2"]
|
| 335 |
|
|
[frame="all",grid="none"]
|
| 336 |
|
|
|======
|
| 337 |
|
|
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
|
| 338 |
|
|
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extensions of the `M` extension.
|
| 339 |
|
|
See section <<_zmmul_integer_multiplication>>.
|
| 340 |
|
|
|======
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
60 |
zero_gravi |
// ####################################################################################################################
|
| 344 |
|
|
:sectnums:
|
| 345 |
|
|
==== Extension Options
|
| 346 |
|
|
|
| 347 |
|
|
See section <<_instruction_sets_and_extensions>> for more information.
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
:sectnums!:
|
| 351 |
|
|
===== _FAST_MUL_EN_
|
| 352 |
|
|
|
| 353 |
|
|
[cols="4,4,2"]
|
| 354 |
|
|
[frame="all",grid="none"]
|
| 355 |
|
|
|======
|
| 356 |
|
|
| **FAST_MUL_EN** | _boolean_ | false
|
| 357 |
|
|
3+| When this generic is enabled, the multiplier of the `M` extension is realized using DSPs blocks instead of an
|
| 358 |
|
|
iterative bit-serial approach. This generic is only relevant when the multiplier and divider CPU extension is
|
| 359 |
|
|
enabled (<<_cpu_extension_riscv_m>> is _true_).
|
| 360 |
|
|
|======
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
:sectnums!:
|
| 364 |
|
|
===== _FAST_SHIFT_EN_
|
| 365 |
|
|
|
| 366 |
|
|
[cols="4,4,2"]
|
| 367 |
|
|
[frame="all",grid="none"]
|
| 368 |
|
|
|======
|
| 369 |
|
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
| 370 |
61 |
zero_gravi |
3+| When this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
| 371 |
|
|
more hardware resources). If it is set _false_ the CPU uses a serial shifter that only performs a single bit shift per cycle
|
| 372 |
|
|
(small but slow).
|
| 373 |
60 |
zero_gravi |
|======
|
| 374 |
|
|
|
| 375 |
|
|
|
| 376 |
|
|
:sectnums!:
|
| 377 |
|
|
===== _CPU_CNT_WIDTH_
|
| 378 |
|
|
|
| 379 |
|
|
[cols="4,4,2"]
|
| 380 |
|
|
[frame="all",grid="none"]
|
| 381 |
|
|
|======
|
| 382 |
62 |
zero_gravi |
| **CPU_CNT_WIDTH** | _natural_ | 64
|
| 383 |
60 |
zero_gravi |
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
|
| 384 |
62 |
zero_gravi |
The maximum value is 64, the minimum value is 0. See
|
| 385 |
|
|
section <<_machine_counters_and_timers>> for more information. Note: configurations with <<_cpu_cnt_width>>
|
| 386 |
|
|
less than 64 bits do not comply to the RISC-V specs.
|
| 387 |
60 |
zero_gravi |
|======
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
62 |
zero_gravi |
:sectnums!:
|
| 391 |
|
|
===== _CPU_IPB_ENTRIES_
|
| 392 |
|
|
|
| 393 |
|
|
[cols="4,4,2"]
|
| 394 |
|
|
[frame="all",grid="none"]
|
| 395 |
|
|
|======
|
| 396 |
|
|
| **CPU_IPB_ENTRIES** | _natural_ | 2
|
| 397 |
|
|
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
|
| 398 |
|
|
The value has to be a power of two and has to be greater than zero.
|
| 399 |
|
|
Long linear sequences of code can benefit from an increased IPB size. For setups that use the instruction
|
| 400 |
|
|
cache (<<_icache_en>>) this generic should be set to 1.
|
| 401 |
|
|
|======
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
60 |
zero_gravi |
// ####################################################################################################################
|
| 405 |
|
|
:sectnums:
|
| 406 |
|
|
==== Physical Memory Protection (PMP)
|
| 407 |
|
|
|
| 408 |
|
|
See section <<_pmp_physical_memory_protection>> for more information.
|
| 409 |
|
|
|
| 410 |
|
|
|
| 411 |
|
|
:sectnums!:
|
| 412 |
|
|
===== _PMP_NUM_REGIONS_
|
| 413 |
|
|
|
| 414 |
|
|
[cols="4,4,2"]
|
| 415 |
|
|
[frame="all",grid="none"]
|
| 416 |
|
|
|======
|
| 417 |
|
|
| **PMP_NUM_REGIONS** | _natural_ | 0
|
| 418 |
|
|
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
|
| 419 |
|
|
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _CSR_MZEXT_PMP_ flag
|
| 420 |
|
|
in the <<_mzext>> CSR.
|
| 421 |
|
|
|======
|
| 422 |
|
|
|
| 423 |
|
|
|
| 424 |
|
|
:sectnums!:
|
| 425 |
|
|
===== _PMP_MIN_GRANULARITY_
|
| 426 |
|
|
|
| 427 |
|
|
[cols="4,4,2"]
|
| 428 |
|
|
[frame="all",grid="none"]
|
| 429 |
|
|
|======
|
| 430 |
|
|
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
|
| 431 |
|
|
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
|
| 432 |
|
|
|======
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
// ####################################################################################################################
|
| 436 |
|
|
:sectnums:
|
| 437 |
|
|
==== Hardware Performance Monitors (HPM)
|
| 438 |
|
|
|
| 439 |
|
|
See section <<_hpm_hardware_performance_monitors>> for more information.
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
:sectnums!:
|
| 443 |
|
|
===== _HPM_NUM_CNTS_
|
| 444 |
|
|
|
| 445 |
|
|
[cols="4,4,2"]
|
| 446 |
|
|
[frame="all",grid="none"]
|
| 447 |
|
|
|======
|
| 448 |
|
|
| **HPM_NUM_CNTS** | _natural_ | 0
|
| 449 |
|
|
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero no
|
| 450 |
|
|
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _CSR_MZEXT_HPM_ flag
|
| 451 |
|
|
in the <<_mzext>> CSR.
|
| 452 |
|
|
|======
|
| 453 |
|
|
|
| 454 |
|
|
|
| 455 |
|
|
:sectnums!:
|
| 456 |
|
|
===== _HPM_CNT_WIDTH_
|
| 457 |
|
|
|
| 458 |
|
|
[cols="4,4,2"]
|
| 459 |
|
|
[frame="all",grid="none"]
|
| 460 |
|
|
|======
|
| 461 |
|
|
| **HPM_CNT_WIDTH** | _natural_ | 40
|
| 462 |
|
|
3+| This generic defines the total LSB-aligned size of each HPM counter (size(`[m]hpmcounter*h`) +
|
| 463 |
|
|
size(`[m]hpmcounter*`)). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
|
| 464 |
|
|
unused MSB-aligned counter bits are hardwired to zero.
|
| 465 |
|
|
|======
|
| 466 |
|
|
|
| 467 |
|
|
|
| 468 |
|
|
// ####################################################################################################################
|
| 469 |
|
|
:sectnums:
|
| 470 |
|
|
==== Internal Instruction Memory
|
| 471 |
|
|
|
| 472 |
|
|
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
|
| 473 |
|
|
|
| 474 |
|
|
|
| 475 |
|
|
:sectnums!:
|
| 476 |
|
|
===== _MEM_INT_IMEM_EN_
|
| 477 |
|
|
|
| 478 |
|
|
[cols="4,4,2"]
|
| 479 |
|
|
[frame="all",grid="none"]
|
| 480 |
|
|
|======
|
| 481 |
62 |
zero_gravi |
| **MEM_INT_IMEM_EN** | _boolean_ | false
|
| 482 |
60 |
zero_gravi |
3+| Implement processor internal instruction memory (IMEM) when _true_.
|
| 483 |
|
|
|======
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
:sectnums!:
|
| 487 |
|
|
===== _MEM_INT_IMEM_SIZE_
|
| 488 |
|
|
|
| 489 |
|
|
[cols="4,4,2"]
|
| 490 |
|
|
[frame="all",grid="none"]
|
| 491 |
|
|
|======
|
| 492 |
|
|
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
|
| 493 |
|
|
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when _MEM_INT_IMEM_EN_ is _false_.
|
| 494 |
|
|
|======
|
| 495 |
|
|
|
| 496 |
|
|
|
| 497 |
|
|
// ####################################################################################################################
|
| 498 |
|
|
:sectnums:
|
| 499 |
|
|
==== Internal Data Memory
|
| 500 |
|
|
|
| 501 |
|
|
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
|
| 502 |
|
|
|
| 503 |
|
|
|
| 504 |
|
|
:sectnums!:
|
| 505 |
|
|
===== _MEM_INT_DMEM_EN_
|
| 506 |
|
|
|
| 507 |
|
|
[cols="4,4,2"]
|
| 508 |
|
|
[frame="all",grid="none"]
|
| 509 |
|
|
|======
|
| 510 |
62 |
zero_gravi |
| **MEM_INT_DMEM_EN** | _boolean_ | false
|
| 511 |
60 |
zero_gravi |
3+| Implement processor internal data memory (DMEM) when _true_.
|
| 512 |
|
|
|======
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
:sectnums!:
|
| 516 |
|
|
===== _MEM_INT_DMEM_SIZE_
|
| 517 |
|
|
|
| 518 |
|
|
[cols="4,4,2"]
|
| 519 |
|
|
[frame="all",grid="none"]
|
| 520 |
|
|
|======
|
| 521 |
|
|
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
|
| 522 |
|
|
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when _MEM_INT_DMEM_EN_ is _false_.
|
| 523 |
|
|
|======
|
| 524 |
|
|
|
| 525 |
|
|
|
| 526 |
|
|
// ####################################################################################################################
|
| 527 |
|
|
:sectnums:
|
| 528 |
|
|
==== Internal Cache Memory
|
| 529 |
|
|
|
| 530 |
|
|
See section <<_processor_internal_instruction_cache_icache>> for more information.
|
| 531 |
|
|
|
| 532 |
|
|
|
| 533 |
|
|
:sectnums!:
|
| 534 |
|
|
===== _ICACHE_EN_
|
| 535 |
|
|
|
| 536 |
|
|
[cols="4,4,2"]
|
| 537 |
|
|
[frame="all",grid="none"]
|
| 538 |
|
|
|======
|
| 539 |
|
|
| **ICACHE_EN** | _boolean_ | false
|
| 540 |
|
|
3+| Implement processor internal instruction cache when _true_.
|
| 541 |
|
|
|======
|
| 542 |
|
|
|
| 543 |
|
|
|
| 544 |
|
|
:sectnums!:
|
| 545 |
|
|
===== _ICACHE_NUM_BLOCK_
|
| 546 |
|
|
|
| 547 |
|
|
[cols="4,4,2"]
|
| 548 |
|
|
[frame="all",grid="none"]
|
| 549 |
|
|
|======
|
| 550 |
|
|
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
|
| 551 |
|
|
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
|
| 552 |
|
|
effect when _ICACHE_DMEM_EN_ is false.
|
| 553 |
|
|
|======
|
| 554 |
|
|
|
| 555 |
|
|
|
| 556 |
|
|
:sectnums!:
|
| 557 |
|
|
===== _ICACHE_BLOCK_SIZE_
|
| 558 |
|
|
|
| 559 |
|
|
[cols="4,4,2"]
|
| 560 |
|
|
[frame="all",grid="none"]
|
| 561 |
|
|
|======
|
| 562 |
|
|
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
|
| 563 |
|
|
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
|
| 564 |
|
|
_ICACHE_EN_ is _false_.
|
| 565 |
|
|
|======
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
:sectnums!:
|
| 569 |
|
|
===== _ICACHE_ASSOCIATIVITY_
|
| 570 |
|
|
|
| 571 |
|
|
[cols="4,4,2"]
|
| 572 |
|
|
[frame="all",grid="none"]
|
| 573 |
|
|
|======
|
| 574 |
|
|
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
|
| 575 |
|
|
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
|
| 576 |
|
|
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when _ICACHE_EN_ is _false_.
|
| 577 |
|
|
|======
|
| 578 |
|
|
|
| 579 |
|
|
|
| 580 |
|
|
// ####################################################################################################################
|
| 581 |
|
|
:sectnums:
|
| 582 |
|
|
==== External Memory Interface
|
| 583 |
|
|
|
| 584 |
|
|
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
|
| 585 |
|
|
|
| 586 |
|
|
|
| 587 |
|
|
:sectnums!:
|
| 588 |
|
|
===== _MEM_EXT_EN_
|
| 589 |
|
|
|
| 590 |
|
|
[cols="4,4,2"]
|
| 591 |
|
|
[frame="all",grid="none"]
|
| 592 |
|
|
|======
|
| 593 |
|
|
| **MEM_EXT_EN** | _boolean_ | false
|
| 594 |
|
|
3+| Implement external bus interface (WISHBONE) when _true_.
|
| 595 |
|
|
|======
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
:sectnums!:
|
| 599 |
|
|
===== _MEM_EXT_TIMEOUT_
|
| 600 |
|
|
|
| 601 |
|
|
[cols="4,4,2"]
|
| 602 |
|
|
[frame="all",grid="none"]
|
| 603 |
|
|
|======
|
| 604 |
|
|
| **MEM_EXT_TIMEOUT** | _natural_ | 255
|
| 605 |
61 |
zero_gravi |
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
|
| 606 |
60 |
zero_gravi |
|======
|
| 607 |
|
|
|
| 608 |
|
|
|
| 609 |
62 |
zero_gravi |
:sectnums!:
|
| 610 |
|
|
===== _MEM_EXT_PIPE_MODE_
|
| 611 |
|
|
|
| 612 |
|
|
[cols="4,4,2"]
|
| 613 |
|
|
[frame="all",grid="none"]
|
| 614 |
|
|
|======
|
| 615 |
|
|
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
|
| 616 |
|
|
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_; use _pipelined_ Wishbone protocol when _true_.
|
| 617 |
|
|
|======
|
| 618 |
|
|
|
| 619 |
|
|
|
| 620 |
|
|
:sectnums!:
|
| 621 |
|
|
===== _MEM_EXT_BIG_ENDIAN_
|
| 622 |
|
|
|
| 623 |
|
|
[cols="4,4,2"]
|
| 624 |
|
|
[frame="all",grid="none"]
|
| 625 |
|
|
|======
|
| 626 |
|
|
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
|
| 627 |
|
|
3+| Use BIG endian interface for external bus when _true_; use little endian interface when _false_.
|
| 628 |
|
|
|======
|
| 629 |
|
|
|
| 630 |
|
|
|
| 631 |
|
|
:sectnums!:
|
| 632 |
|
|
===== _MEM_EXT_ASYNC_RX_
|
| 633 |
|
|
|
| 634 |
|
|
[cols="4,4,2"]
|
| 635 |
|
|
[frame="all",grid="none"]
|
| 636 |
|
|
|======
|
| 637 |
|
|
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
|
| 638 |
|
|
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
|
| 639 |
|
|
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
|
| 640 |
|
|
implemented reducing access latency by one cycle.
|
| 641 |
|
|
|======
|
| 642 |
|
|
|
| 643 |
|
|
|
| 644 |
60 |
zero_gravi |
// ####################################################################################################################
|
| 645 |
|
|
:sectnums:
|
| 646 |
61 |
zero_gravi |
==== Stream Link Interface
|
| 647 |
|
|
|
| 648 |
|
|
See section <<_stream_link_interface_slink>> for more information.
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
:sectnums!:
|
| 652 |
|
|
===== _SLINK_NUM_TX_
|
| 653 |
|
|
|
| 654 |
|
|
[cols="4,4,2"]
|
| 655 |
|
|
[frame="all",grid="none"]
|
| 656 |
|
|
|======
|
| 657 |
|
|
| **SLINK_NUM_TX** | _natural_ | 0
|
| 658 |
|
|
3+| Number of TX (send) links to implement. Valid values are 0..8.
|
| 659 |
|
|
|======
|
| 660 |
|
|
|
| 661 |
|
|
|
| 662 |
|
|
:sectnums!:
|
| 663 |
|
|
===== _SLINK_NUM_RX_
|
| 664 |
|
|
|
| 665 |
|
|
[cols="4,4,2"]
|
| 666 |
|
|
[frame="all",grid="none"]
|
| 667 |
|
|
|======
|
| 668 |
|
|
| **SLINK_NUM_RX** | _natural_ | 0
|
| 669 |
|
|
3+| Number of RX (receive) links to implement. Valid values are 0..8.
|
| 670 |
|
|
|======
|
| 671 |
|
|
|
| 672 |
|
|
|
| 673 |
|
|
:sectnums!:
|
| 674 |
|
|
===== _SLINK_TX_FIFO_
|
| 675 |
|
|
|
| 676 |
|
|
[cols="4,4,2"]
|
| 677 |
|
|
[frame="all",grid="none"]
|
| 678 |
|
|
|======
|
| 679 |
|
|
| **SLINK_TX_FIFO** | _natural_ | 1
|
| 680 |
|
|
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
|
| 681 |
|
|
|======
|
| 682 |
|
|
|
| 683 |
|
|
|
| 684 |
|
|
:sectnums!:
|
| 685 |
|
|
===== _SLINK_RX_FIFO_
|
| 686 |
|
|
|
| 687 |
|
|
[cols="4,4,2"]
|
| 688 |
|
|
[frame="all",grid="none"]
|
| 689 |
|
|
|======
|
| 690 |
|
|
| **SLINK_RX_FIFO** | _natural_ | 1
|
| 691 |
|
|
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
|
| 692 |
|
|
|======
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
// ####################################################################################################################
|
| 696 |
|
|
:sectnums:
|
| 697 |
|
|
==== External Interrupt Controller
|
| 698 |
|
|
|
| 699 |
|
|
See section <<_external_interrupt_controller_xirq>> for more information.
|
| 700 |
|
|
|
| 701 |
|
|
|
| 702 |
|
|
:sectnums!:
|
| 703 |
|
|
===== _XIRQ_NUM_CH_
|
| 704 |
|
|
|
| 705 |
|
|
[cols="4,4,2"]
|
| 706 |
|
|
[frame="all",grid="none"]
|
| 707 |
|
|
|======
|
| 708 |
|
|
| **XIRQ_NUM_CH** | _natural_ | 0
|
| 709 |
|
|
3+| Number of external interrupt channels o implement. Valid values are 0..32.
|
| 710 |
|
|
|======
|
| 711 |
|
|
|
| 712 |
|
|
|
| 713 |
|
|
:sectnums!:
|
| 714 |
|
|
===== _XIRQ_TRIGGER_TYPE_
|
| 715 |
|
|
|
| 716 |
|
|
[cols="4,4,2"]
|
| 717 |
|
|
[frame="all",grid="none"]
|
| 718 |
|
|
|======
|
| 719 |
|
|
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
| 720 |
|
|
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
|
| 721 |
|
|
_XIRQ_TRIGGER_POLARITY_ generic is used to specify the actual level (high/low) or edge (falling/rising).
|
| 722 |
|
|
|======
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
|
|
:sectnums!:
|
| 726 |
|
|
===== _XIRQ_TRIGGER_POLARITY_
|
| 727 |
|
|
|
| 728 |
|
|
[cols="4,4,2"]
|
| 729 |
|
|
[frame="all",grid="none"]
|
| 730 |
|
|
|======
|
| 731 |
|
|
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
|
| 732 |
|
|
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
|
| 733 |
|
|
'1' = high-level/rising-edge. _XIRQ_TRIGGER_TYPE_ generic is used to specify the actual type (level or edge).
|
| 734 |
|
|
|======
|
| 735 |
|
|
|
| 736 |
|
|
|
| 737 |
|
|
// ####################################################################################################################
|
| 738 |
|
|
:sectnums:
|
| 739 |
60 |
zero_gravi |
==== Processor Peripheral/IO Modules
|
| 740 |
|
|
|
| 741 |
|
|
See section <<_processor_internal_modules>> for more information.
|
| 742 |
|
|
|
| 743 |
|
|
|
| 744 |
|
|
:sectnums!:
|
| 745 |
|
|
===== _IO_GPIO_EN_
|
| 746 |
|
|
|
| 747 |
|
|
[cols="4,4,2"]
|
| 748 |
|
|
[frame="all",grid="none"]
|
| 749 |
|
|
|======
|
| 750 |
62 |
zero_gravi |
| **IO_GPIO_EN** | _boolean_ | false
|
| 751 |
60 |
zero_gravi |
3+| Implement general purpose input/output port unit (GPIO) when _true_.
|
| 752 |
|
|
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
|
| 753 |
|
|
|======
|
| 754 |
|
|
|
| 755 |
|
|
|
| 756 |
|
|
:sectnums!:
|
| 757 |
|
|
===== _IO_MTIME_EN_
|
| 758 |
|
|
|
| 759 |
|
|
[cols="4,4,2"]
|
| 760 |
|
|
[frame="all",grid="none"]
|
| 761 |
|
|
|======
|
| 762 |
62 |
zero_gravi |
| **IO_MTIME_EN** | _boolean_ | false
|
| 763 |
60 |
zero_gravi |
3+| Implement machine system timer (MTIME) when _true_.
|
| 764 |
|
|
See section <<_machine_system_timer_mtime>> for more information.
|
| 765 |
|
|
|======
|
| 766 |
|
|
|
| 767 |
|
|
|
| 768 |
|
|
:sectnums!:
|
| 769 |
|
|
===== _IO_UART0_EN_
|
| 770 |
|
|
|
| 771 |
|
|
[cols="4,4,2"]
|
| 772 |
|
|
[frame="all",grid="none"]
|
| 773 |
|
|
|======
|
| 774 |
62 |
zero_gravi |
| **IO_UART0_EN** | _boolean_ | false
|
| 775 |
60 |
zero_gravi |
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
|
| 776 |
|
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
| 777 |
|
|
more information.
|
| 778 |
|
|
|======
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
:sectnums!:
|
| 782 |
|
|
===== _IO_UART1_EN_
|
| 783 |
|
|
|
| 784 |
|
|
[cols="4,4,2"]
|
| 785 |
|
|
[frame="all",grid="none"]
|
| 786 |
|
|
|======
|
| 787 |
62 |
zero_gravi |
| **IO_UART1_EN** | _boolean_ | false
|
| 788 |
61 |
zero_gravi |
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
|
| 789 |
60 |
zero_gravi |
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
|
| 790 |
|
|
|======
|
| 791 |
|
|
|
| 792 |
|
|
|
| 793 |
|
|
:sectnums!:
|
| 794 |
|
|
===== _IO_SPI_EN_
|
| 795 |
|
|
|
| 796 |
|
|
[cols="4,4,2"]
|
| 797 |
|
|
[frame="all",grid="none"]
|
| 798 |
|
|
|======
|
| 799 |
62 |
zero_gravi |
| **IO_SPI_EN** | _boolean_ | false
|
| 800 |
60 |
zero_gravi |
3+| Implement serial peripheral interface controller (SPI) when _true_.
|
| 801 |
|
|
See section <<_serial_peripheral_interface_controller_spi>> for more information.
|
| 802 |
|
|
|======
|
| 803 |
|
|
|
| 804 |
|
|
|
| 805 |
|
|
:sectnums!:
|
| 806 |
|
|
===== _IO_TWI_EN_
|
| 807 |
|
|
|
| 808 |
|
|
[cols="4,4,2"]
|
| 809 |
|
|
[frame="all",grid="none"]
|
| 810 |
|
|
|======
|
| 811 |
62 |
zero_gravi |
| **IO_TWI_EN** | _boolean_ | false
|
| 812 |
60 |
zero_gravi |
3+| Implement two-wire interface controller (TWI) when _true_.
|
| 813 |
|
|
See section <<_two_wire_serial_interface_controller_twi>> for
|
| 814 |
|
|
more information.
|
| 815 |
|
|
|======
|
| 816 |
|
|
|
| 817 |
|
|
|
| 818 |
|
|
:sectnums!:
|
| 819 |
|
|
===== _IO_PWM_NUM_CH_
|
| 820 |
|
|
|
| 821 |
|
|
[cols="4,4,2"]
|
| 822 |
|
|
[frame="all",grid="none"]
|
| 823 |
|
|
|======
|
| 824 |
62 |
zero_gravi |
| **IO_PWM_NUM_CH** | _natural_ | 0
|
| 825 |
60 |
zero_gravi |
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
|
| 826 |
|
|
See section <<_pulse_width_modulation_controller_pwm>> for more information.
|
| 827 |
|
|
|======
|
| 828 |
|
|
|
| 829 |
|
|
|
| 830 |
|
|
:sectnums!:
|
| 831 |
|
|
===== _IO_WDT_EN_
|
| 832 |
|
|
|
| 833 |
|
|
[cols="4,4,2"]
|
| 834 |
|
|
[frame="all",grid="none"]
|
| 835 |
|
|
|======
|
| 836 |
62 |
zero_gravi |
| **IO_WDT_EN** | _boolean_ | false
|
| 837 |
60 |
zero_gravi |
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
|
| 838 |
|
|
information.
|
| 839 |
|
|
|======
|
| 840 |
|
|
|
| 841 |
|
|
|
| 842 |
|
|
:sectnums!:
|
| 843 |
|
|
===== _IO_TRNG_EN_
|
| 844 |
|
|
|
| 845 |
|
|
[cols="4,4,2"]
|
| 846 |
|
|
[frame="all",grid="none"]
|
| 847 |
|
|
|======
|
| 848 |
|
|
| **IO_TRNG_EN** | _boolean_ | false
|
| 849 |
|
|
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
|
| 850 |
|
|
|======
|
| 851 |
|
|
|
| 852 |
|
|
|
| 853 |
|
|
:sectnums!:
|
| 854 |
|
|
===== _IO_CFS_EN_
|
| 855 |
|
|
|
| 856 |
|
|
[cols="4,4,2"]
|
| 857 |
|
|
[frame="all",grid="none"]
|
| 858 |
|
|
|======
|
| 859 |
|
|
| **IO_CFS_EN** | _boolean_ | false
|
| 860 |
|
|
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
|
| 861 |
|
|
|======
|
| 862 |
|
|
|
| 863 |
|
|
|
| 864 |
|
|
:sectnums!:
|
| 865 |
|
|
===== _IO_CFS_CONFIG_
|
| 866 |
|
|
|
| 867 |
|
|
[cols="4,4,2"]
|
| 868 |
|
|
[frame="all",grid="none"]
|
| 869 |
|
|
|======
|
| 870 |
|
|
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
|
| 871 |
|
|
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
|
| 872 |
|
|
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
|
| 873 |
|
|
|======
|
| 874 |
|
|
|
| 875 |
|
|
|
| 876 |
|
|
:sectnums!:
|
| 877 |
|
|
===== _IO_CFS_IN_SIZE_
|
| 878 |
|
|
|
| 879 |
|
|
[cols="4,4,2"]
|
| 880 |
|
|
[frame="all",grid="none"]
|
| 881 |
|
|
|======
|
| 882 |
|
|
| **IO_CFS_IN_SIZE** | _positive_ | 32
|
| 883 |
|
|
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
|
| 884 |
|
|
|======
|
| 885 |
|
|
|
| 886 |
|
|
|
| 887 |
|
|
:sectnums!:
|
| 888 |
|
|
===== _IO_CFS_OUT_SIZE_
|
| 889 |
|
|
|
| 890 |
|
|
[cols="4,4,2"]
|
| 891 |
|
|
[frame="all",grid="none"]
|
| 892 |
|
|
|======
|
| 893 |
|
|
| **IO_CFS_OUT_SIZE** | _positive_ | 32
|
| 894 |
|
|
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
|
| 895 |
|
|
|======
|
| 896 |
|
|
|
| 897 |
|
|
|
| 898 |
|
|
:sectnums!:
|
| 899 |
|
|
===== _IO_NEOLED_EN_
|
| 900 |
|
|
|
| 901 |
|
|
[cols="4,4,2"]
|
| 902 |
|
|
[frame="all",grid="none"]
|
| 903 |
|
|
|======
|
| 904 |
62 |
zero_gravi |
| **IO_NEOLED_EN** | _boolean_ | false
|
| 905 |
60 |
zero_gravi |
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
|
| 906 |
|
|
See section <<_smart_led_interface_neoled>> for more information.
|
| 907 |
|
|
|======
|
| 908 |
|
|
|
| 909 |
|
|
|
| 910 |
62 |
zero_gravi |
:sectnums!:
|
| 911 |
|
|
===== _IO_NEOLED_TX_FIFO_
|
| 912 |
|
|
|
| 913 |
|
|
[cols="4,4,2"]
|
| 914 |
|
|
[frame="all",grid="none"]
|
| 915 |
|
|
|======
|
| 916 |
|
|
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
|
| 917 |
|
|
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
|
| 918 |
|
|
See section <<_smart_led_interface_neoled>> for more information.
|
| 919 |
|
|
|======
|
| 920 |
|
|
|
| 921 |
|
|
|
| 922 |
|
|
|
| 923 |
60 |
zero_gravi |
<<<
|
| 924 |
|
|
// ####################################################################################################################
|
| 925 |
|
|
:sectnums:
|
| 926 |
|
|
=== Processor Interrupts
|
| 927 |
|
|
|
| 928 |
61 |
zero_gravi |
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
|
| 929 |
60 |
zero_gravi |
|
| 930 |
|
|
|
| 931 |
61 |
zero_gravi |
:sectnums:
|
| 932 |
|
|
==== RISC-V Standard Interrupts
|
| 933 |
|
|
|
| 934 |
62 |
zero_gravi |
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
|
| 935 |
61 |
zero_gravi |
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
|
| 936 |
|
|
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
|
| 937 |
|
|
<<_traps_exceptions_and_interrupts>> for more information.
|
| 938 |
60 |
zero_gravi |
|
| 939 |
61 |
zero_gravi |
[cols="<3,^2,<11"]
|
| 940 |
|
|
[options="header",grid="rows"]
|
| 941 |
|
|
|=======================
|
| 942 |
|
|
| Top signal | Width | Description
|
| 943 |
|
|
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
|
| 944 |
|
|
| `msw_irq_i` | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
|
| 945 |
|
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
| 946 |
|
|
|=======================
|
| 947 |
60 |
zero_gravi |
|
| 948 |
62 |
zero_gravi |
[IMPORTANT]
|
| 949 |
|
|
These IRQs trigger on a **rising-edge**.
|
| 950 |
61 |
zero_gravi |
|
| 951 |
|
|
|
| 952 |
|
|
:sectnums:
|
| 953 |
|
|
==== Non-Maskable Interrupt
|
| 954 |
|
|
|
| 955 |
|
|
[cols="<3,^2,<11"]
|
| 956 |
|
|
[options="header",grid="rows"]
|
| 957 |
|
|
|=======================
|
| 958 |
|
|
| Top signal | Width | Description
|
| 959 |
|
|
| `nm_irq_i` | 1 | Non-maskable interrupt.
|
| 960 |
|
|
|=======================
|
| 961 |
|
|
|
| 962 |
|
|
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
|
| 963 |
|
|
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
|
| 964 |
|
|
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
|
| 965 |
|
|
|
| 966 |
62 |
zero_gravi |
[IMPORTANT]
|
| 967 |
|
|
This IRQ triggers on a **rising-edge**.
|
| 968 |
61 |
zero_gravi |
|
| 969 |
|
|
|
| 970 |
|
|
:sectnums:
|
| 971 |
|
|
==== Platform External Interrupts
|
| 972 |
|
|
|
| 973 |
|
|
[cols="<3,^2,<11"]
|
| 974 |
|
|
[options="header",grid="rows"]
|
| 975 |
|
|
|=======================
|
| 976 |
|
|
| Top signal | Width | Description
|
| 977 |
|
|
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
|
| 978 |
|
|
|=======================
|
| 979 |
|
|
|
| 980 |
|
|
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
|
| 981 |
|
|
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
|
| 982 |
|
|
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
|
| 983 |
|
|
|
| 984 |
|
|
[NOTE]
|
| 985 |
62 |
zero_gravi |
The trigger for these interrupt can be defined via generics. See section
|
| 986 |
61 |
zero_gravi |
<<_external_interrupt_controller_xirq>> for more information.
|
| 987 |
|
|
|
| 988 |
|
|
|
| 989 |
|
|
:sectnums:
|
| 990 |
|
|
==== NEORV32-Specific Fast Interrupt Requests
|
| 991 |
|
|
|
| 992 |
60 |
zero_gravi |
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
|
| 993 |
61 |
zero_gravi |
(`FIRQ0` – `FIRQ15`). These are used for _processor-internal_ modules only (for example for the communication
|
| 994 |
|
|
interfaces to signal "available incoming data" or "ready to send new data").
|
| 995 |
60 |
zero_gravi |
|
| 996 |
61 |
zero_gravi |
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
|
| 997 |
|
|
the according FIRQ priority; 0 = highest, 15 = lowest):
|
| 998 |
60 |
zero_gravi |
|
| 999 |
|
|
.NEORV32 fast interrupt channel mapping
|
| 1000 |
|
|
[cols="^1,<2,<7"]
|
| 1001 |
|
|
[options="header",grid="rows"]
|
| 1002 |
|
|
|=======================
|
| 1003 |
|
|
| Channel | Source | Description
|
| 1004 |
61 |
zero_gravi |
| 0 | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
|
| 1005 |
|
|
| 1 | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
|
| 1006 |
|
|
| 2 | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
|
| 1007 |
|
|
| 3 | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
|
| 1008 |
|
|
| 4 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
|
| 1009 |
|
|
| 5 | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
|
| 1010 |
|
|
| 6 | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
|
| 1011 |
|
|
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 1012 |
|
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 1013 |
|
|
| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
|
| 1014 |
|
|
| 10 | <<_stream_link_interface_slink,SLINK>> | RX data received
|
| 1015 |
|
|
| 11 | <<_stream_link_interface_slink,SLINK>> | TX data send
|
| 1016 |
62 |
zero_gravi |
| 12:15 | - | _reserved_, will never fire
|
| 1017 |
60 |
zero_gravi |
|=======================
|
| 1018 |
|
|
|
| 1019 |
|
|
|
| 1020 |
|
|
|
| 1021 |
|
|
<<<
|
| 1022 |
|
|
// ####################################################################################################################
|
| 1023 |
|
|
:sectnums:
|
| 1024 |
|
|
=== Address Space
|
| 1025 |
|
|
|
| 1026 |
61 |
zero_gravi |
The NEORV32 Processor provides 32-bit physical addresses accessing up to 4GB of address space.
|
| 1027 |
|
|
By default, this address space is divided into four main regions:
|
| 1028 |
60 |
zero_gravi |
|
| 1029 |
61 |
zero_gravi |
1. **Instruction address space** – for instructions (=code) and constants. A configurable section of this address space is used by
|
| 1030 |
|
|
internal and/or external _instruction memory_ (IMEM).
|
| 1031 |
|
|
2. **Data address space** – for application runtime data (heap, stack, etc.). A configurable section of this address space is used by
|
| 1032 |
|
|
internal and/or external _data memory_ (DMEM).
|
| 1033 |
|
|
3. **Bootloader address space**. A _fixed_ section of this address space is used by
|
| 1034 |
|
|
internal _bootloader memory_ (BOOTLDROM).
|
| 1035 |
|
|
4. **IO/peripheral address space** – for the processor-internal IO/peripheral devices (e.g., UART).
|
| 1036 |
60 |
zero_gravi |
|
| 1037 |
|
|
[TIP]
|
| 1038 |
|
|
These four memory regions are handled by the linker when compiling a NEORV32 executable.
|
| 1039 |
|
|
See section <<_executable_image_format>> for more information.
|
| 1040 |
|
|
|
| 1041 |
61 |
zero_gravi |
.NEORV32 processor - address space (default configuration)
|
| 1042 |
|
|
image::address_space.png[900]
|
| 1043 |
60 |
zero_gravi |
|
| 1044 |
|
|
|
| 1045 |
|
|
:sectnums:
|
| 1046 |
|
|
==== CPU Data and Instruction Access
|
| 1047 |
|
|
|
| 1048 |
|
|
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
|
| 1049 |
|
|
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
|
| 1050 |
|
|
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
|
| 1051 |
|
|
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
|
| 1052 |
|
|
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
|
| 1053 |
|
|
setup a modified von-Neumann architecture.
|
| 1054 |
|
|
|
| 1055 |
|
|
.Processor-internal bus architecture
|
| 1056 |
|
|
image::neorv32_bus.png[1300]
|
| 1057 |
|
|
|
| 1058 |
|
|
[NOTE]
|
| 1059 |
|
|
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
|
| 1060 |
|
|
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
|
| 1061 |
|
|
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
|
| 1062 |
|
|
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
|
| 1063 |
|
|
accesses.
|
| 1064 |
|
|
|
| 1065 |
|
|
[IMPORTANT]
|
| 1066 |
|
|
Please note that all processor-internal components including the peripheral/IO devices can also be
|
| 1067 |
|
|
accessed from programs running in less-privileged user mode. For example, if the system relies on
|
| 1068 |
|
|
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
|
| 1069 |
|
|
configuration corrupting this interrupt. This kind of security issues can be compensated using the
|
| 1070 |
|
|
PMP system (see <<_machine_physical_memory_protection>>).
|
| 1071 |
|
|
|
| 1072 |
61 |
zero_gravi |
|
| 1073 |
60 |
zero_gravi |
:sectnums:
|
| 1074 |
61 |
zero_gravi |
==== Address Space Layout
|
| 1075 |
|
|
|
| 1076 |
|
|
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
|
| 1077 |
|
|
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
|
| 1078 |
|
|
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
|
| 1079 |
|
|
`rtl/core/neorv32_package.vhd`:
|
| 1080 |
|
|
|
| 1081 |
|
|
[source,vhdl]
|
| 1082 |
|
|
----
|
| 1083 |
|
|
-- Architecture Configuration ----------------------------------------------------
|
| 1084 |
|
|
-- ----------------------------------------------------------------------------------
|
| 1085 |
|
|
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
|
| 1086 |
|
|
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
|
| 1087 |
|
|
----
|
| 1088 |
|
|
|
| 1089 |
|
|
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
|
| 1090 |
|
|
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
|
| 1091 |
|
|
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
|
| 1092 |
|
|
are _aligned_ to a 4-byte boundary.
|
| 1093 |
|
|
|
| 1094 |
|
|
[NOTE]
|
| 1095 |
|
|
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
|
| 1096 |
|
|
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
|
| 1097 |
|
|
applications – even if the bootloader or all IO devices are not implemented - without modifying the core's
|
| 1098 |
|
|
hardware sources.
|
| 1099 |
|
|
|
| 1100 |
|
|
|
| 1101 |
|
|
:sectnums:
|
| 1102 |
60 |
zero_gravi |
==== Physical Memory Attributes
|
| 1103 |
|
|
|
| 1104 |
61 |
zero_gravi |
The processor setup defines fixed attributes for the four processor-internal address space regions.
|
| 1105 |
|
|
Accessing a memory region in a way that violates any of these attributes will raise an according
|
| 1106 |
|
|
access exception..
|
| 1107 |
60 |
zero_gravi |
|
| 1108 |
|
|
* `r` – read access (from CPU data access interface, e.g. via "load")
|
| 1109 |
|
|
* `w` – write access (from CPU data access interface, e.g. via "store")
|
| 1110 |
|
|
* `x` – execute access (from CPU instruction fetch interface)
|
| 1111 |
|
|
* `a` – atomic access (from CPU data access interface)
|
| 1112 |
|
|
* `8` – byte (8-bit)-accessible (when writing)
|
| 1113 |
|
|
* `16` – half-word (16-bit)-accessible (when writing)
|
| 1114 |
|
|
* `32` – word (32-bit)-accessible (when writing)
|
| 1115 |
|
|
|
| 1116 |
61 |
zero_gravi |
[NOTE]
|
| 1117 |
|
|
Read accesses (i.e. loads) can always access data in word, half-word and byte quantities (requiring an accordingly aligned address).
|
| 1118 |
60 |
zero_gravi |
|
| 1119 |
|
|
[cols="^1,^2,^2,^3,^2"]
|
| 1120 |
|
|
[options="header",grid="rows"]
|
| 1121 |
|
|
|=======================
|
| 1122 |
|
|
| # | Region | Base address | Size | Attributes
|
| 1123 |
|
|
| 4 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
|
| 1124 |
|
|
| 3 | bootloader ROM | 0xffff0000 | up to 32kB| `r/x/a`
|
| 1125 |
|
|
| 2 | DMEM | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
|
| 1126 |
|
|
| 1 | IMEM | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
|
| 1127 |
|
|
|=======================
|
| 1128 |
|
|
|
| 1129 |
61 |
zero_gravi |
[TIP]
|
| 1130 |
|
|
The following table shows the provided physical memory attributes of each region. Additional attributes (for example
|
| 1131 |
|
|
controlling certain right for specific address space regions) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
|
| 1132 |
60 |
zero_gravi |
|
| 1133 |
|
|
|
| 1134 |
|
|
:sectnums:
|
| 1135 |
61 |
zero_gravi |
==== Memory Configuration
|
| 1136 |
60 |
zero_gravi |
|
| 1137 |
61 |
zero_gravi |
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
|
| 1138 |
|
|
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
|
| 1139 |
|
|
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
|
| 1140 |
|
|
the internal ones. The figure below show some exemplary memory configurations.
|
| 1141 |
60 |
zero_gravi |
|
| 1142 |
61 |
zero_gravi |
.Exemplary memory configurations
|
| 1143 |
|
|
image::neorv32_memory_configurations.png[800]
|
| 1144 |
60 |
zero_gravi |
|
| 1145 |
61 |
zero_gravi |
:sectnums!:
|
| 1146 |
|
|
===== Internal Memories
|
| 1147 |
|
|
|
| 1148 |
|
|
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
|
| 1149 |
|
|
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
|
| 1150 |
|
|
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
|
| 1151 |
|
|
|
| 1152 |
60 |
zero_gravi |
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
|
| 1153 |
|
|
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
|
| 1154 |
|
|
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
|
| 1155 |
|
|
implemented.
|
| 1156 |
|
|
|
| 1157 |
61 |
zero_gravi |
[TIP]
|
| 1158 |
|
|
The default processor setup uses only _internal_ memories.
|
| 1159 |
60 |
zero_gravi |
|
| 1160 |
61 |
zero_gravi |
[NOTE]
|
| 1161 |
|
|
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
|
| 1162 |
|
|
a "dead address space" between it and the DMEM. This provides an additional safety feature
|
| 1163 |
|
|
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
|
| 1164 |
|
|
any access to the "dead address space" in between will raise an exception that can be caught
|
| 1165 |
|
|
by the runtime environment.
|
| 1166 |
60 |
zero_gravi |
|
| 1167 |
61 |
zero_gravi |
:sectnums!:
|
| 1168 |
|
|
===== External Memories
|
| 1169 |
|
|
|
| 1170 |
|
|
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
|
| 1171 |
|
|
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
|
| 1172 |
|
|
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
|
| 1173 |
|
|
|
| 1174 |
|
|
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
|
| 1175 |
|
|
via the processor's bus interface to external components:
|
| 1176 |
|
|
|
| 1177 |
60 |
zero_gravi |
* access to the processor-internal IMEM and processor-internal IMEM is implemented
|
| 1178 |
|
|
* access to the processor-internal DMEM and processor-internal DMEM is implemented
|
| 1179 |
|
|
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
|
| 1180 |
|
|
|
| 1181 |
61 |
zero_gravi |
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
|
| 1182 |
|
|
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
|
| 1183 |
|
|
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
|
| 1184 |
|
|
memory system.
|
| 1185 |
60 |
zero_gravi |
|
| 1186 |
61 |
zero_gravi |
[NOTE]
|
| 1187 |
|
|
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
|
| 1188 |
|
|
the internal peripheral address space will trigger a bus access fault exception.
|
| 1189 |
60 |
zero_gravi |
|
| 1190 |
|
|
|
| 1191 |
61 |
zero_gravi |
:sectnums:
|
| 1192 |
|
|
==== Boot Configuration
|
| 1193 |
|
|
|
| 1194 |
|
|
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
|
| 1195 |
|
|
The figure below shows the exemplary concepts for the two most common boot scenarios.
|
| 1196 |
|
|
|
| 1197 |
|
|
.NEORV32 boot configurations
|
| 1198 |
|
|
image::neorv32_boot_configurations.png[800]
|
| 1199 |
|
|
|
| 1200 |
|
|
[NOTE]
|
| 1201 |
|
|
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
|
| 1202 |
|
|
relevant for the boot configuration itself. Hence, it is not further illustrated here.
|
| 1203 |
|
|
|
| 1204 |
|
|
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
|
| 1205 |
|
|
<<_int_bootloader_en>> generic If this generic is set **true** the _indirect_ boot scenario is used. This is also the
|
| 1206 |
|
|
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
|
| 1207 |
|
|
|
| 1208 |
|
|
[NOTE]
|
| 1209 |
|
|
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
|
| 1210 |
|
|
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
|
| 1211 |
|
|
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
|
| 1212 |
|
|
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
|
| 1213 |
|
|
store it to external _data_ memory and transfers CPU control to that.
|
| 1214 |
|
|
|
| 1215 |
|
|
:sectnums!:
|
| 1216 |
|
|
===== Indirect Boot
|
| 1217 |
|
|
|
| 1218 |
|
|
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
|
| 1219 |
|
|
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
|
| 1220 |
|
|
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
|
| 1221 |
|
|
|
| 1222 |
|
|
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
|
| 1223 |
|
|
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
|
| 1224 |
|
|
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
|
| 1225 |
|
|
RAM so the bootloader can write the actual executable to it.
|
| 1226 |
|
|
|
| 1227 |
|
|
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
|
| 1228 |
|
|
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
|
| 1229 |
|
|
write the executable to the processor-external memory.
|
| 1230 |
|
|
|
| 1231 |
|
|
:sectnums!:
|
| 1232 |
|
|
===== Direct Boot
|
| 1233 |
|
|
|
| 1234 |
|
|
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
|
| 1235 |
|
|
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
|
| 1236 |
|
|
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
|
| 1237 |
|
|
in order to provide an executable _in_ memory.
|
| 1238 |
|
|
|
| 1239 |
|
|
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
|
| 1240 |
|
|
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
|
| 1241 |
|
|
|
| 1242 |
|
|
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
|
| 1243 |
|
|
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
|
| 1244 |
|
|
|
| 1245 |
|
|
|
| 1246 |
|
|
|
| 1247 |
60 |
zero_gravi |
<<<
|
| 1248 |
|
|
// ####################################################################################################################
|
| 1249 |
|
|
:sectnums:
|
| 1250 |
|
|
=== Processor-Internal Modules
|
| 1251 |
|
|
|
| 1252 |
|
|
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
|
| 1253 |
|
|
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
|
| 1254 |
|
|
system implements an internal reset generator and a global clock generator/divider.
|
| 1255 |
|
|
|
| 1256 |
|
|
**Internal Reset Generator**
|
| 1257 |
|
|
|
| 1258 |
|
|
Most processor-internal modules – except for the CPU and the watchdog timer – do not have a dedicated
|
| 1259 |
|
|
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
|
| 1260 |
|
|
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
|
| 1261 |
|
|
modules to ensure a clean system reset state.
|
| 1262 |
|
|
|
| 1263 |
|
|
The hardware reset signal of the processor can either be
|
| 1264 |
|
|
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
|
| 1265 |
|
|
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
|
| 1266 |
|
|
clock cycles.
|
| 1267 |
|
|
|
| 1268 |
|
|
**Internal Clock Divider**
|
| 1269 |
|
|
|
| 1270 |
|
|
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
|
| 1271 |
|
|
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
|
| 1272 |
|
|
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
|
| 1273 |
|
|
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
|
| 1274 |
|
|
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
|
| 1275 |
|
|
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
|
| 1276 |
|
|
power.
|
| 1277 |
|
|
|
| 1278 |
|
|
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
|
| 1279 |
|
|
according control register to select one out of the eight available clocks. The mapping of the prescaler select
|
| 1280 |
|
|
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
|
| 1281 |
|
|
from the top entity's `clk_i` signal.
|
| 1282 |
|
|
|
| 1283 |
|
|
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
|
| 1284 |
|
|
[grid="rows"]
|
| 1285 |
|
|
|=======================
|
| 1286 |
|
|
| Prescaler bits: | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
|
| 1287 |
|
|
| Resulting clock: | _f/2_ | _f/4_ | _f/8_ | _f/64_ | _f/128_ | _f/1024_| _f/2048_| _f/4096_
|
| 1288 |
|
|
|=======================
|
| 1289 |
|
|
|
| 1290 |
|
|
**Peripheral / IO Devices**
|
| 1291 |
|
|
|
| 1292 |
|
|
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
|
| 1293 |
|
|
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
|
| 1294 |
|
|
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
|
| 1295 |
|
|
library abstract the specific memory layout for the user.
|
| 1296 |
|
|
|
| 1297 |
|
|
[IMPORTANT]
|
| 1298 |
|
|
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
|
| 1299 |
|
|
load/store access fault exception is triggered.
|
| 1300 |
|
|
|
| 1301 |
|
|
[IMPORTANT]
|
| 1302 |
|
|
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
|
| 1303 |
|
|
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
|
| 1304 |
|
|
Processor-internal memories as well as modules connected to the external memory interface can still
|
| 1305 |
|
|
be written with a byte-wide granularity.
|
| 1306 |
|
|
|
| 1307 |
|
|
[TIP]
|
| 1308 |
|
|
You should use the provided core software library to interact with the peripheral devices. This
|
| 1309 |
|
|
prevents incompatibilities with future versions, since the hardware driver functions handle all the
|
| 1310 |
|
|
register and register bit accesses.
|
| 1311 |
|
|
|
| 1312 |
|
|
[TIP]
|
| 1313 |
|
|
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
|
| 1314 |
|
|
writing zero to the unit's control register. A general software-based reset of all devices is done by the
|
| 1315 |
|
|
application start-up code `crt0.S`.
|
| 1316 |
|
|
|
| 1317 |
|
|
**Nomenclature for the Peripheral / IO Devices Listing**
|
| 1318 |
|
|
|
| 1319 |
|
|
Each peripheral device chapter features a register map showing accessible control and data registers of the
|
| 1320 |
|
|
according device including the implemented control and status bits. You can directly interact with these
|
| 1321 |
|
|
registers/bits via the provided _C-code defines_. These defines are set in the main processor core library
|
| 1322 |
|
|
include file `sw/lib/include/neorv32.h`. The registers and/or register bits, which can be accessed
|
| 1323 |
|
|
directly using plain C-code, are marked with a "[C]".
|
| 1324 |
|
|
|
| 1325 |
|
|
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
|
| 1326 |
|
|
available:
|
| 1327 |
|
|
|
| 1328 |
|
|
* `r/w` registers / bits can be read and written
|
| 1329 |
|
|
* `r/-` registers / bits are read-only; any write access to them has no effect
|
| 1330 |
|
|
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
|
| 1331 |
|
|
|
| 1332 |
|
|
[TIP]
|
| 1333 |
|
|
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
|
| 1334 |
|
|
/ bits are always read as zero. A write access to them has no effect, but user programs should only
|
| 1335 |
|
|
write zero to them to keep compatible with future extension.
|
| 1336 |
|
|
|
| 1337 |
|
|
[TIP]
|
| 1338 |
|
|
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
|
| 1339 |
|
|
written. When reading data from a write-only register the result is undefined.
|
| 1340 |
|
|
|
| 1341 |
|
|
|
| 1342 |
|
|
include::soc_imem.adoc[]
|
| 1343 |
|
|
|
| 1344 |
|
|
include::soc_dmem.adoc[]
|
| 1345 |
|
|
|
| 1346 |
|
|
include::soc_bootrom.adoc[]
|
| 1347 |
|
|
|
| 1348 |
|
|
include::soc_icache.adoc[]
|
| 1349 |
|
|
|
| 1350 |
|
|
include::soc_wishbone.adoc[]
|
| 1351 |
|
|
|
| 1352 |
61 |
zero_gravi |
include::soc_slink.adoc[]
|
| 1353 |
|
|
|
| 1354 |
60 |
zero_gravi |
include::soc_gpio.adoc[]
|
| 1355 |
|
|
|
| 1356 |
|
|
include::soc_wdt.adoc[]
|
| 1357 |
|
|
|
| 1358 |
|
|
include::soc_mtime.adoc[]
|
| 1359 |
|
|
|
| 1360 |
|
|
include::soc_uart.adoc[]
|
| 1361 |
|
|
|
| 1362 |
|
|
include::soc_spi.adoc[]
|
| 1363 |
|
|
|
| 1364 |
|
|
include::soc_twi.adoc[]
|
| 1365 |
|
|
|
| 1366 |
|
|
include::soc_pwm.adoc[]
|
| 1367 |
|
|
|
| 1368 |
|
|
include::soc_trng.adoc[]
|
| 1369 |
|
|
|
| 1370 |
|
|
include::soc_cfs.adoc[]
|
| 1371 |
|
|
|
| 1372 |
|
|
include::soc_neoled.adoc[]
|
| 1373 |
|
|
|
| 1374 |
61 |
zero_gravi |
include::soc_xirq.adoc[]
|
| 1375 |
|
|
|
| 1376 |
60 |
zero_gravi |
include::soc_sysinfo.adoc[]
|
| 1377 |
|
|
|
| 1378 |
|
|
|
