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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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6 
The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
7 
interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
12 
 
13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS)
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
24 
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
25 
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
29 
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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31 
 
32 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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[IMPORTAN]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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since all control signals have defined level.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 4 | out | pulse-width modulated channels
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **<<_processor_interrupts, External Interrupts>>**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **<<_processor_interrupts, CPU Interrupts>>**
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| `nm_irq_i`    | 1 | in | non-maskable interrupt, rising-edge-triggered
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), rising-edge-triggered
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), rising-edge-triggered
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), rising-edge-triggered
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|=======================
120 
 
121 
 
122 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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127 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
130 
 
131 
[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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**More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
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138 
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the `misa` and the
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i_SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
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163 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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168 
See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
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Note that hart IDs must be unique within a system.
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
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219 
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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[TIP]
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See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
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(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
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can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
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240 
 
241 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
243 
 
244 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
251 
 
252 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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256 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
259 
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
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requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
262 
requires a different application binary interface (ABI).
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|======
264 
 
265 
 
266 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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269 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
274 
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
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If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
276 
to DSP slices via the <<_fast_mul_en>> generic.
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See section <<_m_integer_multiplication_and_division>> for more information.
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|======
279 
 
280 
 
281 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_U_
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284 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
287 
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
291 
 
292 
 
293 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zbb_
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296 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
299 
| **CPU_EXTENSION_RISCV_Zbb** | _boolean_ | false
300 
3+| Implement the `Zbb` _basic_ bit-manipulation sub-extension when _true_.
301 
See section <<_zbb_basic_bit_manipulation_operations>> for more information.
302 
|======
303 
 
304 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
311 
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
315 
 
316 
 
317 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicsr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
323 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
324 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
325 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
326 
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
329 
 
330 
 
331 
:sectnums!:
332 
===== _CPU_EXTENSION_RISCV_Zifencei_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
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See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
342 
 
343 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zmmul_
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347 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
350 
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
352 
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
354 
 
355 
 
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// ####################################################################################################################
357 
:sectnums:
358 
==== Extension Options
359 
 
360 
See section <<_instruction_sets_and_extensions>> for more information.
361 
 
362 
 
363 
:sectnums!:
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===== _FAST_MUL_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
369 
| **FAST_MUL_EN** | _boolean_ | false
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3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
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iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
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utilization. This generic is only relevant when a hardware multiplier CPU extension is
373 
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
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<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
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|======
376 
 
377 
 
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:sectnums!:
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===== _FAST_SHIFT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
384 
| **FAST_SHIFT_EN** | _boolean_ | false
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3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
386 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
387 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
388 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
389 
shift-related operations of the <<_zbb_basic_bit_manipulation_operations>> extension.**
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|======
391 
 
392 
 
393 
:sectnums!:
394 
===== _CPU_CNT_WIDTH_
395 
 
396 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_CNT_WIDTH** | _natural_ | 64
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3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
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The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
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Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
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|======
404 
 
405 
 
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:sectnums!:
407 
===== _CPU_IPB_ENTRIES_
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409 
[cols="4,4,2"]
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[frame="all",grid="none"]
411 
|======
412 
| **CPU_IPB_ENTRIES** | _natural_ | 2
413 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
414 
The value has to be a power of two and has to be greater than zero.
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Long linear sequences of code can benefit from an increased IPB size.
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|======
417 
 
418 
 
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// ####################################################################################################################
420 
:sectnums:
421 
==== Physical Memory Protection (PMP)
422 
 
423 
See section <<_pmp_physical_memory_protection>> for more information.
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425 
 
426 
:sectnums!:
427 
===== _PMP_NUM_REGIONS_
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429 
[cols="4,4,2"]
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[frame="all",grid="none"]
431 
|======
432 
| **PMP_NUM_REGIONS** | _natural_ | 0
433 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
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protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
435 
in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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|======
437 
 
438 
 
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:sectnums!:
440 
===== _PMP_MIN_GRANULARITY_
441 
 
442 
[cols="4,4,2"]
443 
[frame="all",grid="none"]
444 
|======
445 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
446 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
447 
|======
448 
 
449 
 
450 
// ####################################################################################################################
451 
:sectnums:
452 
==== Hardware Performance Monitors (HPM)
453 
 
454 
See section <<_hpm_hardware_performance_monitors>> for more information.
455 
 
456 
 
457 
:sectnums!:
458 
===== _HPM_NUM_CNTS_
459 
 
460 
[cols="4,4,2"]
461 
[frame="all",grid="none"]
462 
|======
463 
| **HPM_NUM_CNTS** | _natural_ | 0
464 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
465 
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _SYSINFO_CPU_HPM_ flag
466 
in the _SYSINFO_CPU_ <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
467 60 zero_gravi 
|======
468 
 
469 
 
470 
:sectnums!:
471 
===== _HPM_CNT_WIDTH_
472 
 
473 
[cols="4,4,2"]
474 
[frame="all",grid="none"]
475 
|======
476 
| **HPM_CNT_WIDTH** | _natural_ | 40
477 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
478 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
479 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
480 
|======
481 
 
482 
 
483 
// ####################################################################################################################
484 
:sectnums:
485 
==== Internal Instruction Memory
486 
 
487 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
488 
 
489 
 
490 
:sectnums!:
491 
===== _MEM_INT_IMEM_EN_
492 
 
493 
[cols="4,4,2"]
494 
[frame="all",grid="none"]
495 
|======
496 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
497 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
498 
|======
499 
 
500 
 
501 
:sectnums!:
502 
===== _MEM_INT_IMEM_SIZE_
503 
 
504 
[cols="4,4,2"]
505 
[frame="all",grid="none"]
506 
|======
507 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
508 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
509 60 zero_gravi 
|======
510 
 
511 
 
512 
// ####################################################################################################################
513 
:sectnums:
514 
==== Internal Data Memory
515 
 
516 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
517 
 
518 
 
519 
:sectnums!:
520 
===== _MEM_INT_DMEM_EN_
521 
 
522 
[cols="4,4,2"]
523 
[frame="all",grid="none"]
524 
|======
525 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
526 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
527 
|======
528 
 
529 
 
530 
:sectnums!:
531 
===== _MEM_INT_DMEM_SIZE_
532 
 
533 
[cols="4,4,2"]
534 
[frame="all",grid="none"]
535 
|======
536 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
537 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
538 60 zero_gravi 
|======
539 
 
540 
 
541 
// ####################################################################################################################
542 
:sectnums:
543 
==== Internal Cache Memory
544 
 
545 
See section <<_processor_internal_instruction_cache_icache>> for more information.
546 
 
547 
 
548 
:sectnums!:
549 
===== _ICACHE_EN_
550 
 
551 
[cols="4,4,2"]
552 
[frame="all",grid="none"]
553 
|======
554 
| **ICACHE_EN** | _boolean_ | false
555 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
556 
and instruction memories there is not point of implementing the i-cache.
557 60 zero_gravi 
|======
558 
 
559 
 
560 
:sectnums!:
561 
===== _ICACHE_NUM_BLOCK_
562 
 
563 
[cols="4,4,2"]
564 
[frame="all",grid="none"]
565 
|======
566 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
567 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
568 63 zero_gravi 
effect when <<_icache_dmem_en>> is false.
569 60 zero_gravi 
|======
570 
 
571 
 
572 
:sectnums!:
573 
===== _ICACHE_BLOCK_SIZE_
574 
 
575 
[cols="4,4,2"]
576 
[frame="all",grid="none"]
577 
|======
578 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
579 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
580 63 zero_gravi 
<<_icache_dmem_en>> is _false_.
581 60 zero_gravi 
|======
582 
 
583 
 
584 
:sectnums!:
585 
===== _ICACHE_ASSOCIATIVITY_
586 
 
587 
[cols="4,4,2"]
588 
[frame="all",grid="none"]
589 
|======
590 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
591 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
592 63 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
593 60 zero_gravi 
|======
594 
 
595 
 
596 
// ####################################################################################################################
597 
:sectnums:
598 
==== External Memory Interface
599 
 
600 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
601 
 
602 
 
603 
:sectnums!:
604 
===== _MEM_EXT_EN_
605 
 
606 
[cols="4,4,2"]
607 
[frame="all",grid="none"]
608 
|======
609 
| **MEM_EXT_EN** | _boolean_ | false
610 
3+| Implement external bus interface (WISHBONE) when _true_.
611 
|======
612 
 
613 
 
614 
:sectnums!:
615 
===== _MEM_EXT_TIMEOUT_
616 
 
617 
[cols="4,4,2"]
618 
[frame="all",grid="none"]
619 
|======
620 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
621 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
622 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
623 60 zero_gravi 
|======
624 
 
625 
 
626 62 zero_gravi 
:sectnums!:
627 
===== _MEM_EXT_PIPE_MODE_
628 
 
629 
[cols="4,4,2"]
630 
[frame="all",grid="none"]
631 
|======
632 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
633 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
634 
Use _pipelined_ Wishbone protocol when _true_.
635 62 zero_gravi 
|======
636 
 
637 
 
638 
:sectnums!:
639 
===== _MEM_EXT_BIG_ENDIAN_
640 
 
641 
[cols="4,4,2"]
642 
[frame="all",grid="none"]
643 
|======
644 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
645 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
646 62 zero_gravi 
|======
647 
 
648 
 
649 
:sectnums!:
650 
===== _MEM_EXT_ASYNC_RX_
651 
 
652 
[cols="4,4,2"]
653 
[frame="all",grid="none"]
654 
|======
655 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
656 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
657 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
658 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
659 62 zero_gravi 
|======
660 
 
661 
 
662 60 zero_gravi 
// ####################################################################################################################
663 
:sectnums:
664 61 zero_gravi 
==== Stream Link Interface
665 
 
666 
See section <<_stream_link_interface_slink>> for more information.
667 
 
668 
 
669 
:sectnums!:
670 
===== _SLINK_NUM_TX_
671 
 
672 
[cols="4,4,2"]
673 
[frame="all",grid="none"]
674 
|======
675 
| **SLINK_NUM_TX** | _natural_ | 0
676 
3+| Number of TX (send) links to implement. Valid values are 0..8.
677 
|======
678 
 
679 
 
680 
:sectnums!:
681 
===== _SLINK_NUM_RX_
682 
 
683 
[cols="4,4,2"]
684 
[frame="all",grid="none"]
685 
|======
686 
| **SLINK_NUM_RX** | _natural_ | 0
687 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
688 
|======
689 
 
690 
 
691 
:sectnums!:
692 
===== _SLINK_TX_FIFO_
693 
 
694 
[cols="4,4,2"]
695 
[frame="all",grid="none"]
696 
|======
697 
| **SLINK_TX_FIFO** | _natural_ | 1
698 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
699 
|======
700 
 
701 
 
702 
:sectnums!:
703 
===== _SLINK_RX_FIFO_
704 
 
705 
[cols="4,4,2"]
706 
[frame="all",grid="none"]
707 
|======
708 
| **SLINK_RX_FIFO** | _natural_ | 1
709 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
710 
|======
711 
 
712 
 
713 
// ####################################################################################################################
714 
:sectnums:
715 
==== External Interrupt Controller
716 
 
717 
See section <<_external_interrupt_controller_xirq>> for more information.
718 
 
719 
 
720 
:sectnums!:
721 
===== _XIRQ_NUM_CH_
722 
 
723 
[cols="4,4,2"]
724 
[frame="all",grid="none"]
725 
|======
726 
| **XIRQ_NUM_CH** | _natural_ | 0
727 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
728 
|======
729 
 
730 
 
731 
:sectnums!:
732 
===== _XIRQ_TRIGGER_TYPE_
733 
 
734 
[cols="4,4,2"]
735 
[frame="all",grid="none"]
736 
|======
737 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
738 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
739 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
740 61 zero_gravi 
|======
741 
 
742 
 
743 
:sectnums!:
744 
===== _XIRQ_TRIGGER_POLARITY_
745 
 
746 
[cols="4,4,2"]
747 
[frame="all",grid="none"]
748 
|======
749 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
750 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
751 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
752 61 zero_gravi 
|======
753 
 
754 
 
755 
// ####################################################################################################################
756 
:sectnums:
757 60 zero_gravi 
==== Processor Peripheral/IO Modules
758 
 
759 
See section <<_processor_internal_modules>> for more information.
760 
 
761 
 
762 
:sectnums!:
763 
===== _IO_GPIO_EN_
764 
 
765 
[cols="4,4,2"]
766 
[frame="all",grid="none"]
767 
|======
768 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
769 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
770 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
771 
|======
772 
 
773 
 
774 
:sectnums!:
775 
===== _IO_MTIME_EN_
776 
 
777 
[cols="4,4,2"]
778 
[frame="all",grid="none"]
779 
|======
780 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
781 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
782 
See section <<_machine_system_timer_mtime>> for more information.
783 
|======
784 
 
785 
 
786 
:sectnums!:
787 
===== _IO_UART0_EN_
788 
 
789 
[cols="4,4,2"]
790 
[frame="all",grid="none"]
791 
|======
792 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
793 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
794 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
795 
more information.
796 
|======
797 
 
798 
 
799 
:sectnums!:
800 
===== _IO_UART1_EN_
801 
 
802 
[cols="4,4,2"]
803 
[frame="all",grid="none"]
804 
|======
805 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
806 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
807 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
808 
|======
809 
 
810 
 
811 
:sectnums!:
812 
===== _IO_SPI_EN_
813 
 
814 
[cols="4,4,2"]
815 
[frame="all",grid="none"]
816 
|======
817 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
818 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
819 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
820 
|======
821 
 
822 
 
823 
:sectnums!:
824 
===== _IO_TWI_EN_
825 
 
826 
[cols="4,4,2"]
827 
[frame="all",grid="none"]
828 
|======
829 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
830 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
831 
See section <<_two_wire_serial_interface_controller_twi>> for
832 
more information.
833 
|======
834 
 
835 
 
836 
:sectnums!:
837 
===== _IO_PWM_NUM_CH_
838 
 
839 
[cols="4,4,2"]
840 
[frame="all",grid="none"]
841 
|======
842 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
843 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
844 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
845 
|======
846 
 
847 
 
848 
:sectnums!:
849 
===== _IO_WDT_EN_
850 
 
851 
[cols="4,4,2"]
852 
[frame="all",grid="none"]
853 
|======
854 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
855 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
856 
information.
857 
|======
858 
 
859 
 
860 
:sectnums!:
861 
===== _IO_TRNG_EN_
862 
 
863 
[cols="4,4,2"]
864 
[frame="all",grid="none"]
865 
|======
866 
| **IO_TRNG_EN** | _boolean_ | false
867 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
868 
|======
869 
 
870 
 
871 
:sectnums!:
872 
===== _IO_CFS_EN_
873 
 
874 
[cols="4,4,2"]
875 
[frame="all",grid="none"]
876 
|======
877 
| **IO_CFS_EN** | _boolean_ | false
878 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
879 
|======
880 
 
881 
 
882 
:sectnums!:
883 
===== _IO_CFS_CONFIG_
884 
 
885 
[cols="4,4,2"]
886 
[frame="all",grid="none"]
887 
|======
888 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
889 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
890 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
891 
|======
892 
 
893 
 
894 
:sectnums!:
895 
===== _IO_CFS_IN_SIZE_
896 
 
897 
[cols="4,4,2"]
898 
[frame="all",grid="none"]
899 
|======
900 
| **IO_CFS_IN_SIZE** | _positive_ | 32
901 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
902 
|======
903 
 
904 
 
905 
:sectnums!:
906 
===== _IO_CFS_OUT_SIZE_
907 
 
908 
[cols="4,4,2"]
909 
[frame="all",grid="none"]
910 
|======
911 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
912 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
913 
|======
914 
 
915 
 
916 
:sectnums!:
917 
===== _IO_NEOLED_EN_
918 
 
919 
[cols="4,4,2"]
920 
[frame="all",grid="none"]
921 
|======
922 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
923 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
924 
See section <<_smart_led_interface_neoled>> for more information.
925 
|======
926 
 
927 
 
928 62 zero_gravi 
:sectnums!:
929 
===== _IO_NEOLED_TX_FIFO_
930 
 
931 
[cols="4,4,2"]
932 
[frame="all",grid="none"]
933 
|======
934 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
935 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
936 
See section <<_smart_led_interface_neoled>> for more information.
937 
|======
938 
 
939 
 
940 
 
941 60 zero_gravi 
<<<
942 
// ####################################################################################################################
943 
:sectnums:
944 
=== Processor Interrupts
945 
 
946 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
947 60 zero_gravi 
 
948 
 
949 61 zero_gravi 
:sectnums:
950 
==== RISC-V Standard Interrupts
951 
 
952 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
953 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
954 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
955 
<<_traps_exceptions_and_interrupts>> for more information.
956 60 zero_gravi 
 
957 61 zero_gravi 
[cols="<3,^2,<11"]
958 
[options="header",grid="rows"]
959 
|=======================
960 
| Top signal | Width | Description
961 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
962 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
963 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
964 
|=======================
965 60 zero_gravi 
 
966 62 zero_gravi 
[IMPORTANT]
967 
These IRQs trigger on a **rising-edge**.
968 61 zero_gravi 
 
969 
 
970 
:sectnums:
971 
==== Non-Maskable Interrupt
972 
 
973 
[cols="<3,^2,<11"]
974 
[options="header",grid="rows"]
975 
|=======================
976 
| Top signal | Width | Description
977 
| `nm_irq_i` | 1 | Non-maskable interrupt.
978 
|=======================
979 
 
980 
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
981 
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
982 
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
983 
 
984 62 zero_gravi 
[IMPORTANT]
985 
This IRQ triggers on a **rising-edge**.
986 61 zero_gravi 
 
987 
 
988 
:sectnums:
989 
==== Platform External Interrupts
990 
 
991 
[cols="<3,^2,<11"]
992 
[options="header",grid="rows"]
993 
|=======================
994 
| Top signal | Width | Description
995 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
996 
|=======================
997 
 
998 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
999 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1000 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1001 
 
1002 
[NOTE]
1003 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1004 61 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information.
1005 
 
1006 
 
1007 
:sectnums:
1008 
==== NEORV32-Specific Fast Interrupt Requests
1009 
 
1010 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1011 61 zero_gravi 
(`FIRQ0` – `FIRQ15`). These are used for _processor-internal_ modules only (for example for the communication
1012 
interfaces to signal "available incoming data" or "ready to send new data").
1013 60 zero_gravi 
 
1014 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1015 
the according FIRQ priority; 0 = highest, 15 = lowest):
1016 60 zero_gravi 
 
1017 
.NEORV32 fast interrupt channel mapping
1018 
[cols="^1,<2,<7"]
1019 
[options="header",grid="rows"]
1020 
|=======================
1021 
| Channel | Source | Description
1022 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1023 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1024 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1025 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1026 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1027 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1028 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1029 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1030 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1031 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
1032 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data received
1033 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data send
1034 62 zero_gravi 
| 12:15   | - | _reserved_, will never fire
1035 60 zero_gravi 
|=======================
1036 
 
1037 
 
1038 
 
1039 
<<<
1040 
// ####################################################################################################################
1041 
:sectnums:
1042 
=== Address Space
1043 
 
1044 61 zero_gravi 
The NEORV32 Processor provides 32-bit physical addresses accessing up to 4GB of address space.
1045 
By default, this address space is divided into four main regions:
1046 60 zero_gravi 
 
1047 61 zero_gravi 
1. **Instruction address space** – for instructions (=code) and constants. A configurable section of this address space is used by
1048 
internal and/or external _instruction memory_ (IMEM).
1049 
2. **Data address space** – for application runtime data (heap, stack, etc.). A configurable section of this address space is used by
1050 
internal and/or external _data memory_ (DMEM).
1051 
3. **Bootloader address space**. A _fixed_ section of this address space is used by
1052 
internal _bootloader memory_ (BOOTLDROM).
1053 
4. **IO/peripheral address space** – for the processor-internal IO/peripheral devices (e.g., UART).
1054 60 zero_gravi 
 
1055 
[TIP]
1056 
These four memory regions are handled by the linker when compiling a NEORV32 executable.
1057 
See section <<_executable_image_format>> for more information.
1058 
 
1059 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1060 
image::address_space.png[900]
1061 60 zero_gravi 
 
1062 
 
1063 
:sectnums:
1064 
==== CPU Data and Instruction Access
1065 
 
1066 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1067 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1068 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1069 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1070 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1071 
setup a modified von-Neumann architecture.
1072 
 
1073 
.Processor-internal bus architecture
1074 
image::neorv32_bus.png[1300]
1075 
 
1076 
[NOTE]
1077 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1078 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1079 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1080 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1081 
accesses.
1082 
 
1083 
[IMPORTANT]
1084 
Please note that all processor-internal components including the peripheral/IO devices can also be
1085 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1086 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1087 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1088 
PMP system (see <<_machine_physical_memory_protection>>).
1089 
 
1090 61 zero_gravi 
 
1091 60 zero_gravi 
:sectnums:
1092 61 zero_gravi 
==== Address Space Layout
1093 
 
1094 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1095 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1096 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1097 
`rtl/core/neorv32_package.vhd`:
1098 
 
1099 
[source,vhdl]
1100 
----
1101 
-- Architecture Configuration ----------------------------------------------------
1102 
-- ----------------------------------------------------------------------------------
1103 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1104 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1105 
----
1106 
 
1107 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1108 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1109 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1110 
are _aligned_ to a 4-byte boundary.
1111 
 
1112 
[NOTE]
1113 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1114 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1115 
applications – even if the bootloader or all IO devices are not implemented - without modifying the core's
1116 
hardware sources.
1117 
 
1118 
 
1119 
:sectnums:
1120 60 zero_gravi 
==== Physical Memory Attributes
1121 
 
1122 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1123 
Accessing a memory region in a way that violates any of these attributes will raise an according
1124 
access exception..
1125 60 zero_gravi 
 
1126 
* `r` – read access (from CPU data access interface, e.g. via "load")
1127 
* `w` – write access (from CPU data access interface, e.g. via "store")
1128 
* `x` – execute access (from CPU instruction fetch interface)
1129 
* `a` – atomic access (from CPU data access interface)
1130 
* `8` – byte (8-bit)-accessible (when writing)
1131 
* `16` – half-word (16-bit)-accessible (when writing)
1132 
* `32` – word (32-bit)-accessible (when writing)
1133 
 
1134 61 zero_gravi 
[NOTE]
1135 
Read accesses (i.e. loads) can always access data in word, half-word and byte quantities (requiring an accordingly aligned address).
1136 60 zero_gravi 
 
1137 
[cols="^1,^2,^2,^3,^2"]
1138 
[options="header",grid="rows"]
1139 
|=======================
1140 
| # | Region | Base address | Size | Attributes
1141 
| 4 | IO/peripheral devices | 0xfffffe00 | 512 bytes | `r/w/a/32`
1142 
| 3 | bootloader ROM        | 0xffff0000 | up to 32kB| `r/x/a`
1143 
| 2 | DMEM                  | 0x80000000 | up to 2GB (-64kB) | `r/w/x/a/8/16/32`
1144 
| 1 | IMEM                  | 0x00000000 | up to 2GB | `r/w/x/a/8/16/32`
1145 
|=======================
1146 
 
1147 61 zero_gravi 
[TIP]
1148 
The following table shows the provided physical memory attributes of each region. Additional attributes (for example
1149 
controlling certain right for specific address space regions) can be provided using the RISC-V <<_machine_physical_memory_protection>> extension.
1150 60 zero_gravi 
 
1151 
 
1152 
:sectnums:
1153 61 zero_gravi 
==== Memory Configuration
1154 60 zero_gravi 
 
1155 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1156 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1157 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1158 
the internal ones. The figure below show some exemplary memory configurations.
1159 60 zero_gravi 
 
1160 61 zero_gravi 
.Exemplary memory configurations
1161 
image::neorv32_memory_configurations.png[800]
1162 60 zero_gravi 
 
1163 61 zero_gravi 
:sectnums!:
1164 
===== Internal Memories
1165 
 
1166 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1167 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1168 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1169 
 
1170 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1171 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1172 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1173 
implemented.
1174 
 
1175 61 zero_gravi 
[TIP]
1176 
The default processor setup uses only _internal_ memories.
1177 60 zero_gravi 
 
1178 61 zero_gravi 
[NOTE]
1179 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1180 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1181 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1182 
any access to the "dead address space" in between will raise an exception that can be caught
1183 
by the runtime environment.
1184 60 zero_gravi 
 
1185 61 zero_gravi 
:sectnums!:
1186 
===== External Memories
1187 
 
1188 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1189 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1190 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1191 
 
1192 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1193 
via the processor's bus interface to external components:
1194 
 
1195 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1196 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1197 
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1198 
 
1199 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1200 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1201 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1202 
memory system.
1203 60 zero_gravi 
 
1204 61 zero_gravi 
[NOTE]
1205 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1206 
the internal peripheral address space will trigger a bus access fault exception.
1207 60 zero_gravi 
 
1208 
 
1209 61 zero_gravi 
:sectnums:
1210 
==== Boot Configuration
1211 
 
1212 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1213 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1214 
 
1215 
.NEORV32 boot configurations
1216 
image::neorv32_boot_configurations.png[800]
1217 
 
1218 
[NOTE]
1219 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1220 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1221 
 
1222 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1223 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1224 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1225 
 
1226 
[NOTE]
1227 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1228 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1229 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1230 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1231 
store it to external _data_ memory and transfers CPU control to that.
1232 
 
1233 
:sectnums!:
1234 
===== Indirect Boot
1235 
 
1236 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
1237 
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1238 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1239 
 
1240 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
1241 
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
1242 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1243 
RAM so the bootloader can write the actual executable to it.
1244 
 
1245 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1246 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1247 
write the executable to the processor-external memory.
1248 
 
1249 
:sectnums!:
1250 
===== Direct Boot
1251 
 
1252 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
1253 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1254 
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
1255 
in order to provide an executable _in_ memory.
1256 
 
1257 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1258 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
1259 
 
1260 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1261 
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
1262 
 
1263 
 
1264 
 
1265 60 zero_gravi 
<<<
1266 
// ####################################################################################################################
1267 
:sectnums:
1268 
=== Processor-Internal Modules
1269 
 
1270 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1271 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1272 
system implements an internal reset generator and a global clock generator/divider.
1273 
 
1274 
**Internal Reset Generator**
1275 
 
1276 
Most processor-internal modules – except for the CPU and the watchdog timer – do not have a dedicated
1277 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1278 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1279 
modules to ensure a clean system reset state.
1280 
 
1281 
The hardware reset signal of the processor can either be
1282 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1283 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1284 
clock cycles.
1285 
 
1286 
**Internal Clock Divider**
1287 
 
1288 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1289 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1290 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1291 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1292 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1293 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1294 
power.
1295 
 
1296 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1297 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1298 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1299 
from the top entity's `clk_i` signal.
1300 
 
1301 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1302 
[grid="rows"]
1303 
|=======================
1304 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1305 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1306 
|=======================
1307 
 
1308 
**Peripheral / IO Devices**
1309 
 
1310 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1311 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1312 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1313 
library abstract the specific memory layout for the user.
1314 
 
1315 
[IMPORTANT]
1316 
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
1317 
load/store access fault exception is triggered.
1318 
 
1319 
[IMPORTANT]
1320 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1321 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1322 
Processor-internal memories as well as modules connected to the external memory interface can still
1323 
be written with a byte-wide granularity.
1324 
 
1325 
[TIP]
1326 
You should use the provided core software library to interact with the peripheral devices. This
1327 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1328 
register and register bit accesses.
1329 
 
1330 
[TIP]
1331 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1332 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1333 
application start-up code `crt0.S`.
1334 
 
1335 
**Nomenclature for the Peripheral / IO Devices Listing**
1336 
 
1337 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1338 
according device including the implemented control and status bits. You can directly interact with these
1339 
registers/bits via the provided _C-code defines_. These defines are set in the main processor core library
1340 
include file `sw/lib/include/neorv32.h`. The registers and/or register bits, which can be accessed
1341 
directly using plain C-code, are marked with a "[C]".
1342 
 
1343 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1344 
available:
1345 
 
1346 
* `r/w` registers / bits can be read and written
1347 
* `r/-` registers / bits are read-only; any write access to them has no effect
1348 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1349 
 
1350 
[TIP]
1351 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1352 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1353 
write zero to them to keep compatible with future extension.
1354 
 
1355 
[TIP]
1356 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1357 
written. When reading data from a write-only register the result is undefined.
1358 
 
1359 
 
1360 
include::soc_imem.adoc[]
1361 
 
1362 
include::soc_dmem.adoc[]
1363 
 
1364 
include::soc_bootrom.adoc[]
1365 
 
1366 
include::soc_icache.adoc[]
1367 
 
1368 
include::soc_wishbone.adoc[]
1369 
 
1370 61 zero_gravi 
include::soc_slink.adoc[]
1371 
 
1372 60 zero_gravi 
include::soc_gpio.adoc[]
1373 
 
1374 
include::soc_wdt.adoc[]
1375 
 
1376 
include::soc_mtime.adoc[]
1377 
 
1378 
include::soc_uart.adoc[]
1379 
 
1380 
include::soc_spi.adoc[]
1381 
 
1382 
include::soc_twi.adoc[]
1383 
 
1384 
include::soc_pwm.adoc[]
1385 
 
1386 
include::soc_trng.adoc[]
1387 
 
1388 
include::soc_cfs.adoc[]
1389 
 
1390 
include::soc_neoled.adoc[]
1391 
 
1392 61 zero_gravi 
include::soc_xirq.adoc[]
1393 
 
1394 60 zero_gravi 
include::soc_sysinfo.adoc[]
1395 
 
1396 
 

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