OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc.adoc] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 zero_gravi 
 
2 
// ####################################################################################################################
3 
:sectnums:
4 
== NEORV32 Processor (SoC)
5 
 
6 
The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
7 
interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
10 
 
11 
**Key Features**
12 
 
13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
14 
* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
15 
* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
16 65 zero_gravi 
* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
17 60 zero_gravi 
* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
18 
* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
19 61 zero_gravi 
* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
20 60 zero_gravi 
* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
21 61 zero_gravi 
* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
22 60 zero_gravi 
* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
23 
* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
24 
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
25 
* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
26 
* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
27 61 zero_gravi 
* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
28 60 zero_gravi 
* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
29 66 zero_gravi 
* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
30 60 zero_gravi 
* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
31 
 
32 
 
33 
<<<
34 
// ####################################################################################################################
35 
:sectnums:
36 
=== Processor Top Entity - Signals
37 
 
38 62 zero_gravi 
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
39 
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
40 60 zero_gravi 
 
41 62 zero_gravi 
[IMPORTAN]
42 
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
43 
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
44 
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
45 
since all control signals have defined level.
46 60 zero_gravi 
 
47 
[cols="<3,^2,^2,<11"]
48 
[options="header",grid="rows"]
49 
|=======================
50 
| Signal | Width | Dir. | Function
51 
4+^| **Global Control**
52 
| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
53 
| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
54 
4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
55 
| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
56 61 zero_gravi 
| `jtag_tck_i`  | 1 | in  | serial clock
57 
| `jtag_tdi_i`  | 1 | in  | serial data input
58 
| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
59 
| `jtag_tms_i`  | 1 | in  | mode select
60 60 zero_gravi 
4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
61 
| `wb_tag_o` | 3  | out | tag (access type identifier)
62 
| `wb_adr_o` | 32 | out | destination address
63 
| `wb_dat_i` | 32 | in | write data
64 
| `wb_dat_o` | 32 | out | read data
65 
| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
66 
| `wb_sel_o` | 4  | out | byte enable
67 
| `wb_stb_o` | 1  | out | strobe
68 
| `wb_cyc_o` | 1  | out | valid cycle
69 
| `wb_lock_o`| 1  | out | exclusive access request
70 
| `wb_ack_i` | 1  | in | transfer acknowledge
71 
| `wb_err_i` | 1  | in | transfer error
72 
4+^| **Advanced Memory Control Signals**
73 
| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
74 
| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
75 61 zero_gravi 
4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
76 
| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
77 
| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
78 
| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
79 
| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
80 
| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
81 
| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
82 60 zero_gravi 
4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
83 61 zero_gravi 
| `gpio_o` | 64 | out | general purpose parallel output
84 
| `gpio_i` | 64 | in | general purpose parallel input
85 60 zero_gravi 
4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
86 
| `uart0_txd_o` | 1 | out | UART0 serial transmitter
87 
| `uart0_rxd_i` | 1 | in | UART0 serial receiver
88 
| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
89 
| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
90 
4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
91 
| `uart1_txd_o` | 1 | out | UART1 serial transmitter
92 
| `uart1_rxd_i` | 1 | in | UART1 serial receiver
93 
| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
94 
| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
95 
4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
96 
| `spi_sck_o` | 1 | out | SPI controller clock line
97 
| `spi_sdo_o` | 1 | out | SPI serial data output
98 
| `spi_sdi_i` | 1 | in | SPI serial data input
99 
| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
100 
4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
101 
| `twi_sda_io` | 1 | inout | TWI serial data line
102 
| `twi_scl_io` | 1 | inout | TWI serial clock line
103 64 zero_gravi 
4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
104 
| `pwm_o` | 0..60 | out | pulse-width modulated channels
105 60 zero_gravi 
4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
106 
| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
107 
| `cfs_out_o` | 32 | out | custom CFS output signal conduit
108 
4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
109 
| `neoled_o` | 1 | out | asynchronous serial data output
110 
4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
111 
| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
112 
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
113 64 zero_gravi 
4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
114 61 zero_gravi 
| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
115 64 zero_gravi 
4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
116 
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
117 
| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
118 
| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
119 60 zero_gravi 
|=======================
120 
 
121 
 
122 
<<<
123 
// ####################################################################################################################
124 
:sectnums:
125 
=== Processor Top Entity - Generics
126 
 
127 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
128 
The generic name is shown in orange, followed by the type in printed in black and concluded by the default
129 
value printed in light gray.
130 
 
131 
[TIP]
132 
The NEORV32 generics allow to configure the system according to your needs. The generics are
133 
used to control implementation of certain CPU extensions and peripheral modules and even allow to
134 63 zero_gravi 
optimize the system for certain design goals like minimal area or maximum performance. +
135 
**More information can be found in the user guides' section
136 
https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
137 60 zero_gravi 
 
138 
[TIP]
139 63 zero_gravi 
Privileged software can determine the actual CPU and processor configuration via the `misa` and the
140 64 zero_gravi 
<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
141 60 zero_gravi 
 
142 63 zero_gravi 
[NOTE]
143 
If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
144 
**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
145 
and do not impact the timing.
146 60 zero_gravi 
 
147 63 zero_gravi 
[NOTE]
148 61 zero_gravi 
Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
149 
during synthesis/simulation if an invalid combination has been detected.
150 60 zero_gravi 
 
151 61 zero_gravi 
**Generic Description**
152 60 zero_gravi 
 
153 61 zero_gravi 
The description of each generic provides the following summary:
154 
 
155 60 zero_gravi 
.Generic description
156 
[cols="4,4,2"]
157 
[frame="all",grid="none"]
158 
|======
159 61 zero_gravi 
| _Generic name_ | _type_ | _default value_
160 60 zero_gravi 
3+| _Description_
161 
|======
162 
 
163 
<<<
164 
// ####################################################################################################################
165 
:sectnums:
166 
==== General
167 
 
168 
See section <<_system_configuration_information_memory_sysinfo>> for more information.
169 
 
170 
:sectnums!:
171 
===== _CLOCK_FREQUENCY_
172 
 
173 
[cols="4,4,2"]
174 
[frame="all",grid="none"]
175 
|======
176 62 zero_gravi 
| **CLOCK_FREQUENCY** | _natural_ | _none_
177 63 zero_gravi 
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
178 
from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
179 60 zero_gravi 
|======
180 
 
181 
 
182 
:sectnums!:
183 61 zero_gravi 
===== _INT_BOOTLOADER_EN_
184 60 zero_gravi 
 
185 
[cols="4,4,2"]
186 
[frame="all",grid="none"]
187 
|======
188 62 zero_gravi 
| **INT_BOOTLOADER_EN** | _boolean_ | false
189 61 zero_gravi 
3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
190 
This will also change the processor's boot address from the beginning of the instruction memory address space (default =
191 
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
192 60 zero_gravi 
|======
193 
 
194 
 
195 
:sectnums!:
196 
===== _HW_THREAD_ID_
197 
 
198 
[cols="4,4,2"]
199 
[frame="all",grid="none"]
200 
|======
201 
| **HW_THREAD_ID** | _natural_ | 0
202 63 zero_gravi 
3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
203 
Note that hart IDs must be unique within a system.
204 60 zero_gravi 
|======
205 
 
206 
 
207 
:sectnums!:
208 
===== _ON_CHIP_DEBUGGER_EN_
209 
 
210 
[cols="4,4,2"]
211 
[frame="all",grid="none"]
212 
|======
213 
| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
214 63 zero_gravi 
3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
215 
See chapter <<_on_chip_debugger_ocd>> for more information.
216 60 zero_gravi 
|======
217 
 
218 
 
219 
// ####################################################################################################################
220 
:sectnums:
221 
==== RISC-V CPU Extensions
222 
 
223 63 zero_gravi 
[TIP]
224 
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
225 
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
226 
can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
227 60 zero_gravi 
 
228 
 
229 
:sectnums!:
230 
===== _CPU_EXTENSION_RISCV_A_
231 
 
232 
[cols="4,4,2"]
233 
[frame="all",grid="none"]
234 
|======
235 
| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
236 
3+| Implement atomic memory access operations when _true_.
237 61 zero_gravi 
See section <<_a_atomic_memory_access>>.
238 60 zero_gravi 
|======
239 
 
240 
 
241 
:sectnums!:
242 66 zero_gravi 
===== _CPU_EXTENSION_RISCV_B_
243 
 
244 
[cols="4,4,2"]
245 
[frame="all",grid="none"]
246 
|======
247 
| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
248 
3+| Implement the `B` bit-manipulation sub-extension when _true_.
249 
See section <<_b_bit_manipulation_operations>> for more information.
250 
|======
251 
 
252 
 
253 
:sectnums!:
254 60 zero_gravi 
===== _CPU_EXTENSION_RISCV_C_
255 
 
256 
[cols="4,4,2"]
257 
[frame="all",grid="none"]
258 
|======
259 
| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
260 63 zero_gravi 
3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
261 
size by approx. 30%. See section <<_c_compressed_instructions>>.
262 60 zero_gravi 
|======
263 
 
264 
 
265 
:sectnums!:
266 
===== _CPU_EXTENSION_RISCV_E_
267 
 
268 
[cols="4,4,2"]
269 
[frame="all",grid="none"]
270 
|======
271 
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
272 63 zero_gravi 
3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
273 
requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
274 
requires a different application binary interface (ABI).
275 60 zero_gravi 
|======
276 
 
277 
 
278 
:sectnums!:
279 
===== _CPU_EXTENSION_RISCV_M_
280 
 
281 
[cols="4,4,2"]
282 
[frame="all",grid="none"]
283 
|======
284 
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
285 63 zero_gravi 
3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
286 
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
287 
If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
288 
to DSP slices via the <<_fast_mul_en>> generic.
289 
See section <<_m_integer_multiplication_and_division>> for more information.
290 60 zero_gravi 
|======
291 
 
292 
 
293 
:sectnums!:
294 
===== _CPU_EXTENSION_RISCV_U_
295 
 
296 
[cols="4,4,2"]
297 
[frame="all",grid="none"]
298 
|======
299 
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
300 
3+| Implement less-privileged user mode when _true_.
301 63 zero_gravi 
See section <<_u_less_privileged_user_mode>> for more information.
302 60 zero_gravi 
|======
303 
 
304 
 
305 
:sectnums!:
306 
===== _CPU_EXTENSION_RISCV_Zfinx_
307 
 
308 
[cols="4,4,2"]
309 
[frame="all",grid="none"]
310 
|======
311 
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
312 61 zero_gravi 
3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
313 63 zero_gravi 
See section <<_zfinx_single_precision_floating_point_operations>> for more information.
314 60 zero_gravi 
|======
315 
 
316 
 
317 
:sectnums!:
318 
===== _CPU_EXTENSION_RISCV_Zicsr_
319 
 
320 
[cols="4,4,2"]
321 
[frame="all",grid="none"]
322 
|======
323 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
324 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
325 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
326 
no machine information will be available.
327 63 zero_gravi 
See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
328 60 zero_gravi 
|======
329 
 
330 
 
331 
:sectnums!:
332 66 zero_gravi 
===== _CPU_EXTENSION_RISCV_Zicntr_
333 
 
334 
[cols="4,4,2"]
335 
[frame="all",grid="none"]
336 
|======
337 
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
338 
3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
339 
Enabling this extension will set the  _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
340 
See section <<_zicntr_cpu_base_counters>> for more information.
341 
|======
342 
 
343 
 
344 
:sectnums!:
345 
===== _CPU_EXTENSION_RISCV_Zihpm_
346 
 
347 
[cols="4,4,2"]
348 
[frame="all",grid="none"]
349 
|======
350 
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
351 
3+| Implement hardware performance monitor CSRs when true.
352 
Enabling this extension will set the  _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
353 
See section <<_zihpm_hardware_performance_monitors>> for more information.
354 
|======
355 
 
356 
 
357 
:sectnums!:
358 60 zero_gravi 
===== _CPU_EXTENSION_RISCV_Zifencei_
359 
 
360 
[cols="4,4,2"]
361 
[frame="all",grid="none"]
362 
|======
363 
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
364 61 zero_gravi 
3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
365 63 zero_gravi 
for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
366 
See section <<_zifencei_instruction_stream_synchronization>> for more information.
367 60 zero_gravi 
|======
368 
 
369 
 
370 61 zero_gravi 
:sectnums!:
371 
===== _CPU_EXTENSION_RISCV_Zmmul_
372 
 
373 
[cols="4,4,2"]
374 
[frame="all",grid="none"]
375 
|======
376 
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
377 63 zero_gravi 
3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
378 
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
379 61 zero_gravi 
|======
380 
 
381 
 
382 60 zero_gravi 
// ####################################################################################################################
383 
:sectnums:
384 
==== Extension Options
385 
 
386 
See section <<_instruction_sets_and_extensions>> for more information.
387 
 
388 
 
389 
:sectnums!:
390 
===== _FAST_MUL_EN_
391 
 
392 
[cols="4,4,2"]
393 
[frame="all",grid="none"]
394 
|======
395 
| **FAST_MUL_EN** | _boolean_ | false
396 63 zero_gravi 
3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
397 
iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
398 
utilization. This generic is only relevant when a hardware multiplier CPU extension is
399 
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
400 
<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
401 60 zero_gravi 
|======
402 
 
403 
 
404 
:sectnums!:
405 
===== _FAST_SHIFT_EN_
406 
 
407 
[cols="4,4,2"]
408 
[frame="all",grid="none"]
409 
|======
410 
| **FAST_SHIFT_EN** | _boolean_ | false
411 63 zero_gravi 
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
412 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
413 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
414 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
415 66 zero_gravi 
shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
416 60 zero_gravi 
|======
417 
 
418 
 
419 
:sectnums!:
420 
===== _CPU_CNT_WIDTH_
421 
 
422 
[cols="4,4,2"]
423 
[frame="all",grid="none"]
424 
|======
425 62 zero_gravi 
| **CPU_CNT_WIDTH** | _natural_ | 64
426 64 zero_gravi 
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
427 63 zero_gravi 
The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
428 66 zero_gravi 
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
429 63 zero_gravi 
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
430 60 zero_gravi 
|======
431 
 
432 
 
433 62 zero_gravi 
:sectnums!:
434 
===== _CPU_IPB_ENTRIES_
435 
 
436 
[cols="4,4,2"]
437 
[frame="all",grid="none"]
438 
|======
439 
| **CPU_IPB_ENTRIES** | _natural_ | 2
440 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
441 
The value has to be a power of two and has to be greater than zero.
442 63 zero_gravi 
Long linear sequences of code can benefit from an increased IPB size.
443 62 zero_gravi 
|======
444 
 
445 
 
446 60 zero_gravi 
// ####################################################################################################################
447 
:sectnums:
448 
==== Physical Memory Protection (PMP)
449 
 
450 
See section <<_pmp_physical_memory_protection>> for more information.
451 
 
452 
 
453 
:sectnums!:
454 
===== _PMP_NUM_REGIONS_
455 
 
456 
[cols="4,4,2"]
457 
[frame="all",grid="none"]
458 
|======
459 
| **PMP_NUM_REGIONS** | _natural_ | 0
460 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
461 63 zero_gravi 
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
462 64 zero_gravi 
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
463 60 zero_gravi 
|======
464 
 
465 
 
466 
:sectnums!:
467 
===== _PMP_MIN_GRANULARITY_
468 
 
469 
[cols="4,4,2"]
470 
[frame="all",grid="none"]
471 
|======
472 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
473 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
474 
|======
475 
 
476 
 
477 
// ####################################################################################################################
478 
:sectnums:
479 
==== Hardware Performance Monitors (HPM)
480 
 
481 66 zero_gravi 
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
482 
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
483 60 zero_gravi 
 
484 
 
485 
:sectnums!:
486 
===== _HPM_NUM_CNTS_
487 
 
488 
[cols="4,4,2"]
489 
[frame="all",grid="none"]
490 
|======
491 
| **HPM_NUM_CNTS** | _natural_ | 0
492 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
493 66 zero_gravi 
hardware performance monitor logic will be implemented at all.
494 60 zero_gravi 
|======
495 
 
496 
 
497 
:sectnums!:
498 
===== _HPM_CNT_WIDTH_
499 
 
500 
[cols="4,4,2"]
501 
[frame="all",grid="none"]
502 
|======
503 
| **HPM_CNT_WIDTH** | _natural_ | 40
504 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
505 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
506 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
507 
|======
508 
 
509 
 
510 
// ####################################################################################################################
511 
:sectnums:
512 
==== Internal Instruction Memory
513 
 
514 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
515 
 
516 
 
517 
:sectnums!:
518 
===== _MEM_INT_IMEM_EN_
519 
 
520 
[cols="4,4,2"]
521 
[frame="all",grid="none"]
522 
|======
523 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
524 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
525 
|======
526 
 
527 
 
528 
:sectnums!:
529 
===== _MEM_INT_IMEM_SIZE_
530 
 
531 
[cols="4,4,2"]
532 
[frame="all",grid="none"]
533 
|======
534 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
535 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
536 60 zero_gravi 
|======
537 
 
538 
 
539 
// ####################################################################################################################
540 
:sectnums:
541 
==== Internal Data Memory
542 
 
543 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
544 
 
545 
 
546 
:sectnums!:
547 
===== _MEM_INT_DMEM_EN_
548 
 
549 
[cols="4,4,2"]
550 
[frame="all",grid="none"]
551 
|======
552 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
553 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
554 
|======
555 
 
556 
 
557 
:sectnums!:
558 
===== _MEM_INT_DMEM_SIZE_
559 
 
560 
[cols="4,4,2"]
561 
[frame="all",grid="none"]
562 
|======
563 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
564 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
565 60 zero_gravi 
|======
566 
 
567 
 
568 
// ####################################################################################################################
569 
:sectnums:
570 
==== Internal Cache Memory
571 
 
572 
See section <<_processor_internal_instruction_cache_icache>> for more information.
573 
 
574 
 
575 
:sectnums!:
576 
===== _ICACHE_EN_
577 
 
578 
[cols="4,4,2"]
579 
[frame="all",grid="none"]
580 
|======
581 
| **ICACHE_EN** | _boolean_ | false
582 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
583 
and instruction memories there is not point of implementing the i-cache.
584 60 zero_gravi 
|======
585 
 
586 
 
587 
:sectnums!:
588 
===== _ICACHE_NUM_BLOCK_
589 
 
590 
[cols="4,4,2"]
591 
[frame="all",grid="none"]
592 
|======
593 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
594 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
595 63 zero_gravi 
effect when <<_icache_dmem_en>> is false.
596 60 zero_gravi 
|======
597 
 
598 
 
599 
:sectnums!:
600 
===== _ICACHE_BLOCK_SIZE_
601 
 
602 
[cols="4,4,2"]
603 
[frame="all",grid="none"]
604 
|======
605 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
606 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
607 63 zero_gravi 
<<_icache_dmem_en>> is _false_.
608 60 zero_gravi 
|======
609 
 
610 
 
611 
:sectnums!:
612 
===== _ICACHE_ASSOCIATIVITY_
613 
 
614 
[cols="4,4,2"]
615 
[frame="all",grid="none"]
616 
|======
617 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
618 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
619 63 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
620 60 zero_gravi 
|======
621 
 
622 
 
623 
// ####################################################################################################################
624 
:sectnums:
625 
==== External Memory Interface
626 
 
627 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
628 
 
629 
 
630 
:sectnums!:
631 
===== _MEM_EXT_EN_
632 
 
633 
[cols="4,4,2"]
634 
[frame="all",grid="none"]
635 
|======
636 
| **MEM_EXT_EN** | _boolean_ | false
637 
3+| Implement external bus interface (WISHBONE) when _true_.
638 
|======
639 
 
640 
 
641 
:sectnums!:
642 
===== _MEM_EXT_TIMEOUT_
643 
 
644 
[cols="4,4,2"]
645 
[frame="all",grid="none"]
646 
|======
647 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
648 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
649 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
650 60 zero_gravi 
|======
651 
 
652 
 
653 62 zero_gravi 
:sectnums!:
654 
===== _MEM_EXT_PIPE_MODE_
655 
 
656 
[cols="4,4,2"]
657 
[frame="all",grid="none"]
658 
|======
659 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
660 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
661 
Use _pipelined_ Wishbone protocol when _true_.
662 62 zero_gravi 
|======
663 
 
664 
 
665 
:sectnums!:
666 
===== _MEM_EXT_BIG_ENDIAN_
667 
 
668 
[cols="4,4,2"]
669 
[frame="all",grid="none"]
670 
|======
671 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
672 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
673 62 zero_gravi 
|======
674 
 
675 
 
676 
:sectnums!:
677 
===== _MEM_EXT_ASYNC_RX_
678 
 
679 
[cols="4,4,2"]
680 
[frame="all",grid="none"]
681 
|======
682 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
683 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
684 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
685 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
686 62 zero_gravi 
|======
687 
 
688 
 
689 60 zero_gravi 
// ####################################################################################################################
690 
:sectnums:
691 61 zero_gravi 
==== Stream Link Interface
692 
 
693 
See section <<_stream_link_interface_slink>> for more information.
694 
 
695 
 
696 
:sectnums!:
697 
===== _SLINK_NUM_TX_
698 
 
699 
[cols="4,4,2"]
700 
[frame="all",grid="none"]
701 
|======
702 
| **SLINK_NUM_TX** | _natural_ | 0
703 
3+| Number of TX (send) links to implement. Valid values are 0..8.
704 
|======
705 
 
706 
 
707 
:sectnums!:
708 
===== _SLINK_NUM_RX_
709 
 
710 
[cols="4,4,2"]
711 
[frame="all",grid="none"]
712 
|======
713 
| **SLINK_NUM_RX** | _natural_ | 0
714 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
715 
|======
716 
 
717 
 
718 
:sectnums!:
719 
===== _SLINK_TX_FIFO_
720 
 
721 
[cols="4,4,2"]
722 
[frame="all",grid="none"]
723 
|======
724 
| **SLINK_TX_FIFO** | _natural_ | 1
725 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
726 
|======
727 
 
728 
 
729 
:sectnums!:
730 
===== _SLINK_RX_FIFO_
731 
 
732 
[cols="4,4,2"]
733 
[frame="all",grid="none"]
734 
|======
735 
| **SLINK_RX_FIFO** | _natural_ | 1
736 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
737 
|======
738 
 
739 
 
740 
// ####################################################################################################################
741 
:sectnums:
742 
==== External Interrupt Controller
743 
 
744 
See section <<_external_interrupt_controller_xirq>> for more information.
745 
 
746 
 
747 
:sectnums!:
748 
===== _XIRQ_NUM_CH_
749 
 
750 
[cols="4,4,2"]
751 
[frame="all",grid="none"]
752 
|======
753 
| **XIRQ_NUM_CH** | _natural_ | 0
754 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
755 
|======
756 
 
757 
 
758 
:sectnums!:
759 
===== _XIRQ_TRIGGER_TYPE_
760 
 
761 
[cols="4,4,2"]
762 
[frame="all",grid="none"]
763 
|======
764 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
765 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
766 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
767 61 zero_gravi 
|======
768 
 
769 
 
770 
:sectnums!:
771 
===== _XIRQ_TRIGGER_POLARITY_
772 
 
773 
[cols="4,4,2"]
774 
[frame="all",grid="none"]
775 
|======
776 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
777 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
778 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
779 61 zero_gravi 
|======
780 
 
781 
 
782 
// ####################################################################################################################
783 
:sectnums:
784 60 zero_gravi 
==== Processor Peripheral/IO Modules
785 
 
786 
See section <<_processor_internal_modules>> for more information.
787 
 
788 
 
789 
:sectnums!:
790 
===== _IO_GPIO_EN_
791 
 
792 
[cols="4,4,2"]
793 
[frame="all",grid="none"]
794 
|======
795 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
796 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
797 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
798 
|======
799 
 
800 
 
801 
:sectnums!:
802 
===== _IO_MTIME_EN_
803 
 
804 
[cols="4,4,2"]
805 
[frame="all",grid="none"]
806 
|======
807 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
808 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
809 
See section <<_machine_system_timer_mtime>> for more information.
810 
|======
811 
 
812 
 
813 
:sectnums!:
814 
===== _IO_UART0_EN_
815 
 
816 
[cols="4,4,2"]
817 
[frame="all",grid="none"]
818 
|======
819 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
820 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
821 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
822 
more information.
823 
|======
824 
 
825 
 
826 
:sectnums!:
827 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
828 
 
829 
[cols="4,4,2"]
830 
[frame="all",grid="none"]
831 
|======
832 
| **IO_UART0_RX_FIFO** | _natural_ | 1
833 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
834 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
835 
more information.
836 
|======
837 
 
838 
 
839 
:sectnums!:
840 
===== _IO_UART0_TX_FIFO_
841 
 
842 
[cols="4,4,2"]
843 
[frame="all",grid="none"]
844 
|======
845 
| **IO_UART0_TX_FIFO** | _natural_ | 1
846 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
847 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
848 
more information.
849 
|======
850 
 
851 
 
852 
:sectnums!:
853 60 zero_gravi 
===== _IO_UART1_EN_
854 
 
855 
[cols="4,4,2"]
856 
[frame="all",grid="none"]
857 
|======
858 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
859 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
860 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
861 
|======
862 
 
863 
 
864 
:sectnums!:
865 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
866 
 
867 
[cols="4,4,2"]
868 
[frame="all",grid="none"]
869 
|======
870 
| **IO_UART1_RX_FIFO** | _natural_ | 1
871 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
872 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
873 
more information.
874 
|======
875 
 
876 
 
877 
:sectnums!:
878 
===== _IO_UART1_TX_FIFO_
879 
 
880 
[cols="4,4,2"]
881 
[frame="all",grid="none"]
882 
|======
883 
| **IO_UART1_TX_FIFO** | _natural_ | 1
884 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
885 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
886 
more information.
887 
|======
888 
 
889 
 
890 
:sectnums!:
891 60 zero_gravi 
===== _IO_SPI_EN_
892 
 
893 
[cols="4,4,2"]
894 
[frame="all",grid="none"]
895 
|======
896 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
897 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
898 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
899 
|======
900 
 
901 
 
902 
:sectnums!:
903 
===== _IO_TWI_EN_
904 
 
905 
[cols="4,4,2"]
906 
[frame="all",grid="none"]
907 
|======
908 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
909 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
910 
See section <<_two_wire_serial_interface_controller_twi>> for
911 
more information.
912 
|======
913 
 
914 
 
915 
:sectnums!:
916 
===== _IO_PWM_NUM_CH_
917 
 
918 
[cols="4,4,2"]
919 
[frame="all",grid="none"]
920 
|======
921 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
922 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
923 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
924 
|======
925 
 
926 
 
927 
:sectnums!:
928 
===== _IO_WDT_EN_
929 
 
930 
[cols="4,4,2"]
931 
[frame="all",grid="none"]
932 
|======
933 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
934 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
935 
information.
936 
|======
937 
 
938 
 
939 
:sectnums!:
940 
===== _IO_TRNG_EN_
941 
 
942 
[cols="4,4,2"]
943 
[frame="all",grid="none"]
944 
|======
945 
| **IO_TRNG_EN** | _boolean_ | false
946 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
947 
|======
948 
 
949 
 
950 
:sectnums!:
951 
===== _IO_CFS_EN_
952 
 
953 
[cols="4,4,2"]
954 
[frame="all",grid="none"]
955 
|======
956 
| **IO_CFS_EN** | _boolean_ | false
957 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
958 
|======
959 
 
960 
 
961 
:sectnums!:
962 
===== _IO_CFS_CONFIG_
963 
 
964 
[cols="4,4,2"]
965 
[frame="all",grid="none"]
966 
|======
967 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
968 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
969 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
970 
|======
971 
 
972 
 
973 
:sectnums!:
974 
===== _IO_CFS_IN_SIZE_
975 
 
976 
[cols="4,4,2"]
977 
[frame="all",grid="none"]
978 
|======
979 
| **IO_CFS_IN_SIZE** | _positive_ | 32
980 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
981 
|======
982 
 
983 
 
984 
:sectnums!:
985 
===== _IO_CFS_OUT_SIZE_
986 
 
987 
[cols="4,4,2"]
988 
[frame="all",grid="none"]
989 
|======
990 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
991 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
992 
|======
993 
 
994 
 
995 
:sectnums!:
996 
===== _IO_NEOLED_EN_
997 
 
998 
[cols="4,4,2"]
999 
[frame="all",grid="none"]
1000 
|======
1001 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
1002 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
1003 
See section <<_smart_led_interface_neoled>> for more information.
1004 
|======
1005 
 
1006 
 
1007 62 zero_gravi 
:sectnums!:
1008 
===== _IO_NEOLED_TX_FIFO_
1009 
 
1010 
[cols="4,4,2"]
1011 
[frame="all",grid="none"]
1012 
|======
1013 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
1014 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
1015 
See section <<_smart_led_interface_neoled>> for more information.
1016 
|======
1017 
 
1018 
 
1019 
 
1020 60 zero_gravi 
<<<
1021 
// ####################################################################################################################
1022 
:sectnums:
1023 
=== Processor Interrupts
1024 
 
1025 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
1026 60 zero_gravi 
 
1027 
 
1028 61 zero_gravi 
:sectnums:
1029 
==== RISC-V Standard Interrupts
1030 
 
1031 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1032 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1033 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1034 
<<_traps_exceptions_and_interrupts>> for more information.
1035 60 zero_gravi 
 
1036 61 zero_gravi 
[cols="<3,^2,<11"]
1037 
[options="header",grid="rows"]
1038 
|=======================
1039 
| Top signal | Width | Description
1040 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1041 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1042 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1043 
|=======================
1044 60 zero_gravi 
 
1045 64 zero_gravi 
.Trigger type
1046 62 zero_gravi 
[IMPORTANT]
1047 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1048 66 zero_gravi 
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
1049 65 zero_gravi 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1050 61 zero_gravi 
 
1051 
 
1052 
:sectnums:
1053 
==== Platform External Interrupts
1054 
 
1055 
[cols="<3,^2,<11"]
1056 
[options="header",grid="rows"]
1057 
|=======================
1058 
| Top signal | Width | Description
1059 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1060 
|=======================
1061 
 
1062 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1063 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1064 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1065 
 
1066 64 zero_gravi 
.Trigger type
1067 
[IMPORTANT]
1068 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1069 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1070 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1071 
_fast interrupt request_ (see below).
1072 61 zero_gravi 
 
1073 
 
1074 
:sectnums:
1075 
==== NEORV32-Specific Fast Interrupt Requests
1076 
 
1077 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1078 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1079 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1080 60 zero_gravi 
 
1081 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1082 
the according FIRQ priority; 0 = highest, 15 = lowest):
1083 60 zero_gravi 
 
1084 
.NEORV32 fast interrupt channel mapping
1085 
[cols="^1,<2,<7"]
1086 
[options="header",grid="rows"]
1087 
|=======================
1088 
| Channel | Source | Description
1089 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1090 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1091 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1092 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1093 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1094 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1095 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1096 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1097 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1098 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1099 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1100 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1101 62 zero_gravi 
| 12:15   | - | _reserved_, will never fire
1102 60 zero_gravi 
|=======================
1103 
 
1104 64 zero_gravi 
.Trigger type
1105 
[IMPORTANT]
1106 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1107 66 zero_gravi 
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
1108 65 zero_gravi 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1109 60 zero_gravi 
 
1110 
 
1111 64 zero_gravi 
 
1112 60 zero_gravi 
<<<
1113 
// ####################################################################################################################
1114 
:sectnums:
1115 
=== Address Space
1116 
 
1117 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1118 
By default, this address space is divided into five main regions:
1119 60 zero_gravi 
 
1120 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1121 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1122 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1123 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1124 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1125 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1126 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1127 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1128 60 zero_gravi 
 
1129 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1130 
image::address_space.png[900]
1131 60 zero_gravi 
 
1132 
 
1133 
:sectnums:
1134 
==== CPU Data and Instruction Access
1135 
 
1136 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1137 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1138 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1139 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1140 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1141 
setup a modified von-Neumann architecture.
1142 
 
1143 
.Processor-internal bus architecture
1144 
image::neorv32_bus.png[1300]
1145 
 
1146 
[NOTE]
1147 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1148 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1149 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1150 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1151 
accesses.
1152 
 
1153 
[IMPORTANT]
1154 
Please note that all processor-internal components including the peripheral/IO devices can also be
1155 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1156 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1157 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1158 
PMP system (see <<_machine_physical_memory_protection>>).
1159 
 
1160 61 zero_gravi 
 
1161 60 zero_gravi 
:sectnums:
1162 61 zero_gravi 
==== Address Space Layout
1163 
 
1164 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1165 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1166 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1167 
`rtl/core/neorv32_package.vhd`:
1168 
 
1169 
[source,vhdl]
1170 
----
1171 
-- Architecture Configuration ----------------------------------------------------
1172 
-- ----------------------------------------------------------------------------------
1173 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1174 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1175 
----
1176 
 
1177 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1178 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1179 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1180 
are _aligned_ to a 4-byte boundary.
1181 
 
1182 
[NOTE]
1183 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1184 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1185 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1186 61 zero_gravi 
hardware sources.
1187 
 
1188 
 
1189 
:sectnums:
1190 60 zero_gravi 
==== Physical Memory Attributes
1191 
 
1192 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1193 
Accessing a memory region in a way that violates any of these attributes will raise an according
1194 
access exception..
1195 60 zero_gravi 
 
1196 65 zero_gravi 
* `r` - read access (from CPU data access interface, "loads")
1197 
* `w` - write access (from CPU data access interface, "stores")
1198 
* `x` - execute access (from CPU instruction fetch interface)
1199 
* `a` - atomic access (from CPU data access interface)
1200 
* `8` - byte (8-bit)-accessible (when writing)
1201 
* `16` - half-word (16-bit)-accessible (when writing)
1202 
* `32` - word (32-bit)-accessible (when writing)
1203 60 zero_gravi 
 
1204 61 zero_gravi 
[NOTE]
1205 65 zero_gravi 
Read accesses (loads and instruction fetches) can always access data in
1206 
word, half-word (for instruction fetch only if `C` extension is enabled)
1207 
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
1208 60 zero_gravi 
 
1209 65 zero_gravi 
[TIP]
1210 
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
1211 
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
1212 
provided using the RISC-V <<_machine_physical_memory_protection>>.
1213 
 
1214 60 zero_gravi 
[cols="^1,^2,^2,^3,^2"]
1215 
[options="header",grid="rows"]
1216 
|=======================
1217 65 zero_gravi 
| # | Region                | Base address | Size        | Attributes
1218 
| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
1219 
| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
1220 
| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
1221 
| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
1222 
| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
1223 60 zero_gravi 
|=======================
1224 
 
1225 
 
1226 
:sectnums:
1227 61 zero_gravi 
==== Memory Configuration
1228 60 zero_gravi 
 
1229 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1230 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1231 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1232 
the internal ones. The figure below show some exemplary memory configurations.
1233 60 zero_gravi 
 
1234 61 zero_gravi 
.Exemplary memory configurations
1235 
image::neorv32_memory_configurations.png[800]
1236 60 zero_gravi 
 
1237 61 zero_gravi 
:sectnums!:
1238 
===== Internal Memories
1239 
 
1240 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1241 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1242 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1243 
 
1244 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1245 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1246 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1247 
implemented.
1248 
 
1249 61 zero_gravi 
[TIP]
1250 
The default processor setup uses only _internal_ memories.
1251 60 zero_gravi 
 
1252 61 zero_gravi 
[NOTE]
1253 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1254 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1255 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1256 
any access to the "dead address space" in between will raise an exception that can be caught
1257 
by the runtime environment.
1258 60 zero_gravi 
 
1259 61 zero_gravi 
:sectnums!:
1260 
===== External Memories
1261 
 
1262 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1263 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1264 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1265 
 
1266 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1267 
via the processor's bus interface to external components:
1268 
 
1269 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1270 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1271 
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1272 
 
1273 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1274 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1275 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1276 
memory system.
1277 60 zero_gravi 
 
1278 61 zero_gravi 
[NOTE]
1279 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1280 
the internal peripheral address space will trigger a bus access fault exception.
1281 60 zero_gravi 
 
1282 
 
1283 61 zero_gravi 
:sectnums:
1284 
==== Boot Configuration
1285 
 
1286 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1287 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1288 
 
1289 
.NEORV32 boot configurations
1290 
image::neorv32_boot_configurations.png[800]
1291 
 
1292 
[NOTE]
1293 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1294 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1295 
 
1296 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1297 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1298 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1299 
 
1300 
[NOTE]
1301 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1302 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1303 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1304 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1305 
store it to external _data_ memory and transfers CPU control to that.
1306 
 
1307 
:sectnums!:
1308 
===== Indirect Boot
1309 
 
1310 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
1311 
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1312 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1313 
 
1314 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
1315 
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
1316 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1317 
RAM so the bootloader can write the actual executable to it.
1318 
 
1319 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1320 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1321 
write the executable to the processor-external memory.
1322 
 
1323 
:sectnums!:
1324 
===== Direct Boot
1325 
 
1326 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
1327 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1328 
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
1329 
in order to provide an executable _in_ memory.
1330 
 
1331 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1332 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
1333 
 
1334 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1335 
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
1336 
 
1337 
 
1338 
 
1339 60 zero_gravi 
<<<
1340 
// ####################################################################################################################
1341 
:sectnums:
1342 
=== Processor-Internal Modules
1343 
 
1344 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1345 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1346 
system implements an internal reset generator and a global clock generator/divider.
1347 
 
1348 
**Internal Reset Generator**
1349 
 
1350 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1351 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1352 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1353 
modules to ensure a clean system reset state.
1354 
 
1355 
The hardware reset signal of the processor can either be
1356 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1357 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1358 
clock cycles.
1359 
 
1360 
**Internal Clock Divider**
1361 
 
1362 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1363 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1364 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1365 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1366 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1367 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1368 
power.
1369 
 
1370 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1371 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1372 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1373 
from the top entity's `clk_i` signal.
1374 
 
1375 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1376 
[grid="rows"]
1377 
|=======================
1378 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1379 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1380 
|=======================
1381 
 
1382 
**Peripheral / IO Devices**
1383 
 
1384 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1385 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1386 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1387 
library abstract the specific memory layout for the user.
1388 
 
1389 
[IMPORTANT]
1390 64 zero_gravi 
The base address of each component/module has to be aligned to the
1391 
total size of the module's occupied address space! The occupied address space
1392 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1393 
 
1394 
[IMPORTANT]
1395 60 zero_gravi 
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
1396 
load/store access fault exception is triggered.
1397 
 
1398 
[IMPORTANT]
1399 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1400 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1401 
Processor-internal memories as well as modules connected to the external memory interface can still
1402 
be written with a byte-wide granularity.
1403 
 
1404 
[TIP]
1405 
You should use the provided core software library to interact with the peripheral devices. This
1406 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1407 
register and register bit accesses.
1408 
 
1409 
[TIP]
1410 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1411 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1412 
application start-up code `crt0.S`.
1413 
 
1414 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1415 
 
1416 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1417 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1418 66 zero_gravi 
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
1419 64 zero_gravi 
 
1420 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1421 
 
1422 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1423 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1424 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1425 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1426 
main processor core library include file `sw/lib/include/neorv32.h`.
1427 60 zero_gravi 
 
1428 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1429 
 
1430 
.Low-level hardware access example in C using the pre-defined `struct`
1431 
[source,c]
1432 
----
1433 
// Read from SYSINFO "CLK" register
1434 
uint32_t temp = NEORV32_SYSINFO.CLK;
1435 
----
1436 
 
1437 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1438 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1439 
available:
1440 
 
1441 
* `r/w` registers / bits can be read and written
1442 
* `r/-` registers / bits are read-only; any write access to them has no effect
1443 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1444 
 
1445 
[TIP]
1446 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1447 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1448 
write zero to them to keep compatible with future extension.
1449 
 
1450 
[TIP]
1451 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1452 
written. When reading data from a write-only register the result is undefined.
1453 
 
1454 
 
1455 
include::soc_imem.adoc[]
1456 
 
1457 
include::soc_dmem.adoc[]
1458 
 
1459 
include::soc_bootrom.adoc[]
1460 
 
1461 
include::soc_icache.adoc[]
1462 
 
1463 
include::soc_wishbone.adoc[]
1464 
 
1465 66 zero_gravi 
include::soc_buskeeper.adoc[]
1466 
 
1467 61 zero_gravi 
include::soc_slink.adoc[]
1468 
 
1469 60 zero_gravi 
include::soc_gpio.adoc[]
1470 
 
1471 
include::soc_wdt.adoc[]
1472 
 
1473 
include::soc_mtime.adoc[]
1474 
 
1475 
include::soc_uart.adoc[]
1476 
 
1477 
include::soc_spi.adoc[]
1478 
 
1479 
include::soc_twi.adoc[]
1480 
 
1481 
include::soc_pwm.adoc[]
1482 
 
1483 
include::soc_trng.adoc[]
1484 
 
1485 
include::soc_cfs.adoc[]
1486 
 
1487 
include::soc_neoled.adoc[]
1488 
 
1489 61 zero_gravi 
include::soc_xirq.adoc[]
1490 
 
1491 60 zero_gravi 
include::soc_sysinfo.adoc[]
1492 
 
1493 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.