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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
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interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
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13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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[IMPORTAN]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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since all control signals have defined level.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 0..60 | out | pulse-width modulated channels
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
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|=======================
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122 
 
123 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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**More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
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[TIP]
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Privileged software can determine the actual CPU and processor configuration via the `misa` and the
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<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
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164 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
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Note that hart IDs must be unique within a system.
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
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// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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[TIP]
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See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
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(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
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can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_B_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
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3+| Implement the `B` bit-manipulation sub-extension when _true_.
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See section <<_b_bit_manipulation_operations>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
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requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
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requires a different application binary interface (ABI).
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
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If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
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If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
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to DSP slices via the <<_fast_mul_en>> generic.
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See section <<_m_integer_multiplication_and_division>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_U_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicsr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
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3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
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disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
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no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicntr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
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3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
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Enabling this extension will set the  _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
341 
See section <<_zicntr_cpu_base_counters>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zihpm_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
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3+| Implement hardware performance monitor CSRs when true.
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Enabling this extension will set the  _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
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See section <<_zihpm_hardware_performance_monitors>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
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See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
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:sectnums!:
372 
===== _CPU_EXTENSION_RISCV_Zmmul_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
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cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
381 
 
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// ####################################################################################################################
384 
:sectnums:
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==== Extension Options
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387 
See section <<_instruction_sets_and_extensions>> for more information.
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:sectnums!:
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===== _FAST_MUL_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **FAST_MUL_EN** | _boolean_ | false
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3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
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iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
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utilization. This generic is only relevant when a hardware multiplier CPU extension is
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enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
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<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
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|======
403 
 
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:sectnums!:
406 
===== _FAST_SHIFT_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **FAST_SHIFT_EN** | _boolean_ | false
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3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
413 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
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that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
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cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
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shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
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|======
418 
 
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:sectnums!:
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===== _CPU_CNT_WIDTH_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_CNT_WIDTH** | _natural_ | 64
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3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
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The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
429 66 zero_gravi 
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
430 63 zero_gravi 
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
431 60 zero_gravi 
|======
432 
 
433 
 
434 62 zero_gravi 
:sectnums!:
435 
===== _CPU_IPB_ENTRIES_
436 
 
437 
[cols="4,4,2"]
438 
[frame="all",grid="none"]
439 
|======
440 
| **CPU_IPB_ENTRIES** | _natural_ | 2
441 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
442 
The value has to be a power of two and has to be greater than zero.
443 63 zero_gravi 
Long linear sequences of code can benefit from an increased IPB size.
444 62 zero_gravi 
|======
445 
 
446 
 
447 60 zero_gravi 
// ####################################################################################################################
448 
:sectnums:
449 
==== Physical Memory Protection (PMP)
450 
 
451 
See section <<_pmp_physical_memory_protection>> for more information.
452 
 
453 
 
454 
:sectnums!:
455 
===== _PMP_NUM_REGIONS_
456 
 
457 
[cols="4,4,2"]
458 
[frame="all",grid="none"]
459 
|======
460 
| **PMP_NUM_REGIONS** | _natural_ | 0
461 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
462 63 zero_gravi 
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
463 64 zero_gravi 
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
464 60 zero_gravi 
|======
465 
 
466 
 
467 
:sectnums!:
468 
===== _PMP_MIN_GRANULARITY_
469 
 
470 
[cols="4,4,2"]
471 
[frame="all",grid="none"]
472 
|======
473 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
474 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
475 
|======
476 
 
477 
 
478 
// ####################################################################################################################
479 
:sectnums:
480 
==== Hardware Performance Monitors (HPM)
481 
 
482 66 zero_gravi 
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
483 
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
484 60 zero_gravi 
 
485 
 
486 
:sectnums!:
487 
===== _HPM_NUM_CNTS_
488 
 
489 
[cols="4,4,2"]
490 
[frame="all",grid="none"]
491 
|======
492 
| **HPM_NUM_CNTS** | _natural_ | 0
493 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
494 66 zero_gravi 
hardware performance monitor logic will be implemented at all.
495 60 zero_gravi 
|======
496 
 
497 
 
498 
:sectnums!:
499 
===== _HPM_CNT_WIDTH_
500 
 
501 
[cols="4,4,2"]
502 
[frame="all",grid="none"]
503 
|======
504 
| **HPM_CNT_WIDTH** | _natural_ | 40
505 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
506 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
507 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
508 
|======
509 
 
510 
 
511 
// ####################################################################################################################
512 
:sectnums:
513 
==== Internal Instruction Memory
514 
 
515 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
516 
 
517 
 
518 
:sectnums!:
519 
===== _MEM_INT_IMEM_EN_
520 
 
521 
[cols="4,4,2"]
522 
[frame="all",grid="none"]
523 
|======
524 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
525 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
526 
|======
527 
 
528 
 
529 
:sectnums!:
530 
===== _MEM_INT_IMEM_SIZE_
531 
 
532 
[cols="4,4,2"]
533 
[frame="all",grid="none"]
534 
|======
535 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
536 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
537 60 zero_gravi 
|======
538 
 
539 
 
540 
// ####################################################################################################################
541 
:sectnums:
542 
==== Internal Data Memory
543 
 
544 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
545 
 
546 
 
547 
:sectnums!:
548 
===== _MEM_INT_DMEM_EN_
549 
 
550 
[cols="4,4,2"]
551 
[frame="all",grid="none"]
552 
|======
553 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
554 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
555 
|======
556 
 
557 
 
558 
:sectnums!:
559 
===== _MEM_INT_DMEM_SIZE_
560 
 
561 
[cols="4,4,2"]
562 
[frame="all",grid="none"]
563 
|======
564 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
565 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
566 60 zero_gravi 
|======
567 
 
568 
 
569 
// ####################################################################################################################
570 
:sectnums:
571 
==== Internal Cache Memory
572 
 
573 
See section <<_processor_internal_instruction_cache_icache>> for more information.
574 
 
575 
 
576 
:sectnums!:
577 
===== _ICACHE_EN_
578 
 
579 
[cols="4,4,2"]
580 
[frame="all",grid="none"]
581 
|======
582 
| **ICACHE_EN** | _boolean_ | false
583 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
584 
and instruction memories there is not point of implementing the i-cache.
585 60 zero_gravi 
|======
586 
 
587 
 
588 
:sectnums!:
589 
===== _ICACHE_NUM_BLOCK_
590 
 
591 
[cols="4,4,2"]
592 
[frame="all",grid="none"]
593 
|======
594 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
595 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
596 63 zero_gravi 
effect when <<_icache_dmem_en>> is false.
597 60 zero_gravi 
|======
598 
 
599 
 
600 
:sectnums!:
601 
===== _ICACHE_BLOCK_SIZE_
602 
 
603 
[cols="4,4,2"]
604 
[frame="all",grid="none"]
605 
|======
606 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
607 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
608 63 zero_gravi 
<<_icache_dmem_en>> is _false_.
609 60 zero_gravi 
|======
610 
 
611 
 
612 
:sectnums!:
613 
===== _ICACHE_ASSOCIATIVITY_
614 
 
615 
[cols="4,4,2"]
616 
[frame="all",grid="none"]
617 
|======
618 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
619 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
620 63 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_dmem_en>> is _false_.
621 60 zero_gravi 
|======
622 
 
623 
 
624 
// ####################################################################################################################
625 
:sectnums:
626 
==== External Memory Interface
627 
 
628 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
629 
 
630 
 
631 
:sectnums!:
632 
===== _MEM_EXT_EN_
633 
 
634 
[cols="4,4,2"]
635 
[frame="all",grid="none"]
636 
|======
637 
| **MEM_EXT_EN** | _boolean_ | false
638 
3+| Implement external bus interface (WISHBONE) when _true_.
639 
|======
640 
 
641 
 
642 
:sectnums!:
643 
===== _MEM_EXT_TIMEOUT_
644 
 
645 
[cols="4,4,2"]
646 
[frame="all",grid="none"]
647 
|======
648 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
649 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
650 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
651 60 zero_gravi 
|======
652 
 
653 
 
654 62 zero_gravi 
:sectnums!:
655 
===== _MEM_EXT_PIPE_MODE_
656 
 
657 
[cols="4,4,2"]
658 
[frame="all",grid="none"]
659 
|======
660 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
661 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
662 
Use _pipelined_ Wishbone protocol when _true_.
663 62 zero_gravi 
|======
664 
 
665 
 
666 
:sectnums!:
667 
===== _MEM_EXT_BIG_ENDIAN_
668 
 
669 
[cols="4,4,2"]
670 
[frame="all",grid="none"]
671 
|======
672 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
673 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
674 62 zero_gravi 
|======
675 
 
676 
 
677 
:sectnums!:
678 
===== _MEM_EXT_ASYNC_RX_
679 
 
680 
[cols="4,4,2"]
681 
[frame="all",grid="none"]
682 
|======
683 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
684 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
685 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
686 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
687 62 zero_gravi 
|======
688 
 
689 
 
690 60 zero_gravi 
// ####################################################################################################################
691 
:sectnums:
692 61 zero_gravi 
==== Stream Link Interface
693 
 
694 
See section <<_stream_link_interface_slink>> for more information.
695 
 
696 
 
697 
:sectnums!:
698 
===== _SLINK_NUM_TX_
699 
 
700 
[cols="4,4,2"]
701 
[frame="all",grid="none"]
702 
|======
703 
| **SLINK_NUM_TX** | _natural_ | 0
704 
3+| Number of TX (send) links to implement. Valid values are 0..8.
705 
|======
706 
 
707 
 
708 
:sectnums!:
709 
===== _SLINK_NUM_RX_
710 
 
711 
[cols="4,4,2"]
712 
[frame="all",grid="none"]
713 
|======
714 
| **SLINK_NUM_RX** | _natural_ | 0
715 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
716 
|======
717 
 
718 
 
719 
:sectnums!:
720 
===== _SLINK_TX_FIFO_
721 
 
722 
[cols="4,4,2"]
723 
[frame="all",grid="none"]
724 
|======
725 
| **SLINK_TX_FIFO** | _natural_ | 1
726 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
727 
|======
728 
 
729 
 
730 
:sectnums!:
731 
===== _SLINK_RX_FIFO_
732 
 
733 
[cols="4,4,2"]
734 
[frame="all",grid="none"]
735 
|======
736 
| **SLINK_RX_FIFO** | _natural_ | 1
737 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
738 
|======
739 
 
740 
 
741 
// ####################################################################################################################
742 
:sectnums:
743 
==== External Interrupt Controller
744 
 
745 
See section <<_external_interrupt_controller_xirq>> for more information.
746 
 
747 
 
748 
:sectnums!:
749 
===== _XIRQ_NUM_CH_
750 
 
751 
[cols="4,4,2"]
752 
[frame="all",grid="none"]
753 
|======
754 
| **XIRQ_NUM_CH** | _natural_ | 0
755 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
756 
|======
757 
 
758 
 
759 
:sectnums!:
760 
===== _XIRQ_TRIGGER_TYPE_
761 
 
762 
[cols="4,4,2"]
763 
[frame="all",grid="none"]
764 
|======
765 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
766 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
767 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
768 61 zero_gravi 
|======
769 
 
770 
 
771 
:sectnums!:
772 
===== _XIRQ_TRIGGER_POLARITY_
773 
 
774 
[cols="4,4,2"]
775 
[frame="all",grid="none"]
776 
|======
777 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
778 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
779 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
780 61 zero_gravi 
|======
781 
 
782 
 
783 
// ####################################################################################################################
784 
:sectnums:
785 60 zero_gravi 
==== Processor Peripheral/IO Modules
786 
 
787 
See section <<_processor_internal_modules>> for more information.
788 
 
789 
 
790 
:sectnums!:
791 
===== _IO_GPIO_EN_
792 
 
793 
[cols="4,4,2"]
794 
[frame="all",grid="none"]
795 
|======
796 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
797 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
798 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
799 
|======
800 
 
801 
 
802 
:sectnums!:
803 
===== _IO_MTIME_EN_
804 
 
805 
[cols="4,4,2"]
806 
[frame="all",grid="none"]
807 
|======
808 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
809 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
810 
See section <<_machine_system_timer_mtime>> for more information.
811 
|======
812 
 
813 
 
814 
:sectnums!:
815 
===== _IO_UART0_EN_
816 
 
817 
[cols="4,4,2"]
818 
[frame="all",grid="none"]
819 
|======
820 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
821 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
822 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
823 
more information.
824 
|======
825 
 
826 
 
827 
:sectnums!:
828 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
829 
 
830 
[cols="4,4,2"]
831 
[frame="all",grid="none"]
832 
|======
833 
| **IO_UART0_RX_FIFO** | _natural_ | 1
834 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
835 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
836 
more information.
837 
|======
838 
 
839 
 
840 
:sectnums!:
841 
===== _IO_UART0_TX_FIFO_
842 
 
843 
[cols="4,4,2"]
844 
[frame="all",grid="none"]
845 
|======
846 
| **IO_UART0_TX_FIFO** | _natural_ | 1
847 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
848 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
849 
more information.
850 
|======
851 
 
852 
 
853 
:sectnums!:
854 60 zero_gravi 
===== _IO_UART1_EN_
855 
 
856 
[cols="4,4,2"]
857 
[frame="all",grid="none"]
858 
|======
859 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
860 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
861 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
862 
|======
863 
 
864 
 
865 
:sectnums!:
866 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
867 
 
868 
[cols="4,4,2"]
869 
[frame="all",grid="none"]
870 
|======
871 
| **IO_UART1_RX_FIFO** | _natural_ | 1
872 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
873 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
874 
more information.
875 
|======
876 
 
877 
 
878 
:sectnums!:
879 
===== _IO_UART1_TX_FIFO_
880 
 
881 
[cols="4,4,2"]
882 
[frame="all",grid="none"]
883 
|======
884 
| **IO_UART1_TX_FIFO** | _natural_ | 1
885 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
886 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
887 
more information.
888 
|======
889 
 
890 
 
891 
:sectnums!:
892 60 zero_gravi 
===== _IO_SPI_EN_
893 
 
894 
[cols="4,4,2"]
895 
[frame="all",grid="none"]
896 
|======
897 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
898 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
899 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
900 
|======
901 
 
902 
 
903 
:sectnums!:
904 
===== _IO_TWI_EN_
905 
 
906 
[cols="4,4,2"]
907 
[frame="all",grid="none"]
908 
|======
909 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
910 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
911 
See section <<_two_wire_serial_interface_controller_twi>> for
912 
more information.
913 
|======
914 
 
915 
 
916 
:sectnums!:
917 
===== _IO_PWM_NUM_CH_
918 
 
919 
[cols="4,4,2"]
920 
[frame="all",grid="none"]
921 
|======
922 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
923 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
924 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
925 
|======
926 
 
927 
 
928 
:sectnums!:
929 
===== _IO_WDT_EN_
930 
 
931 
[cols="4,4,2"]
932 
[frame="all",grid="none"]
933 
|======
934 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
935 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
936 
information.
937 
|======
938 
 
939 
 
940 
:sectnums!:
941 
===== _IO_TRNG_EN_
942 
 
943 
[cols="4,4,2"]
944 
[frame="all",grid="none"]
945 
|======
946 
| **IO_TRNG_EN** | _boolean_ | false
947 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
948 
|======
949 
 
950 
 
951 
:sectnums!:
952 
===== _IO_CFS_EN_
953 
 
954 
[cols="4,4,2"]
955 
[frame="all",grid="none"]
956 
|======
957 
| **IO_CFS_EN** | _boolean_ | false
958 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
959 
|======
960 
 
961 
 
962 
:sectnums!:
963 
===== _IO_CFS_CONFIG_
964 
 
965 
[cols="4,4,2"]
966 
[frame="all",grid="none"]
967 
|======
968 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
969 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
970 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
971 
|======
972 
 
973 
 
974 
:sectnums!:
975 
===== _IO_CFS_IN_SIZE_
976 
 
977 
[cols="4,4,2"]
978 
[frame="all",grid="none"]
979 
|======
980 
| **IO_CFS_IN_SIZE** | _positive_ | 32
981 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
982 
|======
983 
 
984 
 
985 
:sectnums!:
986 
===== _IO_CFS_OUT_SIZE_
987 
 
988 
[cols="4,4,2"]
989 
[frame="all",grid="none"]
990 
|======
991 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
992 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
993 
|======
994 
 
995 
 
996 
:sectnums!:
997 
===== _IO_NEOLED_EN_
998 
 
999 
[cols="4,4,2"]
1000 
[frame="all",grid="none"]
1001 
|======
1002 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
1003 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
1004 
See section <<_smart_led_interface_neoled>> for more information.
1005 
|======
1006 
 
1007 
 
1008 62 zero_gravi 
:sectnums!:
1009 
===== _IO_NEOLED_TX_FIFO_
1010 
 
1011 
[cols="4,4,2"]
1012 
[frame="all",grid="none"]
1013 
|======
1014 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
1015 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
1016 
See section <<_smart_led_interface_neoled>> for more information.
1017 
|======
1018 
 
1019 
 
1020 67 zero_gravi 
:sectnums!:
1021 
===== _IO_GPTMR_EN_
1022 62 zero_gravi 
 
1023 67 zero_gravi 
[cols="4,4,2"]
1024 
[frame="all",grid="none"]
1025 
|======
1026 
| **IO_GPTMR_EN** | _boolean_ | false
1027 
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
1028 
See section <<_general_purpose_timer_gptmr>> for more information.
1029 
|======
1030 
 
1031 
 
1032 
 
1033 60 zero_gravi 
<<<
1034 
// ####################################################################################################################
1035 
:sectnums:
1036 
=== Processor Interrupts
1037 
 
1038 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
1039 60 zero_gravi 
 
1040 
 
1041 61 zero_gravi 
:sectnums:
1042 
==== RISC-V Standard Interrupts
1043 
 
1044 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1045 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1046 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1047 
<<_traps_exceptions_and_interrupts>> for more information.
1048 60 zero_gravi 
 
1049 61 zero_gravi 
[cols="<3,^2,<11"]
1050 
[options="header",grid="rows"]
1051 
|=======================
1052 
| Top signal | Width | Description
1053 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1054 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1055 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1056 
|=======================
1057 60 zero_gravi 
 
1058 64 zero_gravi 
.Trigger type
1059 62 zero_gravi 
[IMPORTANT]
1060 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1061 66 zero_gravi 
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
1062 65 zero_gravi 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1063 61 zero_gravi 
 
1064 
 
1065 
:sectnums:
1066 
==== Platform External Interrupts
1067 
 
1068 
[cols="<3,^2,<11"]
1069 
[options="header",grid="rows"]
1070 
|=======================
1071 
| Top signal | Width | Description
1072 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1073 
|=======================
1074 
 
1075 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1076 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1077 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1078 
 
1079 64 zero_gravi 
.Trigger type
1080 
[IMPORTANT]
1081 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1082 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1083 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1084 
_fast interrupt request_ (see below).
1085 61 zero_gravi 
 
1086 
 
1087 
:sectnums:
1088 
==== NEORV32-Specific Fast Interrupt Requests
1089 
 
1090 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1091 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1092 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1093 60 zero_gravi 
 
1094 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1095 
the according FIRQ priority; 0 = highest, 15 = lowest):
1096 60 zero_gravi 
 
1097 
.NEORV32 fast interrupt channel mapping
1098 
[cols="^1,<2,<7"]
1099 
[options="header",grid="rows"]
1100 
|=======================
1101 
| Channel | Source | Description
1102 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1103 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1104 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1105 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1106 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1107 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1108 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1109 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1110 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1111 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1112 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1113 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1114 67 zero_gravi 
| 12      | <<_general_purpose_timer_gptmr,GPTMR>> | General purpose timer interrupt
1115 
| 13:15   | - | _reserved_, will never fire
1116 60 zero_gravi 
|=======================
1117 
 
1118 64 zero_gravi 
.Trigger type
1119 
[IMPORTANT]
1120 65 zero_gravi 
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
1121 66 zero_gravi 
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
1122 65 zero_gravi 
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
1123 60 zero_gravi 
 
1124 
 
1125 64 zero_gravi 
 
1126 60 zero_gravi 
<<<
1127 
// ####################################################################################################################
1128 
:sectnums:
1129 
=== Address Space
1130 
 
1131 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1132 
By default, this address space is divided into five main regions:
1133 60 zero_gravi 
 
1134 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1135 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1136 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1137 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1138 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1139 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1140 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1141 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1142 60 zero_gravi 
 
1143 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1144 
image::address_space.png[900]
1145 60 zero_gravi 
 
1146 
 
1147 
:sectnums:
1148 
==== CPU Data and Instruction Access
1149 
 
1150 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1151 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1152 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1153 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1154 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1155 
setup a modified von-Neumann architecture.
1156 
 
1157 
.Processor-internal bus architecture
1158 
image::neorv32_bus.png[1300]
1159 
 
1160 
[NOTE]
1161 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1162 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1163 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1164 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1165 
accesses.
1166 
 
1167 
[IMPORTANT]
1168 
Please note that all processor-internal components including the peripheral/IO devices can also be
1169 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1170 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1171 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1172 
PMP system (see <<_machine_physical_memory_protection>>).
1173 
 
1174 61 zero_gravi 
 
1175 60 zero_gravi 
:sectnums:
1176 61 zero_gravi 
==== Address Space Layout
1177 
 
1178 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1179 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1180 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1181 
`rtl/core/neorv32_package.vhd`:
1182 
 
1183 
[source,vhdl]
1184 
----
1185 
-- Architecture Configuration ----------------------------------------------------
1186 
-- ----------------------------------------------------------------------------------
1187 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1188 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1189 
----
1190 
 
1191 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1192 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1193 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1194 
are _aligned_ to a 4-byte boundary.
1195 
 
1196 
[NOTE]
1197 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1198 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1199 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1200 61 zero_gravi 
hardware sources.
1201 
 
1202 
 
1203 
:sectnums:
1204 60 zero_gravi 
==== Physical Memory Attributes
1205 
 
1206 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1207 
Accessing a memory region in a way that violates any of these attributes will raise an according
1208 
access exception..
1209 60 zero_gravi 
 
1210 65 zero_gravi 
* `r` - read access (from CPU data access interface, "loads")
1211 
* `w` - write access (from CPU data access interface, "stores")
1212 
* `x` - execute access (from CPU instruction fetch interface)
1213 
* `a` - atomic access (from CPU data access interface)
1214 
* `8` - byte (8-bit)-accessible (when writing)
1215 
* `16` - half-word (16-bit)-accessible (when writing)
1216 
* `32` - word (32-bit)-accessible (when writing)
1217 60 zero_gravi 
 
1218 61 zero_gravi 
[NOTE]
1219 65 zero_gravi 
Read accesses (loads and instruction fetches) can always access data in
1220 
word, half-word (for instruction fetch only if `C` extension is enabled)
1221 
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
1222 60 zero_gravi 
 
1223 65 zero_gravi 
[TIP]
1224 
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
1225 
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
1226 
provided using the RISC-V <<_machine_physical_memory_protection>>.
1227 
 
1228 60 zero_gravi 
[cols="^1,^2,^2,^3,^2"]
1229 
[options="header",grid="rows"]
1230 
|=======================
1231 65 zero_gravi 
| # | Region                | Base address | Size        | Attributes
1232 
| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
1233 
| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
1234 
| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
1235 
| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
1236 
| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
1237 60 zero_gravi 
|=======================
1238 
 
1239 
 
1240 
:sectnums:
1241 61 zero_gravi 
==== Memory Configuration
1242 60 zero_gravi 
 
1243 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1244 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1245 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1246 
the internal ones. The figure below show some exemplary memory configurations.
1247 60 zero_gravi 
 
1248 61 zero_gravi 
.Exemplary memory configurations
1249 
image::neorv32_memory_configurations.png[800]
1250 60 zero_gravi 
 
1251 61 zero_gravi 
:sectnums!:
1252 
===== Internal Memories
1253 
 
1254 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1255 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1256 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1257 
 
1258 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1259 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1260 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1261 
implemented.
1262 
 
1263 61 zero_gravi 
[TIP]
1264 
The default processor setup uses only _internal_ memories.
1265 60 zero_gravi 
 
1266 61 zero_gravi 
[NOTE]
1267 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1268 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1269 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1270 
any access to the "dead address space" in between will raise an exception that can be caught
1271 
by the runtime environment.
1272 60 zero_gravi 
 
1273 61 zero_gravi 
:sectnums!:
1274 
===== External Memories
1275 
 
1276 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1277 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1278 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1279 
 
1280 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1281 
via the processor's bus interface to external components:
1282 
 
1283 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1284 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1285 
* access to the bootloader ROM and beyond → addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1286 
 
1287 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1288 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1289 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1290 
memory system.
1291 60 zero_gravi 
 
1292 61 zero_gravi 
[NOTE]
1293 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1294 
the internal peripheral address space will trigger a bus access fault exception.
1295 60 zero_gravi 
 
1296 
 
1297 61 zero_gravi 
:sectnums:
1298 
==== Boot Configuration
1299 
 
1300 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1301 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1302 
 
1303 
.NEORV32 boot configurations
1304 
image::neorv32_boot_configurations.png[800]
1305 
 
1306 
[NOTE]
1307 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1308 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1309 
 
1310 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1311 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1312 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1313 
 
1314 
[NOTE]
1315 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1316 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1317 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1318 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1319 
store it to external _data_ memory and transfers CPU control to that.
1320 
 
1321 
:sectnums!:
1322 
===== Indirect Boot
1323 
 
1324 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This general setup is enabled
1325 
by setting the <<_int_bootloader_en>> generic to true, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1326 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1327 
 
1328 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and store it to
1329 
the _instruction address space_ so the CPU can execute it. Boot scenario **1a** uses the processor-internal IMEM
1330 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1331 
RAM so the bootloader can write the actual executable to it.
1332 
 
1333 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1334 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1335 
write the executable to the processor-external memory.
1336 
 
1337 
:sectnums!:
1338 
===== Direct Boot
1339 
 
1340 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader. Hence, the <<_int_bootloader_en>>
1341 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1342 
directly begin executing code from the instruction address space after reset. A "pre-initialization mechanism is required
1343 
in order to provide an executable _in_ memory.
1344 
 
1345 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1346 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable.
1347 
 
1348 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1349 
system designer is responsible for providing a initialized external memory that contains the actual application to be executed.
1350 
 
1351 
 
1352 
 
1353 60 zero_gravi 
<<<
1354 
// ####################################################################################################################
1355 
:sectnums:
1356 
=== Processor-Internal Modules
1357 
 
1358 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1359 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1360 
system implements an internal reset generator and a global clock generator/divider.
1361 
 
1362 
**Internal Reset Generator**
1363 
 
1364 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1365 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1366 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1367 
modules to ensure a clean system reset state.
1368 
 
1369 
The hardware reset signal of the processor can either be
1370 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1371 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1372 
clock cycles.
1373 
 
1374 
**Internal Clock Divider**
1375 
 
1376 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1377 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1378 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1379 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1380 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1381 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1382 
power.
1383 
 
1384 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1385 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1386 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1387 
from the top entity's `clk_i` signal.
1388 
 
1389 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1390 
[grid="rows"]
1391 
|=======================
1392 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1393 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1394 
|=======================
1395 
 
1396 
**Peripheral / IO Devices**
1397 
 
1398 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1399 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1400 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1401 
library abstract the specific memory layout for the user.
1402 
 
1403 
[IMPORTANT]
1404 64 zero_gravi 
The base address of each component/module has to be aligned to the
1405 
total size of the module's occupied address space! The occupied address space
1406 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1407 
 
1408 
[IMPORTANT]
1409 60 zero_gravi 
When accessing an IO device that hast not been implemented (via the according _IO_x_EN_ generic), a
1410 
load/store access fault exception is triggered.
1411 
 
1412 
[IMPORTANT]
1413 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1414 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1415 
Processor-internal memories as well as modules connected to the external memory interface can still
1416 
be written with a byte-wide granularity.
1417 
 
1418 
[TIP]
1419 
You should use the provided core software library to interact with the peripheral devices. This
1420 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1421 
register and register bit accesses.
1422 
 
1423 
[TIP]
1424 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1425 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1426 
application start-up code `crt0.S`.
1427 
 
1428 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1429 
 
1430 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1431 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1432 66 zero_gravi 
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
1433 64 zero_gravi 
 
1434 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1435 
 
1436 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1437 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1438 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1439 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1440 
main processor core library include file `sw/lib/include/neorv32.h`.
1441 60 zero_gravi 
 
1442 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1443 
 
1444 
.Low-level hardware access example in C using the pre-defined `struct`
1445 
[source,c]
1446 
----
1447 
// Read from SYSINFO "CLK" register
1448 
uint32_t temp = NEORV32_SYSINFO.CLK;
1449 
----
1450 
 
1451 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1452 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1453 
available:
1454 
 
1455 
* `r/w` registers / bits can be read and written
1456 
* `r/-` registers / bits are read-only; any write access to them has no effect
1457 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1458 
 
1459 
[TIP]
1460 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1461 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1462 
write zero to them to keep compatible with future extension.
1463 
 
1464 
[TIP]
1465 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1466 
written. When reading data from a write-only register the result is undefined.
1467 
 
1468 
 
1469 
include::soc_imem.adoc[]
1470 
 
1471 
include::soc_dmem.adoc[]
1472 
 
1473 
include::soc_bootrom.adoc[]
1474 
 
1475 
include::soc_icache.adoc[]
1476 
 
1477 
include::soc_wishbone.adoc[]
1478 
 
1479 66 zero_gravi 
include::soc_buskeeper.adoc[]
1480 
 
1481 61 zero_gravi 
include::soc_slink.adoc[]
1482 
 
1483 60 zero_gravi 
include::soc_gpio.adoc[]
1484 
 
1485 
include::soc_wdt.adoc[]
1486 
 
1487 
include::soc_mtime.adoc[]
1488 
 
1489 
include::soc_uart.adoc[]
1490 
 
1491 
include::soc_spi.adoc[]
1492 
 
1493 
include::soc_twi.adoc[]
1494 
 
1495 
include::soc_pwm.adoc[]
1496 
 
1497 
include::soc_trng.adoc[]
1498 
 
1499 
include::soc_cfs.adoc[]
1500 
 
1501 
include::soc_neoled.adoc[]
1502 
 
1503 61 zero_gravi 
include::soc_xirq.adoc[]
1504 
 
1505 67 zero_gravi 
include::soc_gptmr.adoc[]
1506 
 
1507 60 zero_gravi 
include::soc_sysinfo.adoc[]

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