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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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6 
The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
7 
interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
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13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
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* _optional_ execute in place module (<<_execute_in_place_module_xip,**XIP**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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34 
 
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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.Default Values of Ports
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[IMPORTANT]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
48 
since all control signals have defined level.
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.Configurable Amount of Channels
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[IMPORTANT]
52 
Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
53 
of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
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amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
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in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
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bits/channels are hardwired to zero.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optionalfootnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data outputfootnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)**
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| `xip_csn_o` | 1 | out | chi select, low-active
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| `xip_clk_o` | 1 | out | serial clock
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| `xip_sdi_i` | 1 | in  | serial data input
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| `xip_sdo_o` | 1 | out | serial data output
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 60 | out | pulse-width modulated channels
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
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|=======================
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137 
 
138 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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143 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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147 
[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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**More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration]**.
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154 
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the `misa` and the
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<<_system_configuration_information_memory_sysinfo, SYSINFO>> registers.
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[TIP]
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Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
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to verify the configuration of the processor generics is valid.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
182 
 
183 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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188 
See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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201 
 
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the `mhartid` CSR.
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Note that hart IDs must be unique within a system.
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
237 
 
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239 
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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[TIP]
244 
See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
245 
(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _extension options_
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can be determined via memory-mapped registers of the <<_system_configuration_information_memory_sysinfo>> module.
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248 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
259 
 
260 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_B_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
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3+| Implement the `B` bit-manipulation sub-extension when _true_.
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See section <<_b_bit_manipulation_operations>> for more information.
270 
|======
271 
 
272 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
283 
 
284 
 
285 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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288 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
293 
requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
294 
requires a different application binary interface (ABI).
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|======
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297 
 
298 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
304 
| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
306 
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
307 
If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
308 
to DSP slices via the <<_fast_mul_en>> generic.
309 
See section <<_m_integer_multiplication_and_division>> for more information.
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|======
311 
 
312 
 
313 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_U_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
319 
| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
323 
 
324 
 
325 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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328 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
331 
| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
335 
 
336 
 
337 
:sectnums!:
338 
===== _CPU_EXTENSION_RISCV_Zicsr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
343 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
344 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
345 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
346 
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
349 
 
350 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicntr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
357 
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
358 
3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
359 
Enabling this extension will set the  _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
360 
See section <<_zicntr_cpu_base_counters>> for more information.
361 
|======
362 
 
363 
 
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:sectnums!:
365 
===== _CPU_EXTENSION_RISCV_Zihpm_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
370 
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
371 
3+| Implement hardware performance monitor CSRs when true.
372 
Enabling this extension will set the  _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
373 
See section <<_zihpm_hardware_performance_monitors>> for more information.
374 
|======
375 
 
376 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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380 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
383 
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
386 
See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
388 
 
389 
 
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:sectnums!:
391 
===== _CPU_EXTENSION_RISCV_Zmmul_
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393 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
396 
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
398 
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
400 
 
401 
 
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// ####################################################################################################################
403 
:sectnums:
404 
==== Extension Options
405 
 
406 
See section <<_instruction_sets_and_extensions>> for more information.
407 
 
408 
 
409 
:sectnums!:
410 
===== _FAST_MUL_EN_
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412 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
415 
| **FAST_MUL_EN** | _boolean_ | false
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3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
417 
iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
418 
utilization. This generic is only relevant when a hardware multiplier CPU extension is
419 
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
420 
<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
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|======
422 
 
423 
 
424 
:sectnums!:
425 
===== _FAST_SHIFT_EN_
426 
 
427 
[cols="4,4,2"]
428 
[frame="all",grid="none"]
429 
|======
430 
| **FAST_SHIFT_EN** | _boolean_ | false
431 63 zero_gravi 
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
432 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
433 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
434 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
435 66 zero_gravi 
shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
436 60 zero_gravi 
|======
437 
 
438 
 
439 
:sectnums!:
440 
===== _CPU_CNT_WIDTH_
441 
 
442 
[cols="4,4,2"]
443 
[frame="all",grid="none"]
444 
|======
445 62 zero_gravi 
| **CPU_CNT_WIDTH** | _natural_ | 64
446 64 zero_gravi 
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
447 70 zero_gravi 
The maximum value is 64, the minimum value is 0. See section <<_machine_counter_and_timer_csrs>> for more information.
448 66 zero_gravi 
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
449 63 zero_gravi 
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
450 60 zero_gravi 
|======
451 
 
452 
 
453 62 zero_gravi 
:sectnums!:
454 
===== _CPU_IPB_ENTRIES_
455 
 
456 
[cols="4,4,2"]
457 
[frame="all",grid="none"]
458 
|======
459 
| **CPU_IPB_ENTRIES** | _natural_ | 2
460 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
461 
The value has to be a power of two and has to be greater than zero.
462 63 zero_gravi 
Long linear sequences of code can benefit from an increased IPB size.
463 62 zero_gravi 
|======
464 
 
465 
 
466 60 zero_gravi 
// ####################################################################################################################
467 
:sectnums:
468 
==== Physical Memory Protection (PMP)
469 
 
470 
See section <<_pmp_physical_memory_protection>> for more information.
471 
 
472 
 
473 
:sectnums!:
474 
===== _PMP_NUM_REGIONS_
475 
 
476 
[cols="4,4,2"]
477 
[frame="all",grid="none"]
478 
|======
479 
| **PMP_NUM_REGIONS** | _natural_ | 0
480 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
481 63 zero_gravi 
protection logic will be implemented at all. Setting <<_pmp_num_regions>>_ > 0 will set the _SYSINFO_CPU_PMP_ flag
482 64 zero_gravi 
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
483 60 zero_gravi 
|======
484 
 
485 
 
486 
:sectnums!:
487 
===== _PMP_MIN_GRANULARITY_
488 
 
489 
[cols="4,4,2"]
490 
[frame="all",grid="none"]
491 
|======
492 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
493 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
494 
|======
495 
 
496 
 
497 
// ####################################################################################################################
498 
:sectnums:
499 
==== Hardware Performance Monitors (HPM)
500 
 
501 66 zero_gravi 
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
502 
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
503 60 zero_gravi 
 
504 
 
505 
:sectnums!:
506 
===== _HPM_NUM_CNTS_
507 
 
508 
[cols="4,4,2"]
509 
[frame="all",grid="none"]
510 
|======
511 
| **HPM_NUM_CNTS** | _natural_ | 0
512 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
513 66 zero_gravi 
hardware performance monitor logic will be implemented at all.
514 60 zero_gravi 
|======
515 
 
516 
 
517 
:sectnums!:
518 
===== _HPM_CNT_WIDTH_
519 
 
520 
[cols="4,4,2"]
521 
[frame="all",grid="none"]
522 
|======
523 
| **HPM_CNT_WIDTH** | _natural_ | 40
524 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
525 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
526 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
527 
|======
528 
 
529 
 
530 
// ####################################################################################################################
531 
:sectnums:
532 
==== Internal Instruction Memory
533 
 
534 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
535 
 
536 
 
537 
:sectnums!:
538 
===== _MEM_INT_IMEM_EN_
539 
 
540 
[cols="4,4,2"]
541 
[frame="all",grid="none"]
542 
|======
543 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
544 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
545 
|======
546 
 
547 
 
548 
:sectnums!:
549 
===== _MEM_INT_IMEM_SIZE_
550 
 
551 
[cols="4,4,2"]
552 
[frame="all",grid="none"]
553 
|======
554 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
555 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
556 60 zero_gravi 
|======
557 
 
558 
 
559 
// ####################################################################################################################
560 
:sectnums:
561 
==== Internal Data Memory
562 
 
563 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
564 
 
565 
 
566 
:sectnums!:
567 
===== _MEM_INT_DMEM_EN_
568 
 
569 
[cols="4,4,2"]
570 
[frame="all",grid="none"]
571 
|======
572 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
573 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
574 
|======
575 
 
576 
 
577 
:sectnums!:
578 
===== _MEM_INT_DMEM_SIZE_
579 
 
580 
[cols="4,4,2"]
581 
[frame="all",grid="none"]
582 
|======
583 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
584 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
585 60 zero_gravi 
|======
586 
 
587 
 
588 
// ####################################################################################################################
589 
:sectnums:
590 
==== Internal Cache Memory
591 
 
592 
See section <<_processor_internal_instruction_cache_icache>> for more information.
593 
 
594 
 
595 
:sectnums!:
596 
===== _ICACHE_EN_
597 
 
598 
[cols="4,4,2"]
599 
[frame="all",grid="none"]
600 
|======
601 
| **ICACHE_EN** | _boolean_ | false
602 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
603 
and instruction memories there is not point of implementing the i-cache.
604 60 zero_gravi 
|======
605 
 
606 
 
607 
:sectnums!:
608 70 zero_gravi 
===== _ICACHE_NUM_BLOCKS_
609 60 zero_gravi 
 
610 
[cols="4,4,2"]
611 
[frame="all",grid="none"]
612 
|======
613 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
614 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
615 70 zero_gravi 
effect when <<_icache_en>> is false.
616 60 zero_gravi 
|======
617 
 
618 
 
619 
:sectnums!:
620 
===== _ICACHE_BLOCK_SIZE_
621 
 
622 
[cols="4,4,2"]
623 
[frame="all",grid="none"]
624 
|======
625 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
626 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
627 70 zero_gravi 
<<_icache_en>> is _false_.
628 60 zero_gravi 
|======
629 
 
630 
 
631 
:sectnums!:
632 
===== _ICACHE_ASSOCIATIVITY_
633 
 
634 
[cols="4,4,2"]
635 
[frame="all",grid="none"]
636 
|======
637 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
638 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
639 70 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_en>> is _false_.
640 60 zero_gravi 
|======
641 
 
642 
 
643 
// ####################################################################################################################
644 
:sectnums:
645 
==== External Memory Interface
646 
 
647 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
648 
 
649 
 
650 
:sectnums!:
651 
===== _MEM_EXT_EN_
652 
 
653 
[cols="4,4,2"]
654 
[frame="all",grid="none"]
655 
|======
656 
| **MEM_EXT_EN** | _boolean_ | false
657 
3+| Implement external bus interface (WISHBONE) when _true_.
658 
|======
659 
 
660 
 
661 
:sectnums!:
662 
===== _MEM_EXT_TIMEOUT_
663 
 
664 
[cols="4,4,2"]
665 
[frame="all",grid="none"]
666 
|======
667 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
668 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
669 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
670 60 zero_gravi 
|======
671 
 
672 
 
673 62 zero_gravi 
:sectnums!:
674 
===== _MEM_EXT_PIPE_MODE_
675 
 
676 
[cols="4,4,2"]
677 
[frame="all",grid="none"]
678 
|======
679 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
680 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
681 
Use _pipelined_ Wishbone protocol when _true_.
682 62 zero_gravi 
|======
683 
 
684 
 
685 
:sectnums!:
686 
===== _MEM_EXT_BIG_ENDIAN_
687 
 
688 
[cols="4,4,2"]
689 
[frame="all",grid="none"]
690 
|======
691 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
692 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
693 62 zero_gravi 
|======
694 
 
695 
 
696 
:sectnums!:
697 
===== _MEM_EXT_ASYNC_RX_
698 
 
699 
[cols="4,4,2"]
700 
[frame="all",grid="none"]
701 
|======
702 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
703 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
704 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
705 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
706 62 zero_gravi 
|======
707 
 
708 
 
709 60 zero_gravi 
// ####################################################################################################################
710 
:sectnums:
711 61 zero_gravi 
==== Stream Link Interface
712 
 
713 
See section <<_stream_link_interface_slink>> for more information.
714 
 
715 
 
716 
:sectnums!:
717 
===== _SLINK_NUM_TX_
718 
 
719 
[cols="4,4,2"]
720 
[frame="all",grid="none"]
721 
|======
722 
| **SLINK_NUM_TX** | _natural_ | 0
723 
3+| Number of TX (send) links to implement. Valid values are 0..8.
724 
|======
725 
 
726 
 
727 
:sectnums!:
728 
===== _SLINK_NUM_RX_
729 
 
730 
[cols="4,4,2"]
731 
[frame="all",grid="none"]
732 
|======
733 
| **SLINK_NUM_RX** | _natural_ | 0
734 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
735 
|======
736 
 
737 
 
738 
:sectnums!:
739 
===== _SLINK_TX_FIFO_
740 
 
741 
[cols="4,4,2"]
742 
[frame="all",grid="none"]
743 
|======
744 
| **SLINK_TX_FIFO** | _natural_ | 1
745 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
746 
|======
747 
 
748 
 
749 
:sectnums!:
750 
===== _SLINK_RX_FIFO_
751 
 
752 
[cols="4,4,2"]
753 
[frame="all",grid="none"]
754 
|======
755 
| **SLINK_RX_FIFO** | _natural_ | 1
756 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
757 
|======
758 
 
759 
 
760 
// ####################################################################################################################
761 
:sectnums:
762 
==== External Interrupt Controller
763 
 
764 
See section <<_external_interrupt_controller_xirq>> for more information.
765 
 
766 
 
767 
:sectnums!:
768 
===== _XIRQ_NUM_CH_
769 
 
770 
[cols="4,4,2"]
771 
[frame="all",grid="none"]
772 
|======
773 
| **XIRQ_NUM_CH** | _natural_ | 0
774 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
775 
|======
776 
 
777 
 
778 
:sectnums!:
779 
===== _XIRQ_TRIGGER_TYPE_
780 
 
781 
[cols="4,4,2"]
782 
[frame="all",grid="none"]
783 
|======
784 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
785 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
786 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
787 61 zero_gravi 
|======
788 
 
789 
 
790 
:sectnums!:
791 
===== _XIRQ_TRIGGER_POLARITY_
792 
 
793 
[cols="4,4,2"]
794 
[frame="all",grid="none"]
795 
|======
796 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
797 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
798 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
799 61 zero_gravi 
|======
800 
 
801 
 
802 
// ####################################################################################################################
803 
:sectnums:
804 60 zero_gravi 
==== Processor Peripheral/IO Modules
805 
 
806 
See section <<_processor_internal_modules>> for more information.
807 
 
808 
 
809 
:sectnums!:
810 
===== _IO_GPIO_EN_
811 
 
812 
[cols="4,4,2"]
813 
[frame="all",grid="none"]
814 
|======
815 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
816 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
817 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
818 
|======
819 
 
820 
 
821 
:sectnums!:
822 
===== _IO_MTIME_EN_
823 
 
824 
[cols="4,4,2"]
825 
[frame="all",grid="none"]
826 
|======
827 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
828 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
829 
See section <<_machine_system_timer_mtime>> for more information.
830 
|======
831 
 
832 
 
833 
:sectnums!:
834 
===== _IO_UART0_EN_
835 
 
836 
[cols="4,4,2"]
837 
[frame="all",grid="none"]
838 
|======
839 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
840 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
841 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
842 
more information.
843 
|======
844 
 
845 
 
846 
:sectnums!:
847 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
848 
 
849 
[cols="4,4,2"]
850 
[frame="all",grid="none"]
851 
|======
852 
| **IO_UART0_RX_FIFO** | _natural_ | 1
853 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
854 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
855 
more information.
856 
|======
857 
 
858 
 
859 
:sectnums!:
860 
===== _IO_UART0_TX_FIFO_
861 
 
862 
[cols="4,4,2"]
863 
[frame="all",grid="none"]
864 
|======
865 
| **IO_UART0_TX_FIFO** | _natural_ | 1
866 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
867 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
868 
more information.
869 
|======
870 
 
871 
 
872 
:sectnums!:
873 60 zero_gravi 
===== _IO_UART1_EN_
874 
 
875 
[cols="4,4,2"]
876 
[frame="all",grid="none"]
877 
|======
878 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
879 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
880 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
881 
|======
882 
 
883 
 
884 
:sectnums!:
885 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
886 
 
887 
[cols="4,4,2"]
888 
[frame="all",grid="none"]
889 
|======
890 
| **IO_UART1_RX_FIFO** | _natural_ | 1
891 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
892 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
893 
more information.
894 
|======
895 
 
896 
 
897 
:sectnums!:
898 
===== _IO_UART1_TX_FIFO_
899 
 
900 
[cols="4,4,2"]
901 
[frame="all",grid="none"]
902 
|======
903 
| **IO_UART1_TX_FIFO** | _natural_ | 1
904 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
905 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
906 
more information.
907 
|======
908 
 
909 
 
910 
:sectnums!:
911 60 zero_gravi 
===== _IO_SPI_EN_
912 
 
913 
[cols="4,4,2"]
914 
[frame="all",grid="none"]
915 
|======
916 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
917 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
918 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
919 
|======
920 
 
921 
 
922 
:sectnums!:
923 
===== _IO_TWI_EN_
924 
 
925 
[cols="4,4,2"]
926 
[frame="all",grid="none"]
927 
|======
928 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
929 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
930 
See section <<_two_wire_serial_interface_controller_twi>> for
931 
more information.
932 
|======
933 
 
934 
 
935 
:sectnums!:
936 
===== _IO_PWM_NUM_CH_
937 
 
938 
[cols="4,4,2"]
939 
[frame="all",grid="none"]
940 
|======
941 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
942 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
943 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
944 
|======
945 
 
946 
 
947 
:sectnums!:
948 
===== _IO_WDT_EN_
949 
 
950 
[cols="4,4,2"]
951 
[frame="all",grid="none"]
952 
|======
953 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
954 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
955 
information.
956 
|======
957 
 
958 
 
959 
:sectnums!:
960 
===== _IO_TRNG_EN_
961 
 
962 
[cols="4,4,2"]
963 
[frame="all",grid="none"]
964 
|======
965 
| **IO_TRNG_EN** | _boolean_ | false
966 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
967 
|======
968 
 
969 
 
970 
:sectnums!:
971 
===== _IO_CFS_EN_
972 
 
973 
[cols="4,4,2"]
974 
[frame="all",grid="none"]
975 
|======
976 
| **IO_CFS_EN** | _boolean_ | false
977 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
978 
|======
979 
 
980 
 
981 
:sectnums!:
982 
===== _IO_CFS_CONFIG_
983 
 
984 
[cols="4,4,2"]
985 
[frame="all",grid="none"]
986 
|======
987 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
988 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
989 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
990 
|======
991 
 
992 
 
993 
:sectnums!:
994 
===== _IO_CFS_IN_SIZE_
995 
 
996 
[cols="4,4,2"]
997 
[frame="all",grid="none"]
998 
|======
999 
| **IO_CFS_IN_SIZE** | _positive_ | 32
1000 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
1001 
|======
1002 
 
1003 
 
1004 
:sectnums!:
1005 
===== _IO_CFS_OUT_SIZE_
1006 
 
1007 
[cols="4,4,2"]
1008 
[frame="all",grid="none"]
1009 
|======
1010 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
1011 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
1012 
|======
1013 
 
1014 
 
1015 
:sectnums!:
1016 
===== _IO_NEOLED_EN_
1017 
 
1018 
[cols="4,4,2"]
1019 
[frame="all",grid="none"]
1020 
|======
1021 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
1022 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
1023 
See section <<_smart_led_interface_neoled>> for more information.
1024 
|======
1025 
 
1026 
 
1027 62 zero_gravi 
:sectnums!:
1028 
===== _IO_NEOLED_TX_FIFO_
1029 
 
1030 
[cols="4,4,2"]
1031 
[frame="all",grid="none"]
1032 
|======
1033 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
1034 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
1035 
See section <<_smart_led_interface_neoled>> for more information.
1036 
|======
1037 
 
1038 
 
1039 67 zero_gravi 
:sectnums!:
1040 
===== _IO_GPTMR_EN_
1041 62 zero_gravi 
 
1042 67 zero_gravi 
[cols="4,4,2"]
1043 
[frame="all",grid="none"]
1044 
|======
1045 
| **IO_GPTMR_EN** | _boolean_ | false
1046 
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
1047 
See section <<_general_purpose_timer_gptmr>> for more information.
1048 
|======
1049 
 
1050 
 
1051 70 zero_gravi 
:sectnums!:
1052 
===== _IO_XIP_EN_
1053 67 zero_gravi 
 
1054 70 zero_gravi 
[cols="4,4,2"]
1055 
[frame="all",grid="none"]
1056 
|======
1057 
| **IO_XIP_EN** | _boolean_ | false
1058 
3+| Implement the execute in place module (XIP) when _true_.
1059 
See section <<_execute_in_place_module_xip>> for more information.
1060 
|======
1061 
 
1062 
 
1063 
 
1064 60 zero_gravi 
<<<
1065 
// ####################################################################################################################
1066 
:sectnums:
1067 
=== Processor Interrupts
1068 
 
1069 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
1070 60 zero_gravi 
 
1071 
 
1072 61 zero_gravi 
:sectnums:
1073 
==== RISC-V Standard Interrupts
1074 
 
1075 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1076 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1077 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1078 
<<_traps_exceptions_and_interrupts>> for more information.
1079 60 zero_gravi 
 
1080 61 zero_gravi 
[cols="<3,^2,<11"]
1081 
[options="header",grid="rows"]
1082 
|=======================
1083 
| Top signal | Width | Description
1084 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1085 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1086 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1087 
|=======================
1088 60 zero_gravi 
 
1089 64 zero_gravi 
.Trigger type
1090 62 zero_gravi 
[IMPORTANT]
1091 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1092 
be explicitly cleared by setting the according `mip` CSR bit.
1093 61 zero_gravi 
 
1094 
 
1095 
:sectnums:
1096 
==== Platform External Interrupts
1097 
 
1098 
[cols="<3,^2,<11"]
1099 
[options="header",grid="rows"]
1100 
|=======================
1101 
| Top signal | Width | Description
1102 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1103 
|=======================
1104 
 
1105 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1106 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1107 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1108 
 
1109 64 zero_gravi 
.Trigger type
1110 
[IMPORTANT]
1111 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1112 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1113 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1114 
_fast interrupt request_ (see below).
1115 61 zero_gravi 
 
1116 
 
1117 
:sectnums:
1118 
==== NEORV32-Specific Fast Interrupt Requests
1119 
 
1120 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1121 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1122 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1123 60 zero_gravi 
 
1124 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1125 
the according FIRQ priority; 0 = highest, 15 = lowest):
1126 60 zero_gravi 
 
1127 
.NEORV32 fast interrupt channel mapping
1128 
[cols="^1,<2,<7"]
1129 
[options="header",grid="rows"]
1130 
|=======================
1131 
| Channel | Source | Description
1132 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1133 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1134 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1135 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1136 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1137 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1138 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1139 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1140 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1141 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1142 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1143 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1144 67 zero_gravi 
| 12      | <<_general_purpose_timer_gptmr,GPTMR>> | General purpose timer interrupt
1145 
| 13:15   | - | _reserved_, will never fire
1146 60 zero_gravi 
|=======================
1147 
 
1148 64 zero_gravi 
.Trigger type
1149 
[IMPORTANT]
1150 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1151 
be explicitly cleared by setting the according `mip` CSR bit.
1152 60 zero_gravi 
 
1153 
 
1154 64 zero_gravi 
 
1155 60 zero_gravi 
<<<
1156 
// ####################################################################################################################
1157 
:sectnums:
1158 
=== Address Space
1159 
 
1160 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1161 
By default, this address space is divided into five main regions:
1162 60 zero_gravi 
 
1163 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1164 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1165 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1166 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1167 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1168 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1169 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1170 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1171 60 zero_gravi 
 
1172 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1173 
image::address_space.png[900]
1174 60 zero_gravi 
 
1175 
 
1176 
:sectnums:
1177 
==== CPU Data and Instruction Access
1178 
 
1179 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1180 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1181 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1182 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1183 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1184 
setup a modified von-Neumann architecture.
1185 
 
1186 
.Processor-internal bus architecture
1187 
image::neorv32_bus.png[1300]
1188 
 
1189 
[NOTE]
1190 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1191 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1192 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1193 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1194 
accesses.
1195 
 
1196 
[IMPORTANT]
1197 
Please note that all processor-internal components including the peripheral/IO devices can also be
1198 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1199 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1200 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1201 70 zero_gravi 
PMP system (see <<_machine_physical_memory_protection_csrs>>).
1202 60 zero_gravi 
 
1203 61 zero_gravi 
 
1204 60 zero_gravi 
:sectnums:
1205 61 zero_gravi 
==== Address Space Layout
1206 
 
1207 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1208 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1209 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1210 
`rtl/core/neorv32_package.vhd`:
1211 
 
1212 
[source,vhdl]
1213 
----
1214 
-- Architecture Configuration ----------------------------------------------------
1215 
-- ----------------------------------------------------------------------------------
1216 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1217 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1218 
----
1219 
 
1220 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1221 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1222 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1223 
are _aligned_ to a 4-byte boundary.
1224 
 
1225 
[NOTE]
1226 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1227 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1228 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1229 61 zero_gravi 
hardware sources.
1230 
 
1231 
 
1232 
:sectnums:
1233 60 zero_gravi 
==== Physical Memory Attributes
1234 
 
1235 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1236 
Accessing a memory region in a way that violates any of these attributes will raise an according
1237 
access exception..
1238 60 zero_gravi 
 
1239 65 zero_gravi 
* `r` - read access (from CPU data access interface, "loads")
1240 
* `w` - write access (from CPU data access interface, "stores")
1241 
* `x` - execute access (from CPU instruction fetch interface)
1242 
* `a` - atomic access (from CPU data access interface)
1243 
* `8` - byte (8-bit)-accessible (when writing)
1244 
* `16` - half-word (16-bit)-accessible (when writing)
1245 
* `32` - word (32-bit)-accessible (when writing)
1246 60 zero_gravi 
 
1247 61 zero_gravi 
[NOTE]
1248 65 zero_gravi 
Read accesses (loads and instruction fetches) can always access data in
1249 
word, half-word (for instruction fetch only if `C` extension is enabled)
1250 
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
1251 60 zero_gravi 
 
1252 65 zero_gravi 
[TIP]
1253 
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
1254 
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
1255 70 zero_gravi 
provided using the RISC-V <<_machine_physical_memory_protection_csrs>>.
1256 65 zero_gravi 
 
1257 60 zero_gravi 
[cols="^1,^2,^2,^3,^2"]
1258 
[options="header",grid="rows"]
1259 
|=======================
1260 65 zero_gravi 
| # | Region                | Base address | Size        | Attributes
1261 
| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
1262 
| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
1263 
| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
1264 
| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
1265 
| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
1266 60 zero_gravi 
|=======================
1267 
 
1268 
 
1269 
:sectnums:
1270 61 zero_gravi 
==== Memory Configuration
1271 60 zero_gravi 
 
1272 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1273 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1274 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1275 
the internal ones. The figure below show some exemplary memory configurations.
1276 60 zero_gravi 
 
1277 61 zero_gravi 
.Exemplary memory configurations
1278 
image::neorv32_memory_configurations.png[800]
1279 60 zero_gravi 
 
1280 61 zero_gravi 
:sectnums!:
1281 
===== Internal Memories
1282 
 
1283 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1284 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1285 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1286 
 
1287 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1288 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1289 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1290 
implemented.
1291 
 
1292 61 zero_gravi 
[TIP]
1293 
The default processor setup uses only _internal_ memories.
1294 60 zero_gravi 
 
1295 61 zero_gravi 
[NOTE]
1296 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1297 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1298 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1299 
any access to the "dead address space" in between will raise an exception that can be caught
1300 
by the runtime environment.
1301 60 zero_gravi 
 
1302 61 zero_gravi 
:sectnums!:
1303 
===== External Memories
1304 
 
1305 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1306 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1307 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1308 
 
1309 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1310 
via the processor's bus interface to external components:
1311 
 
1312 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1313 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1314 70 zero_gravi 
* access to the bootloader ROM and beyond -> addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1315 60 zero_gravi 
 
1316 70 zero_gravi 
[NOTE]
1317 
If the Execute In Place module (XIP) is implemented accesses map to this module are not forwarded to the
1318 
external memory interface. See section <<_execute_in_place_module_xip>> for more information.
1319 
 
1320 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1321 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1322 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1323 
memory system.
1324 60 zero_gravi 
 
1325 61 zero_gravi 
[NOTE]
1326 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1327 
the internal peripheral address space will trigger a bus access fault exception.
1328 60 zero_gravi 
 
1329 
 
1330 61 zero_gravi 
:sectnums:
1331 
==== Boot Configuration
1332 
 
1333 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1334 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1335 
 
1336 
.NEORV32 boot configurations
1337 
image::neorv32_boot_configurations.png[800]
1338 
 
1339 
[NOTE]
1340 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1341 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1342 
 
1343 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1344 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1345 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1346 
 
1347 
[NOTE]
1348 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1349 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1350 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1351 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1352 
store it to external _data_ memory and transfers CPU control to that.
1353 
 
1354 
:sectnums!:
1355 
===== Indirect Boot
1356 
 
1357 68 zero_gravi 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This boot setup is enabled
1358 
by setting the <<_int_bootloader_en>> generic to _true_, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1359 61 zero_gravi 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1360 68 zero_gravi 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and copies it to
1361 
the beginning of the _instruction address space_ so the CPU can execute it.
1362 61 zero_gravi 
 
1363 68 zero_gravi 
Boot scenario **1a** uses the processor-internal IMEM
1364 61 zero_gravi 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1365 68 zero_gravi 
RAM so the bootloader can copy the actual executable to it.
1366 61 zero_gravi 
 
1367 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1368 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1369 68 zero_gravi 
copy the executable to the processor-external memory. Hence, the external memory has to be implemented as RAM.
1370 61 zero_gravi 
 
1371 
:sectnums!:
1372 
===== Direct Boot
1373 
 
1374 68 zero_gravi 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader since the <<_int_bootloader_en>>
1375 61 zero_gravi 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1376 68 zero_gravi 
directly begin executing code from the beginning of the instruction address space after reset. An application-specific
1377 
"pre-initialization" mechanism is required in order to provide an executable _in_ memory.
1378 61 zero_gravi 
 
1379 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1380 68 zero_gravi 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable during synthesis.
1381 61 zero_gravi 
 
1382 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1383 68 zero_gravi 
system designer is responsible for providing an initialized external memory that contains the actual application to be executed.
1384 
If the external is not already initialized after reset, a simple ROM containing a "polling loop" can be implemented that is
1385 
exited as soon as the application logic has finished initializing the memory with the acutal application code.
1386 61 zero_gravi 
 
1387 
 
1388 
 
1389 60 zero_gravi 
<<<
1390 
// ####################################################################################################################
1391 
:sectnums:
1392 
=== Processor-Internal Modules
1393 
 
1394 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1395 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1396 
system implements an internal reset generator and a global clock generator/divider.
1397 
 
1398 
**Internal Reset Generator**
1399 
 
1400 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1401 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1402 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1403 
modules to ensure a clean system reset state.
1404 
 
1405 
The hardware reset signal of the processor can either be
1406 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1407 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1408 
clock cycles.
1409 
 
1410 
**Internal Clock Divider**
1411 
 
1412 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1413 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1414 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1415 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1416 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1417 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1418 
power.
1419 
 
1420 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1421 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1422 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1423 
from the top entity's `clk_i` signal.
1424 
 
1425 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1426 
[grid="rows"]
1427 
|=======================
1428 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1429 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1430 
|=======================
1431 
 
1432 
**Peripheral / IO Devices**
1433 
 
1434 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1435 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1436 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1437 
library abstract the specific memory layout for the user.
1438 
 
1439 
[IMPORTANT]
1440 64 zero_gravi 
The base address of each component/module has to be aligned to the
1441 
total size of the module's occupied address space! The occupied address space
1442 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1443 
 
1444 
[IMPORTANT]
1445 70 zero_gravi 
When accessing an IO device that hast not been implemented (via the according generic), a
1446 60 zero_gravi 
load/store access fault exception is triggered.
1447 
 
1448 
[IMPORTANT]
1449 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1450 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1451 
Processor-internal memories as well as modules connected to the external memory interface can still
1452 
be written with a byte-wide granularity.
1453 
 
1454 70 zero_gravi 
[NOTE]
1455 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1456 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1457 
application start-up code `crt0.S`.
1458 
 
1459 60 zero_gravi 
[TIP]
1460 
You should use the provided core software library to interact with the peripheral devices. This
1461 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1462 
register and register bit accesses.
1463 
 
1464 
[TIP]
1465 69 zero_gravi 
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
1466 
 
1467 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1468 
 
1469 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1470 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1471 66 zero_gravi 
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
1472 64 zero_gravi 
 
1473 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1474 
 
1475 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1476 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1477 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1478 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1479 
main processor core library include file `sw/lib/include/neorv32.h`.
1480 60 zero_gravi 
 
1481 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1482 
 
1483 
.Low-level hardware access example in C using the pre-defined `struct`
1484 
[source,c]
1485 
----
1486 
// Read from SYSINFO "CLK" register
1487 
uint32_t temp = NEORV32_SYSINFO.CLK;
1488 
----
1489 
 
1490 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1491 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1492 
available:
1493 
 
1494 
* `r/w` registers / bits can be read and written
1495 
* `r/-` registers / bits are read-only; any write access to them has no effect
1496 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1497 
 
1498 70 zero_gravi 
[NOTE]
1499 60 zero_gravi 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1500 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1501 
write zero to them to keep compatible with future extension.
1502 
 
1503 70 zero_gravi 
[NOTE]
1504 60 zero_gravi 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1505 
written. When reading data from a write-only register the result is undefined.
1506 
 
1507 
 
1508 
include::soc_imem.adoc[]
1509 
 
1510 
include::soc_dmem.adoc[]
1511 
 
1512 
include::soc_bootrom.adoc[]
1513 
 
1514 
include::soc_icache.adoc[]
1515 
 
1516 
include::soc_wishbone.adoc[]
1517 
 
1518 66 zero_gravi 
include::soc_buskeeper.adoc[]
1519 
 
1520 61 zero_gravi 
include::soc_slink.adoc[]
1521 
 
1522 60 zero_gravi 
include::soc_gpio.adoc[]
1523 
 
1524 
include::soc_wdt.adoc[]
1525 
 
1526 
include::soc_mtime.adoc[]
1527 
 
1528 
include::soc_uart.adoc[]
1529 
 
1530 
include::soc_spi.adoc[]
1531 
 
1532 
include::soc_twi.adoc[]
1533 
 
1534 
include::soc_pwm.adoc[]
1535 
 
1536 
include::soc_trng.adoc[]
1537 
 
1538 
include::soc_cfs.adoc[]
1539 
 
1540 
include::soc_neoled.adoc[]
1541 
 
1542 61 zero_gravi 
include::soc_xirq.adoc[]
1543 
 
1544 67 zero_gravi 
include::soc_gptmr.adoc[]
1545 
 
1546 70 zero_gravi 
include::soc_xip.adoc[]
1547 
 
1548 60 zero_gravi 
include::soc_sysinfo.adoc[]

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