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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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6 
The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
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interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
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13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
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* _optional_ execute in place module (<<_execute_in_place_module_xip,**XIP**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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34 
 
35 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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.Default Values of Ports
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[NOTE]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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since all control signals have defined level.
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.Configurable Amount of Channels
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[NOTE]
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Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
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of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
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amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
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in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
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bits/channels are hardwired to zero.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optional footnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data output footnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)**
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| `xip_csn_o` | 1 | out | chi select, low-active
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| `xip_clk_o` | 1 | out | serial clock
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| `xip_sdi_i` | 1 | in  | serial data input
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| `xip_sdo_o` | 1 | out | serial data output
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 60 | out | pulse-width modulated channels
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
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|=======================
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137 
 
138 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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143 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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 +
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More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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155 
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the <<_misa>> and <<_mxisa>> CSRs (CPU)
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and the <<_system_configuration_information_memory_sysinfo, SYSINFO>> (processor) memory-mapped registers.
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[TIP]
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Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
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to verify the configuration of the processor generics is valid.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
183 
 
184 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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189 
See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the <<_mhartid>> CSR.
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Note that hart IDs must be unique within a system.
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
238 
 
239 
 
240 
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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.Discovering ISA Extensions
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[TIP]
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See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
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(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _tuning options_
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can be determined via the NEORV32-specific <<_mxisa>> CSR.
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250 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
261 
 
262 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_B_
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266 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
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3+| Implement the `B` bit-manipulation sub-extension when _true_.
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See section <<_b_bit_manipulation_operations>> for more information.
272 
|======
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274 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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278 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
285 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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290 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
293 
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
295 
requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
296 
requires a different application binary interface (ABI).
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|======
298 
 
299 
 
300 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
308 
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
309 
If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
310 
to DSP slices via the <<_fast_mul_en>> generic.
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See section <<_m_integer_multiplication_and_division>> for more information.
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|======
313 
 
314 
 
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:sectnums!:
316 
===== _CPU_EXTENSION_RISCV_U_
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318 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
325 
 
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327 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
337 
 
338 
 
339 
:sectnums!:
340 
===== _CPU_EXTENSION_RISCV_Zicsr_
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342 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
345 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
346 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
347 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
348 
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
351 
 
352 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicntr_
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356 
[cols="4,4,2"]
357 
[frame="all",grid="none"]
358 
|======
359 
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
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3+| Implement the basic CPU <<_machine_counter_and_timer_csrs>> (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
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See section <<_zicntr_cpu_base_counters>> for more information.
362 
|======
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:sectnums!:
366 
===== _CPU_EXTENSION_RISCV_Zihpm_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
371 
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
372 
3+| Implement hardware performance monitor CSRs when true.
373 
See section <<_zihpm_hardware_performance_monitors>> for more information.
374 
|======
375 
 
376 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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380 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
383 
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
386 
See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
388 
 
389 
 
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:sectnums!:
391 
===== _CPU_EXTENSION_RISCV_Zmmul_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
396 
| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
398 
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
400 
 
401 
 
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:sectnums!:
403 
===== _CPU_EXTENSION_RISCV_Zxcfu_
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405 
[cols="4,4,2"]
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[frame="all",grid="none"]
407 
|======
408 
| **CPU_EXTENSION_RISCV_Zxcfu** | _boolean_ | false
409 
3+| NEORV32-specific "custom RISC-V" ISA extensions: Implement the <<_custom_functions_unit_cfu>> for user-defined
410 
custom instruction when _true_. See section <<_zxcfu_custom_instructions_extension_cfu>> for more information.
411 
|======
412 
 
413 
 
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// ####################################################################################################################
415 
:sectnums:
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==== Tuning Options
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These are generics to fine-tune certain ISA extensions and CPU features.
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See section <<_instruction_sets_and_extensions>> for more information.
420 
 
421 
 
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:sectnums!:
423 
===== _FAST_MUL_EN_
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425 
[cols="4,4,2"]
426 
[frame="all",grid="none"]
427 
|======
428 
| **FAST_MUL_EN** | _boolean_ | false
429 63 zero_gravi 
3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
430 
iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
431 
utilization. This generic is only relevant when a hardware multiplier CPU extension is
432 
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
433 
<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
434 60 zero_gravi 
|======
435 
 
436 
 
437 
:sectnums!:
438 
===== _FAST_SHIFT_EN_
439 
 
440 
[cols="4,4,2"]
441 
[frame="all",grid="none"]
442 
|======
443 
| **FAST_SHIFT_EN** | _boolean_ | false
444 63 zero_gravi 
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
445 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
446 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
447 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
448 66 zero_gravi 
shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
449 60 zero_gravi 
|======
450 
 
451 
 
452 
:sectnums!:
453 
===== _CPU_CNT_WIDTH_
454 
 
455 
[cols="4,4,2"]
456 
[frame="all",grid="none"]
457 
|======
458 62 zero_gravi 
| **CPU_CNT_WIDTH** | _natural_ | 64
459 64 zero_gravi 
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
460 70 zero_gravi 
The maximum value is 64, the minimum value is 0. See section <<_machine_counter_and_timer_csrs>> for more information.
461 66 zero_gravi 
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
462 63 zero_gravi 
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
463 60 zero_gravi 
|======
464 
 
465 
 
466 62 zero_gravi 
:sectnums!:
467 
===== _CPU_IPB_ENTRIES_
468 
 
469 
[cols="4,4,2"]
470 
[frame="all",grid="none"]
471 
|======
472 
| **CPU_IPB_ENTRIES** | _natural_ | 2
473 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
474 
The value has to be a power of two and has to be greater than zero.
475 63 zero_gravi 
Long linear sequences of code can benefit from an increased IPB size.
476 62 zero_gravi 
|======
477 
 
478 
 
479 60 zero_gravi 
// ####################################################################################################################
480 
:sectnums:
481 
==== Physical Memory Protection (PMP)
482 
 
483 
See section <<_pmp_physical_memory_protection>> for more information.
484 
 
485 
 
486 
:sectnums!:
487 
===== _PMP_NUM_REGIONS_
488 
 
489 
[cols="4,4,2"]
490 
[frame="all",grid="none"]
491 
|======
492 
| **PMP_NUM_REGIONS** | _natural_ | 0
493 
3+| Total number of implemented protections regions (0..64). If this generics is zero no physical memory
494 72 zero_gravi 
protection logic will be implemented at all.
495 60 zero_gravi 
|======
496 
 
497 
 
498 
:sectnums!:
499 
===== _PMP_MIN_GRANULARITY_
500 
 
501 
[cols="4,4,2"]
502 
[frame="all",grid="none"]
503 
|======
504 
| **PMP_MIN_GRANULARITY** | _natural_ | 64*1024
505 
3+| Minimal region granularity in bytes. Has to be a power of two. Has to be at least 8 bytes.
506 
|======
507 
 
508 
 
509 
// ####################################################################################################################
510 
:sectnums:
511 
==== Hardware Performance Monitors (HPM)
512 
 
513 66 zero_gravi 
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
514 
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
515 60 zero_gravi 
 
516 
 
517 
:sectnums!:
518 
===== _HPM_NUM_CNTS_
519 
 
520 
[cols="4,4,2"]
521 
[frame="all",grid="none"]
522 
|======
523 
| **HPM_NUM_CNTS** | _natural_ | 0
524 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
525 66 zero_gravi 
hardware performance monitor logic will be implemented at all.
526 60 zero_gravi 
|======
527 
 
528 
 
529 
:sectnums!:
530 
===== _HPM_CNT_WIDTH_
531 
 
532 
[cols="4,4,2"]
533 
[frame="all",grid="none"]
534 
|======
535 
| **HPM_CNT_WIDTH** | _natural_ | 40
536 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
537 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
538 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
539 
|======
540 
 
541 
 
542 
// ####################################################################################################################
543 
:sectnums:
544 
==== Internal Instruction Memory
545 
 
546 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
547 
 
548 
 
549 
:sectnums!:
550 
===== _MEM_INT_IMEM_EN_
551 
 
552 
[cols="4,4,2"]
553 
[frame="all",grid="none"]
554 
|======
555 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
556 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
557 
|======
558 
 
559 
 
560 
:sectnums!:
561 
===== _MEM_INT_IMEM_SIZE_
562 
 
563 
[cols="4,4,2"]
564 
[frame="all",grid="none"]
565 
|======
566 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
567 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
568 60 zero_gravi 
|======
569 
 
570 
 
571 
// ####################################################################################################################
572 
:sectnums:
573 
==== Internal Data Memory
574 
 
575 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
576 
 
577 
 
578 
:sectnums!:
579 
===== _MEM_INT_DMEM_EN_
580 
 
581 
[cols="4,4,2"]
582 
[frame="all",grid="none"]
583 
|======
584 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
585 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
586 
|======
587 
 
588 
 
589 
:sectnums!:
590 
===== _MEM_INT_DMEM_SIZE_
591 
 
592 
[cols="4,4,2"]
593 
[frame="all",grid="none"]
594 
|======
595 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
596 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
597 60 zero_gravi 
|======
598 
 
599 
 
600 
// ####################################################################################################################
601 
:sectnums:
602 
==== Internal Cache Memory
603 
 
604 
See section <<_processor_internal_instruction_cache_icache>> for more information.
605 
 
606 
 
607 
:sectnums!:
608 
===== _ICACHE_EN_
609 
 
610 
[cols="4,4,2"]
611 
[frame="all",grid="none"]
612 
|======
613 
| **ICACHE_EN** | _boolean_ | false
614 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
615 
and instruction memories there is not point of implementing the i-cache.
616 60 zero_gravi 
|======
617 
 
618 
 
619 
:sectnums!:
620 70 zero_gravi 
===== _ICACHE_NUM_BLOCKS_
621 60 zero_gravi 
 
622 
[cols="4,4,2"]
623 
[frame="all",grid="none"]
624 
|======
625 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
626 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
627 70 zero_gravi 
effect when <<_icache_en>> is false.
628 60 zero_gravi 
|======
629 
 
630 
 
631 
:sectnums!:
632 
===== _ICACHE_BLOCK_SIZE_
633 
 
634 
[cols="4,4,2"]
635 
[frame="all",grid="none"]
636 
|======
637 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
638 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
639 70 zero_gravi 
<<_icache_en>> is _false_.
640 60 zero_gravi 
|======
641 
 
642 
 
643 
:sectnums!:
644 
===== _ICACHE_ASSOCIATIVITY_
645 
 
646 
[cols="4,4,2"]
647 
[frame="all",grid="none"]
648 
|======
649 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
650 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
651 70 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_en>> is _false_.
652 60 zero_gravi 
|======
653 
 
654 
 
655 
// ####################################################################################################################
656 
:sectnums:
657 
==== External Memory Interface
658 
 
659 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
660 
 
661 
 
662 
:sectnums!:
663 
===== _MEM_EXT_EN_
664 
 
665 
[cols="4,4,2"]
666 
[frame="all",grid="none"]
667 
|======
668 
| **MEM_EXT_EN** | _boolean_ | false
669 
3+| Implement external bus interface (WISHBONE) when _true_.
670 
|======
671 
 
672 
 
673 
:sectnums!:
674 
===== _MEM_EXT_TIMEOUT_
675 
 
676 
[cols="4,4,2"]
677 
[frame="all",grid="none"]
678 
|======
679 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
680 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
681 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
682 60 zero_gravi 
|======
683 
 
684 
 
685 62 zero_gravi 
:sectnums!:
686 
===== _MEM_EXT_PIPE_MODE_
687 
 
688 
[cols="4,4,2"]
689 
[frame="all",grid="none"]
690 
|======
691 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
692 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
693 
Use _pipelined_ Wishbone protocol when _true_.
694 62 zero_gravi 
|======
695 
 
696 
 
697 
:sectnums!:
698 
===== _MEM_EXT_BIG_ENDIAN_
699 
 
700 
[cols="4,4,2"]
701 
[frame="all",grid="none"]
702 
|======
703 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
704 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
705 62 zero_gravi 
|======
706 
 
707 
 
708 
:sectnums!:
709 
===== _MEM_EXT_ASYNC_RX_
710 
 
711 
[cols="4,4,2"]
712 
[frame="all",grid="none"]
713 
|======
714 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
715 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
716 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
717 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
718 62 zero_gravi 
|======
719 
 
720 
 
721 60 zero_gravi 
// ####################################################################################################################
722 
:sectnums:
723 61 zero_gravi 
==== Stream Link Interface
724 
 
725 
See section <<_stream_link_interface_slink>> for more information.
726 
 
727 
 
728 
:sectnums!:
729 
===== _SLINK_NUM_TX_
730 
 
731 
[cols="4,4,2"]
732 
[frame="all",grid="none"]
733 
|======
734 
| **SLINK_NUM_TX** | _natural_ | 0
735 
3+| Number of TX (send) links to implement. Valid values are 0..8.
736 
|======
737 
 
738 
 
739 
:sectnums!:
740 
===== _SLINK_NUM_RX_
741 
 
742 
[cols="4,4,2"]
743 
[frame="all",grid="none"]
744 
|======
745 
| **SLINK_NUM_RX** | _natural_ | 0
746 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
747 
|======
748 
 
749 
 
750 
:sectnums!:
751 
===== _SLINK_TX_FIFO_
752 
 
753 
[cols="4,4,2"]
754 
[frame="all",grid="none"]
755 
|======
756 
| **SLINK_TX_FIFO** | _natural_ | 1
757 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
758 
|======
759 
 
760 
 
761 
:sectnums!:
762 
===== _SLINK_RX_FIFO_
763 
 
764 
[cols="4,4,2"]
765 
[frame="all",grid="none"]
766 
|======
767 
| **SLINK_RX_FIFO** | _natural_ | 1
768 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
769 
|======
770 
 
771 
 
772 
// ####################################################################################################################
773 
:sectnums:
774 
==== External Interrupt Controller
775 
 
776 
See section <<_external_interrupt_controller_xirq>> for more information.
777 
 
778 
 
779 
:sectnums!:
780 
===== _XIRQ_NUM_CH_
781 
 
782 
[cols="4,4,2"]
783 
[frame="all",grid="none"]
784 
|======
785 
| **XIRQ_NUM_CH** | _natural_ | 0
786 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
787 
|======
788 
 
789 
 
790 
:sectnums!:
791 
===== _XIRQ_TRIGGER_TYPE_
792 
 
793 
[cols="4,4,2"]
794 
[frame="all",grid="none"]
795 
|======
796 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
797 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
798 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
799 61 zero_gravi 
|======
800 
 
801 
 
802 
:sectnums!:
803 
===== _XIRQ_TRIGGER_POLARITY_
804 
 
805 
[cols="4,4,2"]
806 
[frame="all",grid="none"]
807 
|======
808 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
809 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
810 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
811 61 zero_gravi 
|======
812 
 
813 
 
814 
// ####################################################################################################################
815 
:sectnums:
816 60 zero_gravi 
==== Processor Peripheral/IO Modules
817 
 
818 
See section <<_processor_internal_modules>> for more information.
819 
 
820 
 
821 
:sectnums!:
822 
===== _IO_GPIO_EN_
823 
 
824 
[cols="4,4,2"]
825 
[frame="all",grid="none"]
826 
|======
827 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
828 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
829 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
830 
|======
831 
 
832 
 
833 
:sectnums!:
834 
===== _IO_MTIME_EN_
835 
 
836 
[cols="4,4,2"]
837 
[frame="all",grid="none"]
838 
|======
839 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
840 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
841 
See section <<_machine_system_timer_mtime>> for more information.
842 
|======
843 
 
844 
 
845 
:sectnums!:
846 
===== _IO_UART0_EN_
847 
 
848 
[cols="4,4,2"]
849 
[frame="all",grid="none"]
850 
|======
851 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
852 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
853 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
854 
more information.
855 
|======
856 
 
857 
 
858 
:sectnums!:
859 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
860 
 
861 
[cols="4,4,2"]
862 
[frame="all",grid="none"]
863 
|======
864 
| **IO_UART0_RX_FIFO** | _natural_ | 1
865 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
866 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
867 
more information.
868 
|======
869 
 
870 
 
871 
:sectnums!:
872 
===== _IO_UART0_TX_FIFO_
873 
 
874 
[cols="4,4,2"]
875 
[frame="all",grid="none"]
876 
|======
877 
| **IO_UART0_TX_FIFO** | _natural_ | 1
878 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
879 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
880 
more information.
881 
|======
882 
 
883 
 
884 
:sectnums!:
885 60 zero_gravi 
===== _IO_UART1_EN_
886 
 
887 
[cols="4,4,2"]
888 
[frame="all",grid="none"]
889 
|======
890 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
891 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
892 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
893 
|======
894 
 
895 
 
896 
:sectnums!:
897 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
898 
 
899 
[cols="4,4,2"]
900 
[frame="all",grid="none"]
901 
|======
902 
| **IO_UART1_RX_FIFO** | _natural_ | 1
903 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
904 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
905 
more information.
906 
|======
907 
 
908 
 
909 
:sectnums!:
910 
===== _IO_UART1_TX_FIFO_
911 
 
912 
[cols="4,4,2"]
913 
[frame="all",grid="none"]
914 
|======
915 
| **IO_UART1_TX_FIFO** | _natural_ | 1
916 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
917 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
918 
more information.
919 
|======
920 
 
921 
 
922 
:sectnums!:
923 60 zero_gravi 
===== _IO_SPI_EN_
924 
 
925 
[cols="4,4,2"]
926 
[frame="all",grid="none"]
927 
|======
928 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
929 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
930 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
931 
|======
932 
 
933 
 
934 
:sectnums!:
935 
===== _IO_TWI_EN_
936 
 
937 
[cols="4,4,2"]
938 
[frame="all",grid="none"]
939 
|======
940 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
941 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
942 
See section <<_two_wire_serial_interface_controller_twi>> for
943 
more information.
944 
|======
945 
 
946 
 
947 
:sectnums!:
948 
===== _IO_PWM_NUM_CH_
949 
 
950 
[cols="4,4,2"]
951 
[frame="all",grid="none"]
952 
|======
953 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
954 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
955 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
956 
|======
957 
 
958 
 
959 
:sectnums!:
960 
===== _IO_WDT_EN_
961 
 
962 
[cols="4,4,2"]
963 
[frame="all",grid="none"]
964 
|======
965 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
966 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
967 
information.
968 
|======
969 
 
970 
 
971 
:sectnums!:
972 
===== _IO_TRNG_EN_
973 
 
974 
[cols="4,4,2"]
975 
[frame="all",grid="none"]
976 
|======
977 
| **IO_TRNG_EN** | _boolean_ | false
978 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
979 
|======
980 
 
981 
 
982 
:sectnums!:
983 
===== _IO_CFS_EN_
984 
 
985 
[cols="4,4,2"]
986 
[frame="all",grid="none"]
987 
|======
988 
| **IO_CFS_EN** | _boolean_ | false
989 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
990 
|======
991 
 
992 
 
993 
:sectnums!:
994 
===== _IO_CFS_CONFIG_
995 
 
996 
[cols="4,4,2"]
997 
[frame="all",grid="none"]
998 
|======
999 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
1000 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
1001 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
1002 
|======
1003 
 
1004 
 
1005 
:sectnums!:
1006 
===== _IO_CFS_IN_SIZE_
1007 
 
1008 
[cols="4,4,2"]
1009 
[frame="all",grid="none"]
1010 
|======
1011 
| **IO_CFS_IN_SIZE** | _positive_ | 32
1012 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
1013 
|======
1014 
 
1015 
 
1016 
:sectnums!:
1017 
===== _IO_CFS_OUT_SIZE_
1018 
 
1019 
[cols="4,4,2"]
1020 
[frame="all",grid="none"]
1021 
|======
1022 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
1023 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
1024 
|======
1025 
 
1026 
 
1027 
:sectnums!:
1028 
===== _IO_NEOLED_EN_
1029 
 
1030 
[cols="4,4,2"]
1031 
[frame="all",grid="none"]
1032 
|======
1033 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
1034 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
1035 
See section <<_smart_led_interface_neoled>> for more information.
1036 
|======
1037 
 
1038 
 
1039 62 zero_gravi 
:sectnums!:
1040 
===== _IO_NEOLED_TX_FIFO_
1041 
 
1042 
[cols="4,4,2"]
1043 
[frame="all",grid="none"]
1044 
|======
1045 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
1046 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
1047 
See section <<_smart_led_interface_neoled>> for more information.
1048 
|======
1049 
 
1050 
 
1051 67 zero_gravi 
:sectnums!:
1052 
===== _IO_GPTMR_EN_
1053 62 zero_gravi 
 
1054 67 zero_gravi 
[cols="4,4,2"]
1055 
[frame="all",grid="none"]
1056 
|======
1057 
| **IO_GPTMR_EN** | _boolean_ | false
1058 
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
1059 
See section <<_general_purpose_timer_gptmr>> for more information.
1060 
|======
1061 
 
1062 
 
1063 70 zero_gravi 
:sectnums!:
1064 
===== _IO_XIP_EN_
1065 67 zero_gravi 
 
1066 70 zero_gravi 
[cols="4,4,2"]
1067 
[frame="all",grid="none"]
1068 
|======
1069 
| **IO_XIP_EN** | _boolean_ | false
1070 
3+| Implement the execute in place module (XIP) when _true_.
1071 
See section <<_execute_in_place_module_xip>> for more information.
1072 
|======
1073 
 
1074 
 
1075 
 
1076 60 zero_gravi 
<<<
1077 
// ####################################################################################################################
1078 
:sectnums:
1079 
=== Processor Interrupts
1080 
 
1081 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
1082 60 zero_gravi 
 
1083 
 
1084 61 zero_gravi 
:sectnums:
1085 
==== RISC-V Standard Interrupts
1086 
 
1087 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1088 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1089 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1090 
<<_traps_exceptions_and_interrupts>> for more information.
1091 60 zero_gravi 
 
1092 61 zero_gravi 
[cols="<3,^2,<11"]
1093 
[options="header",grid="rows"]
1094 
|=======================
1095 
| Top signal | Width | Description
1096 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1097 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1098 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1099 
|=======================
1100 60 zero_gravi 
 
1101 64 zero_gravi 
.Trigger type
1102 62 zero_gravi 
[IMPORTANT]
1103 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1104 72 zero_gravi 
be explicitly cleared by setting the according <<_mip>> CSR bit.
1105 61 zero_gravi 
 
1106 
 
1107 
:sectnums:
1108 
==== Platform External Interrupts
1109 
 
1110 
[cols="<3,^2,<11"]
1111 
[options="header",grid="rows"]
1112 
|=======================
1113 
| Top signal | Width | Description
1114 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1115 
|=======================
1116 
 
1117 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1118 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1119 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1120 
 
1121 64 zero_gravi 
.Trigger type
1122 
[IMPORTANT]
1123 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1124 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1125 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1126 
_fast interrupt request_ (see below).
1127 61 zero_gravi 
 
1128 
 
1129 
:sectnums:
1130 
==== NEORV32-Specific Fast Interrupt Requests
1131 
 
1132 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1133 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1134 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1135 60 zero_gravi 
 
1136 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1137 
the according FIRQ priority; 0 = highest, 15 = lowest):
1138 60 zero_gravi 
 
1139 
.NEORV32 fast interrupt channel mapping
1140 
[cols="^1,<2,<7"]
1141 
[options="header",grid="rows"]
1142 
|=======================
1143 
| Channel | Source | Description
1144 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1145 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1146 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1147 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1148 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1149 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1150 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1151 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1152 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1153 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1154 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1155 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1156 67 zero_gravi 
| 12      | <<_general_purpose_timer_gptmr,GPTMR>> | General purpose timer interrupt
1157 
| 13:15   | - | _reserved_, will never fire
1158 60 zero_gravi 
|=======================
1159 
 
1160 64 zero_gravi 
.Trigger type
1161 
[IMPORTANT]
1162 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1163 72 zero_gravi 
be explicitly cleared by setting the according <<_mip>> CSR bit.
1164 60 zero_gravi 
 
1165 
 
1166 64 zero_gravi 
 
1167 60 zero_gravi 
<<<
1168 
// ####################################################################################################################
1169 
:sectnums:
1170 
=== Address Space
1171 
 
1172 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1173 
By default, this address space is divided into five main regions:
1174 60 zero_gravi 
 
1175 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1176 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1177 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1178 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1179 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1180 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1181 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1182 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1183 60 zero_gravi 
 
1184 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1185 
image::address_space.png[900]
1186 60 zero_gravi 
 
1187 72 zero_gravi 
.RAM Layout - Usage of the Data Address Space
1188 
[TIP]
1189 
The actual usage of the data address space by the software/executables (stack, heap, ...) is
1190 
illustrated in section <<_ram_layout>>.
1191 60 zero_gravi 
 
1192 72 zero_gravi 
 
1193 60 zero_gravi 
:sectnums:
1194 
==== CPU Data and Instruction Access
1195 
 
1196 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1197 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1198 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1199 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1200 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1201 
setup a modified von-Neumann architecture.
1202 
 
1203 
.Processor-internal bus architecture
1204 
image::neorv32_bus.png[1300]
1205 
 
1206 
[NOTE]
1207 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1208 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1209 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1210 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1211 
accesses.
1212 
 
1213 
[IMPORTANT]
1214 
Please note that all processor-internal components including the peripheral/IO devices can also be
1215 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1216 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1217 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1218 70 zero_gravi 
PMP system (see <<_machine_physical_memory_protection_csrs>>).
1219 60 zero_gravi 
 
1220 61 zero_gravi 
 
1221 60 zero_gravi 
:sectnums:
1222 61 zero_gravi 
==== Address Space Layout
1223 
 
1224 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1225 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1226 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1227 
`rtl/core/neorv32_package.vhd`:
1228 
 
1229 
[source,vhdl]
1230 
----
1231 
-- Architecture Configuration ----------------------------------------------------
1232 
-- ----------------------------------------------------------------------------------
1233 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1234 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1235 
----
1236 
 
1237 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1238 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1239 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1240 
are _aligned_ to a 4-byte boundary.
1241 
 
1242 
[NOTE]
1243 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1244 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1245 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1246 61 zero_gravi 
hardware sources.
1247 
 
1248 
 
1249 
:sectnums:
1250 60 zero_gravi 
==== Physical Memory Attributes
1251 
 
1252 61 zero_gravi 
The processor setup defines fixed attributes for the four processor-internal address space regions.
1253 
Accessing a memory region in a way that violates any of these attributes will raise an according
1254 
access exception..
1255 60 zero_gravi 
 
1256 65 zero_gravi 
* `r` - read access (from CPU data access interface, "loads")
1257 
* `w` - write access (from CPU data access interface, "stores")
1258 
* `x` - execute access (from CPU instruction fetch interface)
1259 
* `a` - atomic access (from CPU data access interface)
1260 
* `8` - byte (8-bit)-accessible (when writing)
1261 
* `16` - half-word (16-bit)-accessible (when writing)
1262 
* `32` - word (32-bit)-accessible (when writing)
1263 60 zero_gravi 
 
1264 61 zero_gravi 
[NOTE]
1265 65 zero_gravi 
Read accesses (loads and instruction fetches) can always access data in
1266 
word, half-word (for instruction fetch only if `C` extension is enabled)
1267 
and byte (not for instruction fetch) quantities (requiring an accordingly aligned address).
1268 60 zero_gravi 
 
1269 65 zero_gravi 
[TIP]
1270 
The following table shows the _default hardware-defined_ physical memory attributes of each main address space region.
1271 
Additional user-defined attributes (for example certain read/write/execute rights for specific address space regions) can be
1272 70 zero_gravi 
provided using the RISC-V <<_machine_physical_memory_protection_csrs>>.
1273 65 zero_gravi 
 
1274 60 zero_gravi 
[cols="^1,^2,^2,^3,^2"]
1275 
[options="header",grid="rows"]
1276 
|=======================
1277 65 zero_gravi 
| # | Region                | Base address | Size        | Attributes
1278 
| 5 | IO/peripheral devices | 0xfffffe00   | 512 bytes   | `r/w/a/32`
1279 
| 4 | On-chip debugger      | 0xfffff800   | 512 bytes   | `r/w/x/32`
1280 
| 3 | Bootloader ROM        | 0xffff0000   | up to 32kB  | `r/x/a`
1281 
| 2 | DMEM                  | 0x80000000   | up to "2GB" | `r/w/x/a/8/16/32`
1282 
| 1 | IMEM                  | 0x00000000   | up to 2GB   | `r/w/x/a/8/16/32`
1283 60 zero_gravi 
|=======================
1284 
 
1285 
 
1286 
:sectnums:
1287 61 zero_gravi 
==== Memory Configuration
1288 60 zero_gravi 
 
1289 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1290 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1291 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1292 
the internal ones. The figure below show some exemplary memory configurations.
1293 60 zero_gravi 
 
1294 61 zero_gravi 
.Exemplary memory configurations
1295 
image::neorv32_memory_configurations.png[800]
1296 60 zero_gravi 
 
1297 61 zero_gravi 
:sectnums!:
1298 
===== Internal Memories
1299 
 
1300 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1301 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1302 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1303 
 
1304 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1305 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1306 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1307 
implemented.
1308 
 
1309 61 zero_gravi 
[TIP]
1310 
The default processor setup uses only _internal_ memories.
1311 60 zero_gravi 
 
1312 61 zero_gravi 
[NOTE]
1313 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1314 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1315 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1316 
any access to the "dead address space" in between will raise an exception that can be caught
1317 
by the runtime environment.
1318 60 zero_gravi 
 
1319 61 zero_gravi 
:sectnums!:
1320 
===== External Memories
1321 
 
1322 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1323 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1324 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1325 
 
1326 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1327 
via the processor's bus interface to external components:
1328 
 
1329 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1330 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1331 70 zero_gravi 
* access to the bootloader ROM and beyond -> addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1332 60 zero_gravi 
 
1333 70 zero_gravi 
[NOTE]
1334 
If the Execute In Place module (XIP) is implemented accesses map to this module are not forwarded to the
1335 
external memory interface. See section <<_execute_in_place_module_xip>> for more information.
1336 
 
1337 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1338 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1339 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1340 
memory system.
1341 60 zero_gravi 
 
1342 61 zero_gravi 
[NOTE]
1343 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1344 
the internal peripheral address space will trigger a bus access fault exception.
1345 60 zero_gravi 
 
1346 
 
1347 61 zero_gravi 
:sectnums:
1348 
==== Boot Configuration
1349 
 
1350 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1351 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1352 
 
1353 
.NEORV32 boot configurations
1354 
image::neorv32_boot_configurations.png[800]
1355 
 
1356 
[NOTE]
1357 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1358 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1359 
 
1360 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1361 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1362 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1363 
 
1364 
[NOTE]
1365 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1366 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1367 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1368 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1369 
store it to external _data_ memory and transfers CPU control to that.
1370 
 
1371 
:sectnums!:
1372 
===== Indirect Boot
1373 
 
1374 68 zero_gravi 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This boot setup is enabled
1375 
by setting the <<_int_bootloader_en>> generic to _true_, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1376 61 zero_gravi 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1377 68 zero_gravi 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and copies it to
1378 
the beginning of the _instruction address space_ so the CPU can execute it.
1379 61 zero_gravi 
 
1380 68 zero_gravi 
Boot scenario **1a** uses the processor-internal IMEM
1381 61 zero_gravi 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1382 68 zero_gravi 
RAM so the bootloader can copy the actual executable to it.
1383 61 zero_gravi 
 
1384 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1385 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1386 68 zero_gravi 
copy the executable to the processor-external memory. Hence, the external memory has to be implemented as RAM.
1387 61 zero_gravi 
 
1388 
:sectnums!:
1389 
===== Direct Boot
1390 
 
1391 68 zero_gravi 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader since the <<_int_bootloader_en>>
1392 61 zero_gravi 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1393 68 zero_gravi 
directly begin executing code from the beginning of the instruction address space after reset. An application-specific
1394 
"pre-initialization" mechanism is required in order to provide an executable _in_ memory.
1395 61 zero_gravi 
 
1396 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1397 68 zero_gravi 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable during synthesis.
1398 61 zero_gravi 
 
1399 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1400 68 zero_gravi 
system designer is responsible for providing an initialized external memory that contains the actual application to be executed.
1401 
If the external is not already initialized after reset, a simple ROM containing a "polling loop" can be implemented that is
1402 
exited as soon as the application logic has finished initializing the memory with the acutal application code.
1403 61 zero_gravi 
 
1404 
 
1405 
 
1406 60 zero_gravi 
<<<
1407 
// ####################################################################################################################
1408 
:sectnums:
1409 
=== Processor-Internal Modules
1410 
 
1411 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1412 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1413 
system implements an internal reset generator and a global clock generator/divider.
1414 
 
1415 
**Internal Reset Generator**
1416 
 
1417 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1418 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1419 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1420 
modules to ensure a clean system reset state.
1421 
 
1422 
The hardware reset signal of the processor can either be
1423 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1424 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1425 
clock cycles.
1426 
 
1427 
**Internal Clock Divider**
1428 
 
1429 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1430 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1431 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1432 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1433 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1434 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1435 
power.
1436 
 
1437 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1438 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1439 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1440 
from the top entity's `clk_i` signal.
1441 
 
1442 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1443 
[grid="rows"]
1444 
|=======================
1445 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1446 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1447 
|=======================
1448 
 
1449 
**Peripheral / IO Devices**
1450 
 
1451 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1452 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1453 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1454 
library abstract the specific memory layout for the user.
1455 
 
1456 
[IMPORTANT]
1457 64 zero_gravi 
The base address of each component/module has to be aligned to the
1458 
total size of the module's occupied address space! The occupied address space
1459 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1460 
 
1461 
[IMPORTANT]
1462 70 zero_gravi 
When accessing an IO device that hast not been implemented (via the according generic), a
1463 60 zero_gravi 
load/store access fault exception is triggered.
1464 
 
1465 
[IMPORTANT]
1466 
The peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1467 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1468 
Processor-internal memories as well as modules connected to the external memory interface can still
1469 
be written with a byte-wide granularity.
1470 
 
1471 70 zero_gravi 
[NOTE]
1472 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1473 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1474 
application start-up code `crt0.S`.
1475 
 
1476 60 zero_gravi 
[TIP]
1477 
You should use the provided core software library to interact with the peripheral devices. This
1478 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1479 
register and register bit accesses.
1480 
 
1481 
[TIP]
1482 69 zero_gravi 
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
1483 
 
1484 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1485 
 
1486 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1487 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1488 66 zero_gravi 
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
1489 64 zero_gravi 
 
1490 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1491 
 
1492 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1493 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1494 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1495 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1496 
main processor core library include file `sw/lib/include/neorv32.h`.
1497 60 zero_gravi 
 
1498 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1499 
 
1500 
.Low-level hardware access example in C using the pre-defined `struct`
1501 
[source,c]
1502 
----
1503 
// Read from SYSINFO "CLK" register
1504 
uint32_t temp = NEORV32_SYSINFO.CLK;
1505 
----
1506 
 
1507 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1508 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1509 
available:
1510 
 
1511 
* `r/w` registers / bits can be read and written
1512 
* `r/-` registers / bits are read-only; any write access to them has no effect
1513 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1514 
 
1515 70 zero_gravi 
[NOTE]
1516 60 zero_gravi 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1517 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1518 
write zero to them to keep compatible with future extension.
1519 
 
1520 70 zero_gravi 
[NOTE]
1521 60 zero_gravi 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1522 
written. When reading data from a write-only register the result is undefined.
1523 
 
1524 
 
1525 
include::soc_imem.adoc[]
1526 
 
1527 
include::soc_dmem.adoc[]
1528 
 
1529 
include::soc_bootrom.adoc[]
1530 
 
1531 
include::soc_icache.adoc[]
1532 
 
1533 
include::soc_wishbone.adoc[]
1534 
 
1535 66 zero_gravi 
include::soc_buskeeper.adoc[]
1536 
 
1537 61 zero_gravi 
include::soc_slink.adoc[]
1538 
 
1539 60 zero_gravi 
include::soc_gpio.adoc[]
1540 
 
1541 
include::soc_wdt.adoc[]
1542 
 
1543 
include::soc_mtime.adoc[]
1544 
 
1545 
include::soc_uart.adoc[]
1546 
 
1547 
include::soc_spi.adoc[]
1548 
 
1549 
include::soc_twi.adoc[]
1550 
 
1551 
include::soc_pwm.adoc[]
1552 
 
1553 
include::soc_trng.adoc[]
1554 
 
1555 
include::soc_cfs.adoc[]
1556 
 
1557 
include::soc_neoled.adoc[]
1558 
 
1559 61 zero_gravi 
include::soc_xirq.adoc[]
1560 
 
1561 67 zero_gravi 
include::soc_gptmr.adoc[]
1562 
 
1563 70 zero_gravi 
include::soc_xip.adoc[]
1564 
 
1565 60 zero_gravi 
include::soc_sysinfo.adoc[]

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