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// ####################################################################################################################
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:sectnums:
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== NEORV32 Processor (SoC)
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6 
The NEORV32 Processor is based on the NEORV32 CPU. Together with common peripheral
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interfaces and embedded memories it provides a RISC-V-based full-scale microcontroller-like SoC platform.
8 
 
9 
image::neorv32_processor.png[align=center]
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11 
**Key Features**
12 
 
13 
* _optional_ processor-internal data and instruction memories (<<_data_memory_dmem,**DMEM**>>/<<_instruction_memory_imem,**IMEM**>>) + cache (<<_processor_internal_instruction_cache_icache,**iCACHE**>>)
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* _optional_ internal bootloader (<<_bootloader_rom_bootrom,**BOOTROM**>>) with UART console & SPI flash boot option
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* _optional_ machine system timer (<<_machine_system_timer_mtime,**MTIME**>>), RISC-V-compatible
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* _optional_ two independent universal asynchronous receivers and transmitters (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,**UART0**>>, <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,**UART1**>>) with optional hardware flow control (RTS/CTS) and optional RX/TX FIFOs
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* _optional_ 8/16/24/32-bit serial peripheral interface controller (<<_serial_peripheral_interface_controller_spi,**SPI**>>) with 8 dedicated CS lines
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* _optional_ two wire serial interface controller (<<_two_wire_serial_interface_controller_twi,**TWI**>>), compatible to the I²C standard
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* _optional_ general purpose parallel IO port (<<_general_purpose_input_and_output_port_gpio,**GPIO**>>), 64xOut, 64xIn
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* _optional_ 32-bit external bus interface, Wishbone b4 / AXI4-Lite compatible (<<_processor_external_memory_interface_wishbone_axi4_lite,**WISHBONE**>>)
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* _optional_ 32-bit stream link interface with up to 8 independent links, AXI4-Stream compatible (<<_stream_link_interface_slink,**SLINK**>>)
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* _optional_ watchdog timer (<<_watchdog_timer_wdt,**WDT**>>)
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* _optional_ PWM controller with up to 60 channels & 8-bit duty cycle resolution (<<_pulse_width_modulation_controller_pwm,**PWM**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ general purpose 32-bit timer (<<_general_purpose_timer_gptmr,**GPTMR**>>)
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* _optional_ execute in place module (<<_execute_in_place_module_xip,**XIP**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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34 
 
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Signals
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The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
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The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
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.Default Values of Ports
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[NOTE]
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All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
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For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
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the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
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since all control signals have defined level.
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.Configurable Amount of Channels
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[NOTE]
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Some peripherals allow to configure the number of channels to-be-implemented by a generic (for example the number
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of PWM or SLINK channels). The according input/output signals have a fixed sized regardless of the actually configured
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amount of channels. If less than the maximum number of channels is configured, only the LSB-aligned channels are used:
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in case of an _input port_ the remaining bits/channels are left unconnected; in case of an _output port_ the remaining
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bits/channels are hardwired to zero.
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[cols="<3,^2,^2,<11"]
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[options="header",grid="rows"]
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|=======================
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| Signal | Width | Dir. | Function
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4+^| **Global Control**
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| `clk_i` | 1 | in | global clock line, all registers triggering on rising edge
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| `rstn_i` | 1 | in | global reset, asynchronous, **low-active**
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4+^| **JTAG Access Port for <<_on_chip_debugger_ocd>>**
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| `jtag_trst_i` | 1 | in  | TAP reset, low-active (optional footnote:[Pull high if not used.])
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| `jtag_tck_i`  | 1 | in  | serial clock
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| `jtag_tdi_i`  | 1 | in  | serial data input
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| `jtag_tdo_o`  | 1 | out | serial data output footnote:[If the on-chip debugger is not implemented (_ON_CHIP_DEBUGGER_EN_ = false) `jtag_tdi_i` is directly forwarded to `jtag_tdo_o` to maintain the JTAG chain.]
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| `jtag_tms_i`  | 1 | in  | mode select
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4+^| **External Bus Interface (<<_processor_external_memory_interface_wishbone_axi4_lite,WISHBONE>>)**
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| `wb_tag_o` | 3  | out | tag (access type identifier)
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| `wb_adr_o` | 32 | out | destination address
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| `wb_dat_i` | 32 | in | write data
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| `wb_dat_o` | 32 | out | read data
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| `wb_we_o`  | 1  | out | write enable ('0' = read transfer)
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| `wb_sel_o` | 4  | out | byte enable
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| `wb_stb_o` | 1  | out | strobe
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| `wb_cyc_o` | 1  | out | valid cycle
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| `wb_lock_o`| 1  | out | exclusive access request
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| `wb_ack_i` | 1  | in | transfer acknowledge
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| `wb_err_i` | 1  | in | transfer error
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4+^| **Advanced Memory Control Signals**
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| `fence_o`  | 1 | out | indicates an executed _fence_ instruction
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| `fencei_o` | 1 | out | indicates an executed _fencei_ instruction
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4+^| **Execute In Place Interface (<<_execute_in_place_module_xip,**XIP**>>)**
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| `xip_csn_o` | 1 | out | chi select, low-active
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| `xip_clk_o` | 1 | out | serial clock
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| `xip_sdi_i` | 1 | in  | serial data input
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| `xip_sdo_o` | 1 | out | serial data output
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4+^| **Stream Link Interface (<<_stream_link_interface_slink,SLINK>>)**
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| `slink_tx_dat_o` | 8x32 | out | TX link _n_ data
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| `slink_tx_val_o` |    8 | out | TX link _n_ data valid
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| `slink_tx_rdy_i` |    8 | in  | TX link _n_ allowed to send
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| `slink_rx_dat_i` | 8x32 | in  | RX link _n_ data
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| `slink_rx_val_i` |    8 | in  | RX link _n_ data valid
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| `slink_rx_rdy_o` |    8 | out | RX link _n_ ready to receive
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4+^| **General Purpose Inputs & Outputs (<<_general_purpose_input_and_output_port_gpio,GPIO>>)**
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| `gpio_o` | 64 | out | general purpose parallel output
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| `gpio_i` | 64 | in | general purpose parallel input
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>>)**
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| `uart0_txd_o` | 1 | out | UART0 serial transmitter
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| `uart0_rxd_i` | 1 | in | UART0 serial receiver
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| `uart0_rts_o` | 1 | out | UART0 RX ready to receive new char
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| `uart0_cts_i` | 1 | in | UART0 TX allowed to start sending
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4+^| **Primary Universal Asynchronous Receiver/Transmitter (<<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>>)**
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| `uart1_txd_o` | 1 | out | UART1 serial transmitter
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| `uart1_rxd_i` | 1 | in | UART1 serial receiver
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| `uart1_rts_o` | 1 | out | UART1 RX ready to receive new char
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| `uart1_cts_i` | 1 | in | UART1 TX allowed to start sending
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4+^| **Serial Peripheral Interface Controller (<<_serial_peripheral_interface_controller_spi,SPI>>)**
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| `spi_sck_o` | 1 | out | SPI controller clock line
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| `spi_sdo_o` | 1 | out | SPI serial data output
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| `spi_sdi_i` | 1 | in | SPI serial data input
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| `spi_csn_o` | 8 | out | SPI dedicated chip select (low-active)
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4+^| **Two-Wire Interface Controller (<<_two_wire_serial_interface_controller_twi,TWI>>)**
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| `twi_sda_io` | 1 | inout | TWI serial data line
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| `twi_scl_io` | 1 | inout | TWI serial clock line
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4+^| **Pulse-Width Modulation Channels (<<_pulse_width_modulation_controller_pwm,PWM>>)**
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| `pwm_o` | 60 | out | pulse-width modulated channels
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4+^| **Custom Functions Subsystem (<<_custom_functions_subsystem_cfs,CFS>>)**
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| `cfs_in_i`  | 32 | in | custom CFS input signal conduit
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| `cfs_out_o` | 32 | out | custom CFS output signal conduit
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4+^| **Smart LED Interface - NeoPixel(TM) compatible (<<_smart_led_interface_neoled,NEOLED>>)**
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| `neoled_o` | 1 | out | asynchronous serial data output
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4+^| **System time (<<_machine_system_timer_mtime,MTIME>>)**
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| `mtime_i` | 64 | in  | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
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| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
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4+^| **External Interrupts (<<_processor_interrupts, XIRQ>>)**
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| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
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4+^| **RISC-V Machine-Level <<_processor_interrupts, CPU Interrupts>>**
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| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), high-active
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| `msw_irq_i`   | 1 | in | machine software interrupt (RISC-V), high-active
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| `mext_irq_i`  | 1 | in | machine external interrupt (RISC-V), high-active
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|=======================
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137 
 
138 
<<<
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// ####################################################################################################################
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:sectnums:
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=== Processor Top Entity - Generics
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143 
This is a list of all configuration generics of the NEORV32 processor top entity rtl/neorv32_top.vhd.
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The generic name is shown in orange, followed by the type in printed in black and concluded by the default
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value printed in light gray.
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147 
[TIP]
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The NEORV32 generics allow to configure the system according to your needs. The generics are
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used to control implementation of certain CPU extensions and peripheral modules and even allow to
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optimize the system for certain design goals like minimal area or maximum performance. +
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 +
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More information can be found in the user guides' section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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155 
[TIP]
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Privileged software can determine the actual CPU and processor configuration via the <<_misa>> and <<_mxisa>> CSRs (CPU)
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and the <<_system_configuration_information_memory_sysinfo, SYSINFO>> (processor) memory-mapped registers.
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[TIP]
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Run a quick simulation using the provided simulation/GHDL scripts (https://stnolting.github.io/neorv32/ug/#_hello_world)
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to verify the configuration of the processor generics is valid.
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[NOTE]
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If optional modules (like CPU extensions or peripheral devices) are *not enabled* the according circuitry
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**will not be synthesized at all**. Hence, the disabled modules do not increase area and power requirements
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and do not impact the timing.
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[NOTE]
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Not all configuration combinations are valid. The processor RTL code provides sanity checks to inform the user
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during synthesis/simulation if an invalid combination has been detected.
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**Generic Description**
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The description of each generic provides the following summary:
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.Generic description
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| _Generic name_ | _type_ | _default value_
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3+| _Description_
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|======
183 
 
184 
<<<
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// ####################################################################################################################
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:sectnums:
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==== General
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189 
See section <<_system_configuration_information_memory_sysinfo>> for more information.
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:sectnums!:
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===== _CLOCK_FREQUENCY_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CLOCK_FREQUENCY** | _natural_ | _none_
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3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz). This value can be retrieved by software
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from the <<_system_configuration_information_memory_sysinfo, SYSINFO>> module.
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|======
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:sectnums!:
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===== _INT_BOOTLOADER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **INT_BOOTLOADER_EN** | _boolean_ | false
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3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
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This will also change the processor's boot address from the beginning of the instruction memory address space (default =
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0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
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|======
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:sectnums!:
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===== _HW_THREAD_ID_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **HW_THREAD_ID** | _natural_ | 0
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3+| The hart ID of the CPU. Software can retrieve this value from the <<_mhartid>> CSR.
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Note that hart IDs must be unique within a system.
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|======
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:sectnums!:
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===== _ON_CHIP_DEBUGGER_EN_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **ON_CHIP_DEBUGGER_EN** | _boolean_ | false
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3+| Implement the on-chip debugger (OCD) and the CPU debug mode.
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See chapter <<_on_chip_debugger_ocd>> for more information.
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|======
238 
 
239 
 
240 
// ####################################################################################################################
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:sectnums:
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==== RISC-V CPU Extensions
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.Discovering ISA Extensions
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[TIP]
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See section <<_instruction_sets_and_extensions>> for more information. The configuration of the RISC-V _main_ ISA extensions
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(like `M`) can be determined via the <<_misa>> CSR. The configuration of ISA _sub-extensions_ (like `Zicsr`) and _tuning options_
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can be determined via the NEORV32-specific <<_mxisa>> CSR.
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250 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_A_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_A** | _boolean_ | false
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3+| Implement atomic memory access operations when _true_.
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See section <<_a_atomic_memory_access>>.
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|======
261 
 
262 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_B_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
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3+| Implement the `B` bit-manipulation sub-extension when _true_.
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See section <<_b_bit_manipulation_operations>> for more information.
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|======
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274 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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278 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_C** | _boolean_ | false
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3+| Implement compressed instructions (16-bit) when _true_. Compressed instructions can reduce program code
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size by approx. 30%. See section <<_c_compressed_instructions>>.
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|======
285 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_E_
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290 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
293 
| **CPU_EXTENSION_RISCV_E** | _boolean_ | false
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3+| Implement the embedded CPU extension (only implement the first 16 data registers) when _true_. This reduces embedded memory
295 
requirements for the register file. See section <<_e_embedded_cpu>> for more information. Note that this RISC-V extensions
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requires a different application binary interface (ABI).
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|======
298 
 
299 
 
300 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_M_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_M** | _boolean_ | false
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3+| Implement hardware accelerators for integer multiplication and division instructions when _true_.
308 
If this extensions is not enabled, multiplication and division operations (_not_ instructions) will be computed entirely in software.
309 
If only a hardware multiplier is required use the <<_cpu_extension_riscv_zmmul>> extension. Multiplication can also be mapped
310 
to DSP slices via the <<_fast_mul_en>> generic.
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See section <<_m_integer_multiplication_and_division>> for more information.
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|======
313 
 
314 
 
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:sectnums!:
316 
===== _CPU_EXTENSION_RISCV_U_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_U** | _boolean_ | false
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3+| Implement less-privileged user mode when _true_.
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See section <<_u_less_privileged_user_mode>> for more information.
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|======
325 
 
326 
 
327 
:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zfinx** | _boolean_ | false
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3+| Implement the 32-bit single-precision floating-point extension (using integer registers) when _true_.
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See section <<_zfinx_single_precision_floating_point_operations>> for more information.
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|======
337 
 
338 
 
339 
:sectnums!:
340 
===== _CPU_EXTENSION_RISCV_Zicsr_
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342 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
345 
| **CPU_EXTENSION_RISCV_Zicsr** | _boolean_ | true
346 
3+| Implement the control and status register (CSR) access instructions when true. Note: When this option is
347 
disabled, the complete privileged architecture / trap system will be excluded from synthesis. Hence, no interrupts, no exceptions and
348 
no machine information will be available.
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See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
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|======
351 
 
352 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicntr_
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356 
[cols="4,4,2"]
357 
[frame="all",grid="none"]
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|======
359 
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
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3+| Implement the basic CPU <<_machine_counter_and_timer_csrs>> (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
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See section <<_zicntr_cpu_base_counters>> for more information.
362 
|======
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:sectnums!:
366 
===== _CPU_EXTENSION_RISCV_Zihpm_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
371 
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
372 
3+| Implement hardware performance monitor CSRs when true.
373 
See section <<_zihpm_hardware_performance_monitors>> for more information.
374 
|======
375 
 
376 
 
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
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380 
[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
383 
| **CPU_EXTENSION_RISCV_Zifencei** | _boolean_ | false
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3+| Implement the instruction fetch synchronization instruction `fence.i`. For example, this option is required
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for self-modifying code (and/or for instruction cache and CPU prefetch buffer flushes).
386 
See section <<_zifencei_instruction_stream_synchronization>> for more information.
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|======
388 
 
389 
 
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:sectnums!:
391 
===== _CPU_EXTENSION_RISCV_Zmmul_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|======
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| **CPU_EXTENSION_RISCV_Zmmul** | _boolean_ | false
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3+| Implement integer multiplication-only instructions when _true_. This is a sub-extension of the `M` extension, which
398 
cannot be used together with the `M` extension. See section <<_zmmul_integer_multiplication>> for more information.
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|======
400 
 
401 
 
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:sectnums!:
403 
===== _CPU_EXTENSION_RISCV_Zxcfu_
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405 
[cols="4,4,2"]
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[frame="all",grid="none"]
407 
|======
408 
| **CPU_EXTENSION_RISCV_Zxcfu** | _boolean_ | false
409 
3+| NEORV32-specific "custom RISC-V" ISA extensions: Implement the <<_custom_functions_unit_cfu>> for user-defined
410 
custom instruction when _true_. See section <<_zxcfu_custom_instructions_extension_cfu>> for more information.
411 
|======
412 
 
413 
 
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// ####################################################################################################################
415 
:sectnums:
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==== Tuning Options
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These are generics to fine-tune certain ISA extensions and CPU features.
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See section <<_instruction_sets_and_extensions>> for more information.
420 
 
421 
 
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:sectnums!:
423 
===== _FAST_MUL_EN_
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425 
[cols="4,4,2"]
426 
[frame="all",grid="none"]
427 
|======
428 
| **FAST_MUL_EN** | _boolean_ | false
429 63 zero_gravi 
3+| When this generic is enabled, the multiplier of the `M` extension is implemented using DSPs blocks instead of an
430 
iterative bit-serial approach. Performance will be increased and LUT utilization will be reduced at the cost of DSP slice
431 
utilization. This generic is only relevant when a hardware multiplier CPU extension is
432 
enabled (<<_cpu_extension_riscv_m>> or <<_cpu_extension_riscv_zmmul>> is _true_). **Note that the multipliers of the
433 
<<_zfinx_single_precision_floating_point_operations>> extension are always mapped to DSP block (if available).**
434 60 zero_gravi 
|======
435 
 
436 
 
437 
:sectnums!:
438 
===== _FAST_SHIFT_EN_
439 
 
440 
[cols="4,4,2"]
441 
[frame="all",grid="none"]
442 
|======
443 
| **FAST_SHIFT_EN** | _boolean_ | false
444 63 zero_gravi 
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
445 
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
446 
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
447 
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
448 66 zero_gravi 
shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
449 60 zero_gravi 
|======
450 
 
451 
 
452 
:sectnums!:
453 
===== _CPU_CNT_WIDTH_
454 
 
455 
[cols="4,4,2"]
456 
[frame="all",grid="none"]
457 
|======
458 62 zero_gravi 
| **CPU_CNT_WIDTH** | _natural_ | 64
459 64 zero_gravi 
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
460 70 zero_gravi 
The maximum value is 64, the minimum value is 0. See section <<_machine_counter_and_timer_csrs>> for more information.
461 66 zero_gravi 
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
462 63 zero_gravi 
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
463 60 zero_gravi 
|======
464 
 
465 
 
466 62 zero_gravi 
:sectnums!:
467 
===== _CPU_IPB_ENTRIES_
468 
 
469 
[cols="4,4,2"]
470 
[frame="all",grid="none"]
471 
|======
472 
| **CPU_IPB_ENTRIES** | _natural_ | 2
473 
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
474 
The value has to be a power of two and has to be greater than zero.
475 63 zero_gravi 
Long linear sequences of code can benefit from an increased IPB size.
476 62 zero_gravi 
|======
477 
 
478 
 
479 60 zero_gravi 
// ####################################################################################################################
480 
:sectnums:
481 
==== Physical Memory Protection (PMP)
482 
 
483 
See section <<_pmp_physical_memory_protection>> for more information.
484 
 
485 
 
486 
:sectnums!:
487 
===== _PMP_NUM_REGIONS_
488 
 
489 
[cols="4,4,2"]
490 
[frame="all",grid="none"]
491 
|======
492 
| **PMP_NUM_REGIONS** | _natural_ | 0
493 73 zero_gravi 
3+| Total number of implemented protection regions (0..16). If this generics is zero no physical memory
494 72 zero_gravi 
protection logic will be implemented at all.
495 60 zero_gravi 
|======
496 
 
497 
 
498 
:sectnums!:
499 
===== _PMP_MIN_GRANULARITY_
500 
 
501 
[cols="4,4,2"]
502 
[frame="all",grid="none"]
503 
|======
504 73 zero_gravi 
| **PMP_MIN_GRANULARITY** | _natural_ | 4
505 
3+| Minimal region granularity in bytes. Has to be a power of two and has to be at least 4 bytes. A larger granularity
506 
will reduce hardware utilization and impact on critical path but will also reduce the minimal region size.
507 60 zero_gravi 
|======
508 
 
509 
 
510 
// ####################################################################################################################
511 
:sectnums:
512 
==== Hardware Performance Monitors (HPM)
513 
 
514 66 zero_gravi 
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
515 
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
516 60 zero_gravi 
 
517 
 
518 
:sectnums!:
519 
===== _HPM_NUM_CNTS_
520 
 
521 
[cols="4,4,2"]
522 
[frame="all",grid="none"]
523 
|======
524 
| **HPM_NUM_CNTS** | _natural_ | 0
525 63 zero_gravi 
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
526 66 zero_gravi 
hardware performance monitor logic will be implemented at all.
527 60 zero_gravi 
|======
528 
 
529 
 
530 
:sectnums!:
531 
===== _HPM_CNT_WIDTH_
532 
 
533 
[cols="4,4,2"]
534 
[frame="all",grid="none"]
535 
|======
536 
| **HPM_CNT_WIDTH** | _natural_ | 40
537 63 zero_gravi 
3+| This generic defines the total LSB-aligned size of each HPM counter (`size([m]hpmcounter*h)` +
538 
`size([m]hpmcounter*)`). The maximum value is 64, the minimal is 0. If the size is less than 64-bit, the
539 60 zero_gravi 
unused MSB-aligned counter bits are hardwired to zero.
540 
|======
541 
 
542 
 
543 
// ####################################################################################################################
544 
:sectnums:
545 
==== Internal Instruction Memory
546 
 
547 
See sections <<_address_space>> and <<_instruction_memory_imem>> for more information.
548 
 
549 
 
550 
:sectnums!:
551 
===== _MEM_INT_IMEM_EN_
552 
 
553 
[cols="4,4,2"]
554 
[frame="all",grid="none"]
555 
|======
556 62 zero_gravi 
| **MEM_INT_IMEM_EN** | _boolean_ | false
557 60 zero_gravi 
3+| Implement processor internal instruction memory (IMEM) when _true_.
558 
|======
559 
 
560 
 
561 
:sectnums!:
562 
===== _MEM_INT_IMEM_SIZE_
563 
 
564 
[cols="4,4,2"]
565 
[frame="all",grid="none"]
566 
|======
567 
| **MEM_INT_IMEM_SIZE** | _natural_ | 16*1024
568 63 zero_gravi 
3+| Size in bytes of the processor internal instruction memory (IMEM). Has no effect when <<_mem_int_imem_en>> is _false_.
569 60 zero_gravi 
|======
570 
 
571 
 
572 
// ####################################################################################################################
573 
:sectnums:
574 
==== Internal Data Memory
575 
 
576 
See sections <<_address_space>> and <<_data_memory_dmem>> for more information.
577 
 
578 
 
579 
:sectnums!:
580 
===== _MEM_INT_DMEM_EN_
581 
 
582 
[cols="4,4,2"]
583 
[frame="all",grid="none"]
584 
|======
585 62 zero_gravi 
| **MEM_INT_DMEM_EN** | _boolean_ | false
586 60 zero_gravi 
3+| Implement processor internal data memory (DMEM) when _true_.
587 
|======
588 
 
589 
 
590 
:sectnums!:
591 
===== _MEM_INT_DMEM_SIZE_
592 
 
593 
[cols="4,4,2"]
594 
[frame="all",grid="none"]
595 
|======
596 
| **MEM_INT_DMEM_SIZE** | _natural_ | 8*1024
597 63 zero_gravi 
3+| Size in bytes of the processor-internal data memory (DMEM). Has no effect when <<_mem_int_dmem_en>> is _false_.
598 60 zero_gravi 
|======
599 
 
600 
 
601 
// ####################################################################################################################
602 
:sectnums:
603 
==== Internal Cache Memory
604 
 
605 
See section <<_processor_internal_instruction_cache_icache>> for more information.
606 
 
607 
 
608 
:sectnums!:
609 
===== _ICACHE_EN_
610 
 
611 
[cols="4,4,2"]
612 
[frame="all",grid="none"]
613 
|======
614 
| **ICACHE_EN** | _boolean_ | false
615 63 zero_gravi 
3+| Implement processor internal instruction cache when _true_. Note: if the setup only uses processor-internal data
616 
and instruction memories there is not point of implementing the i-cache.
617 60 zero_gravi 
|======
618 
 
619 
 
620 
:sectnums!:
621 70 zero_gravi 
===== _ICACHE_NUM_BLOCKS_
622 60 zero_gravi 
 
623 
[cols="4,4,2"]
624 
[frame="all",grid="none"]
625 
|======
626 
| **ICACHE_NUM_BLOCKS** | _natural_ | 4
627 
3+| Number of blocks (cache "pages" or "lines") in the instruction cache. Has to be a power of two. Has no
628 70 zero_gravi 
effect when <<_icache_en>> is false.
629 60 zero_gravi 
|======
630 
 
631 
 
632 
:sectnums!:
633 
===== _ICACHE_BLOCK_SIZE_
634 
 
635 
[cols="4,4,2"]
636 
[frame="all",grid="none"]
637 
|======
638 
| **ICACHE_BLOCK_SIZE** | _natural_ | 64
639 
3+| Size in bytes of each block in the instruction cache. Has to be a power of two. Has no effect when
640 70 zero_gravi 
<<_icache_en>> is _false_.
641 60 zero_gravi 
|======
642 
 
643 
 
644 
:sectnums!:
645 
===== _ICACHE_ASSOCIATIVITY_
646 
 
647 
[cols="4,4,2"]
648 
[frame="all",grid="none"]
649 
|======
650 
| **ICACHE_ASSOCIATIVITY** | _natural_ | 1
651 
3+| Associativity (= number of sets) of the instruction cache. Has to be a power of two. Allowed configurations:
652 70 zero_gravi 
`1` = 1 set, direct mapped; `2` = 2-way set-associative. Has no effect when <<_icache_en>> is _false_.
653 60 zero_gravi 
|======
654 
 
655 
 
656 
// ####################################################################################################################
657 
:sectnums:
658 
==== External Memory Interface
659 
 
660 
See sections <<_address_space>> and <<_processor_external_memory_interface_wishbone_axi4_lite>> for more information.
661 
 
662 
 
663 
:sectnums!:
664 
===== _MEM_EXT_EN_
665 
 
666 
[cols="4,4,2"]
667 
[frame="all",grid="none"]
668 
|======
669 
| **MEM_EXT_EN** | _boolean_ | false
670 
3+| Implement external bus interface (WISHBONE) when _true_.
671 
|======
672 
 
673 
 
674 
:sectnums!:
675 
===== _MEM_EXT_TIMEOUT_
676 
 
677 
[cols="4,4,2"]
678 
[frame="all",grid="none"]
679 
|======
680 
| **MEM_EXT_TIMEOUT** | _natural_ | 255
681 63 zero_gravi 
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
682 
If set to zero, there will be no auto-timeout and no bus fault exception (might permanently stall system!).
683 60 zero_gravi 
|======
684 
 
685 
 
686 62 zero_gravi 
:sectnums!:
687 
===== _MEM_EXT_PIPE_MODE_
688 
 
689 
[cols="4,4,2"]
690 
[frame="all",grid="none"]
691 
|======
692 
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
693 63 zero_gravi 
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_.
694 
Use _pipelined_ Wishbone protocol when _true_.
695 62 zero_gravi 
|======
696 
 
697 
 
698 
:sectnums!:
699 
===== _MEM_EXT_BIG_ENDIAN_
700 
 
701 
[cols="4,4,2"]
702 
[frame="all",grid="none"]
703 
|======
704 
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
705 63 zero_gravi 
3+| Use BIG endian interface for external bus when _true_. Use little endian interface when _false_.
706 62 zero_gravi 
|======
707 
 
708 
 
709 
:sectnums!:
710 
===== _MEM_EXT_ASYNC_RX_
711 
 
712 
[cols="4,4,2"]
713 
[frame="all",grid="none"]
714 
|======
715 
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
716 
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
717 
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
718 63 zero_gravi 
implemented reducing access latency by one cycle but eventually increasing the critical path.
719 62 zero_gravi 
|======
720 
 
721 
 
722 60 zero_gravi 
// ####################################################################################################################
723 
:sectnums:
724 61 zero_gravi 
==== Stream Link Interface
725 
 
726 
See section <<_stream_link_interface_slink>> for more information.
727 
 
728 
 
729 
:sectnums!:
730 
===== _SLINK_NUM_TX_
731 
 
732 
[cols="4,4,2"]
733 
[frame="all",grid="none"]
734 
|======
735 
| **SLINK_NUM_TX** | _natural_ | 0
736 
3+| Number of TX (send) links to implement. Valid values are 0..8.
737 
|======
738 
 
739 
 
740 
:sectnums!:
741 
===== _SLINK_NUM_RX_
742 
 
743 
[cols="4,4,2"]
744 
[frame="all",grid="none"]
745 
|======
746 
| **SLINK_NUM_RX** | _natural_ | 0
747 
3+| Number of RX (receive) links to implement. Valid values are 0..8.
748 
|======
749 
 
750 
 
751 
:sectnums!:
752 
===== _SLINK_TX_FIFO_
753 
 
754 
[cols="4,4,2"]
755 
[frame="all",grid="none"]
756 
|======
757 
| **SLINK_TX_FIFO** | _natural_ | 1
758 
3+| Internal FIFO depth for _all_ implemented TX links. Valid values are 1..32k and have to be a power of two.
759 
|======
760 
 
761 
 
762 
:sectnums!:
763 
===== _SLINK_RX_FIFO_
764 
 
765 
[cols="4,4,2"]
766 
[frame="all",grid="none"]
767 
|======
768 
| **SLINK_RX_FIFO** | _natural_ | 1
769 
3+| Internal FIFO depth for _all_ implemented RX links. Valid values are 1..32k and have to be a power of two.
770 
|======
771 
 
772 
 
773 
// ####################################################################################################################
774 
:sectnums:
775 
==== External Interrupt Controller
776 
 
777 
See section <<_external_interrupt_controller_xirq>> for more information.
778 
 
779 
 
780 
:sectnums!:
781 
===== _XIRQ_NUM_CH_
782 
 
783 
[cols="4,4,2"]
784 
[frame="all",grid="none"]
785 
|======
786 
| **XIRQ_NUM_CH** | _natural_ | 0
787 
3+| Number of external interrupt channels o implement. Valid values are 0..32.
788 
|======
789 
 
790 
 
791 
:sectnums!:
792 
===== _XIRQ_TRIGGER_TYPE_
793 
 
794 
[cols="4,4,2"]
795 
[frame="all",grid="none"]
796 
|======
797 
| **XIRQ_TRIGGER_TYPE** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
798 
3+| Interrupt trigger type configuration (one bit for each IRQ channel): `0` = level-triggered, '1' = edge triggered.
799 63 zero_gravi 
<<_xirq_trigger_polarity>> generic is used to specify the actual level (high/low) or edge (falling/rising).
800 61 zero_gravi 
|======
801 
 
802 
 
803 
:sectnums!:
804 
===== _XIRQ_TRIGGER_POLARITY_
805 
 
806 
[cols="4,4,2"]
807 
[frame="all",grid="none"]
808 
|======
809 
| **XIRQ_TRIGGER_POLARITY** | _std_ulogic_vector(31 downto 0)_ | 0xFFFFFFFF
810 
3+| Interrupt trigger polarity configuration (one bit for each IRQ channel): `0` = low-level/falling-edge,
811 63 zero_gravi 
'1' = high-level/rising-edge. <<_xirq_trigger_type>> generic is used to specify the actual type (level or edge).
812 61 zero_gravi 
|======
813 
 
814 
 
815 
// ####################################################################################################################
816 
:sectnums:
817 60 zero_gravi 
==== Processor Peripheral/IO Modules
818 
 
819 
See section <<_processor_internal_modules>> for more information.
820 
 
821 
 
822 
:sectnums!:
823 
===== _IO_GPIO_EN_
824 
 
825 
[cols="4,4,2"]
826 
[frame="all",grid="none"]
827 
|======
828 62 zero_gravi 
| **IO_GPIO_EN** | _boolean_ | false
829 60 zero_gravi 
3+| Implement general purpose input/output port unit (GPIO) when _true_.
830 
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
831 
|======
832 
 
833 
 
834 
:sectnums!:
835 
===== _IO_MTIME_EN_
836 
 
837 
[cols="4,4,2"]
838 
[frame="all",grid="none"]
839 
|======
840 62 zero_gravi 
| **IO_MTIME_EN** | _boolean_ | false
841 60 zero_gravi 
3+| Implement machine system timer (MTIME) when _true_.
842 
See section <<_machine_system_timer_mtime>> for more information.
843 
|======
844 
 
845 
 
846 
:sectnums!:
847 
===== _IO_UART0_EN_
848 
 
849 
[cols="4,4,2"]
850 
[frame="all",grid="none"]
851 
|======
852 62 zero_gravi 
| **IO_UART0_EN** | _boolean_ | false
853 60 zero_gravi 
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
854 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
855 
more information.
856 
|======
857 
 
858 
 
859 
:sectnums!:
860 65 zero_gravi 
===== _IO_UART0_RX_FIFO_
861 
 
862 
[cols="4,4,2"]
863 
[frame="all",grid="none"]
864 
|======
865 
| **IO_UART0_RX_FIFO** | _natural_ | 1
866 
3+| UART0 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
867 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
868 
more information.
869 
|======
870 
 
871 
 
872 
:sectnums!:
873 
===== _IO_UART0_TX_FIFO_
874 
 
875 
[cols="4,4,2"]
876 
[frame="all",grid="none"]
877 
|======
878 
| **IO_UART0_TX_FIFO** | _natural_ | 1
879 
3+| UART0 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
880 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
881 
more information.
882 
|======
883 
 
884 
 
885 
:sectnums!:
886 60 zero_gravi 
===== _IO_UART1_EN_
887 
 
888 
[cols="4,4,2"]
889 
[frame="all",grid="none"]
890 
|======
891 62 zero_gravi 
| **IO_UART1_EN** | _boolean_ | false
892 61 zero_gravi 
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
893 60 zero_gravi 
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
894 
|======
895 
 
896 
 
897 
:sectnums!:
898 65 zero_gravi 
===== _IO_UART1_RX_FIFO_
899 
 
900 
[cols="4,4,2"]
901 
[frame="all",grid="none"]
902 
|======
903 
| **IO_UART1_RX_FIFO** | _natural_ | 1
904 
3+| UART1 receiver FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
905 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
906 
more information.
907 
|======
908 
 
909 
 
910 
:sectnums!:
911 
===== _IO_UART1_TX_FIFO_
912 
 
913 
[cols="4,4,2"]
914 
[frame="all",grid="none"]
915 
|======
916 
| **IO_UART1_TX_FIFO** | _natural_ | 1
917 
3+| UART1 transmitter FIFO depth, has to be a power of two, minimum value is 1 (implementing simple double-buffering).
918 
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
919 
more information.
920 
|======
921 
 
922 
 
923 
:sectnums!:
924 60 zero_gravi 
===== _IO_SPI_EN_
925 
 
926 
[cols="4,4,2"]
927 
[frame="all",grid="none"]
928 
|======
929 62 zero_gravi 
| **IO_SPI_EN** | _boolean_ | false
930 60 zero_gravi 
3+| Implement serial peripheral interface controller (SPI) when _true_.
931 
See section <<_serial_peripheral_interface_controller_spi>> for more information.
932 
|======
933 
 
934 
 
935 
:sectnums!:
936 
===== _IO_TWI_EN_
937 
 
938 
[cols="4,4,2"]
939 
[frame="all",grid="none"]
940 
|======
941 62 zero_gravi 
| **IO_TWI_EN** | _boolean_ | false
942 60 zero_gravi 
3+| Implement two-wire interface controller (TWI) when _true_.
943 
See section <<_two_wire_serial_interface_controller_twi>> for
944 
more information.
945 
|======
946 
 
947 
 
948 
:sectnums!:
949 
===== _IO_PWM_NUM_CH_
950 
 
951 
[cols="4,4,2"]
952 
[frame="all",grid="none"]
953 
|======
954 62 zero_gravi 
| **IO_PWM_NUM_CH** | _natural_ | 0
955 60 zero_gravi 
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
956 
See section <<_pulse_width_modulation_controller_pwm>> for more information.
957 
|======
958 
 
959 
 
960 
:sectnums!:
961 
===== _IO_WDT_EN_
962 
 
963 
[cols="4,4,2"]
964 
[frame="all",grid="none"]
965 
|======
966 62 zero_gravi 
| **IO_WDT_EN** | _boolean_ | false
967 60 zero_gravi 
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
968 
information.
969 
|======
970 
 
971 
 
972 
:sectnums!:
973 
===== _IO_TRNG_EN_
974 
 
975 
[cols="4,4,2"]
976 
[frame="all",grid="none"]
977 
|======
978 
| **IO_TRNG_EN** | _boolean_ | false
979 
3+| Implement true-random number generator (TRNG) when _true_. See section <<_true_random_number_generator_trng>> for more information.
980 
|======
981 
 
982 
 
983 
:sectnums!:
984 
===== _IO_CFS_EN_
985 
 
986 
[cols="4,4,2"]
987 
[frame="all",grid="none"]
988 
|======
989 
| **IO_CFS_EN** | _boolean_ | false
990 
3+| Implement custom functions subsystem (CFS) when _true_. See section <<_custom_functions_subsystem_cfs>> for more information.
991 
|======
992 
 
993 
 
994 
:sectnums!:
995 
===== _IO_CFS_CONFIG_
996 
 
997 
[cols="4,4,2"]
998 
[frame="all",grid="none"]
999 
|======
1000 
| **IO_CFS_CONFIG** | _std_ulogic_vector(31 downto 0)_ | 0x"00000000"
1001 
3+| This is a "conduit" generic that can be used to pass user-defined CFS implementation flags to the custom
1002 
functions subsystem entity. See section <<_custom_functions_subsystem_cfs>> for more information.
1003 
|======
1004 
 
1005 
 
1006 
:sectnums!:
1007 
===== _IO_CFS_IN_SIZE_
1008 
 
1009 
[cols="4,4,2"]
1010 
[frame="all",grid="none"]
1011 
|======
1012 
| **IO_CFS_IN_SIZE** | _positive_ | 32
1013 
3+| Defines the size of the CFS input signal conduit (`cfs_in_i`). See section <<_custom_functions_subsystem_cfs>> for more information.
1014 
|======
1015 
 
1016 
 
1017 
:sectnums!:
1018 
===== _IO_CFS_OUT_SIZE_
1019 
 
1020 
[cols="4,4,2"]
1021 
[frame="all",grid="none"]
1022 
|======
1023 
| **IO_CFS_OUT_SIZE** | _positive_ | 32
1024 
3+| Defines the size of the CFS output signal conduit (`cfs_out_o`). See section <<_custom_functions_subsystem_cfs>> for more information.
1025 
|======
1026 
 
1027 
 
1028 
:sectnums!:
1029 
===== _IO_NEOLED_EN_
1030 
 
1031 
[cols="4,4,2"]
1032 
[frame="all",grid="none"]
1033 
|======
1034 62 zero_gravi 
| **IO_NEOLED_EN** | _boolean_ | false
1035 60 zero_gravi 
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
1036 
See section <<_smart_led_interface_neoled>> for more information.
1037 
|======
1038 
 
1039 
 
1040 62 zero_gravi 
:sectnums!:
1041 
===== _IO_NEOLED_TX_FIFO_
1042 
 
1043 
[cols="4,4,2"]
1044 
[frame="all",grid="none"]
1045 
|======
1046 
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
1047 
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
1048 
See section <<_smart_led_interface_neoled>> for more information.
1049 
|======
1050 
 
1051 
 
1052 67 zero_gravi 
:sectnums!:
1053 
===== _IO_GPTMR_EN_
1054 62 zero_gravi 
 
1055 67 zero_gravi 
[cols="4,4,2"]
1056 
[frame="all",grid="none"]
1057 
|======
1058 
| **IO_GPTMR_EN** | _boolean_ | false
1059 
3+| Implement general purpose 32-bit timer (GPTMR) when _true_.
1060 
See section <<_general_purpose_timer_gptmr>> for more information.
1061 
|======
1062 
 
1063 
 
1064 70 zero_gravi 
:sectnums!:
1065 
===== _IO_XIP_EN_
1066 67 zero_gravi 
 
1067 70 zero_gravi 
[cols="4,4,2"]
1068 
[frame="all",grid="none"]
1069 
|======
1070 
| **IO_XIP_EN** | _boolean_ | false
1071 
3+| Implement the execute in place module (XIP) when _true_.
1072 
See section <<_execute_in_place_module_xip>> for more information.
1073 
|======
1074 
 
1075 
 
1076 
 
1077 60 zero_gravi 
<<<
1078 
// ####################################################################################################################
1079 
:sectnums:
1080 
=== Processor Interrupts
1081 
 
1082 61 zero_gravi 
The NEORV32 Processor provides several interrupt request signals (IRQs) for custom platform use.
1083 60 zero_gravi 
 
1084 
 
1085 61 zero_gravi 
:sectnums:
1086 
==== RISC-V Standard Interrupts
1087 
 
1088 62 zero_gravi 
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
1089 61 zero_gravi 
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
1090 
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
1091 
<<_traps_exceptions_and_interrupts>> for more information.
1092 60 zero_gravi 
 
1093 61 zero_gravi 
[cols="<3,^2,<11"]
1094 
[options="header",grid="rows"]
1095 
|=======================
1096 
| Top signal | Width | Description
1097 
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
1098 
| `msw_irq_i`   | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
1099 
| `mext_irq_i`  | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
1100 
|=======================
1101 60 zero_gravi 
 
1102 64 zero_gravi 
.Trigger type
1103 62 zero_gravi 
[IMPORTANT]
1104 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1105 73 zero_gravi 
be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
1106 61 zero_gravi 
 
1107 
 
1108 
:sectnums:
1109 
==== Platform External Interrupts
1110 
 
1111 
[cols="<3,^2,<11"]
1112 
[options="header",grid="rows"]
1113 
|=======================
1114 
| Top signal | Width | Description
1115 
| `xirq_i` | up to 32 | External platform interrupts (user-defined).
1116 
|=======================
1117 
 
1118 
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
1119 
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
1120 
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
1121 
 
1122 64 zero_gravi 
.Trigger type
1123 
[IMPORTANT]
1124 62 zero_gravi 
The trigger for these interrupt can be defined via generics. See section
1125 64 zero_gravi 
<<_external_interrupt_controller_xirq>> for more information. Depending on the trigger type, users can
1126 65 zero_gravi 
implement custom acknowledge mechanisms. All _external interrupts_ are mapped to a single processor-internal
1127 
_fast interrupt request_ (see below).
1128 61 zero_gravi 
 
1129 
 
1130 
:sectnums:
1131 
==== NEORV32-Specific Fast Interrupt Requests
1132 
 
1133 60 zero_gravi 
As part of the custom/NEORV32-specific CPU extensions, the CPU features 16 fast interrupt request signals
1134 65 zero_gravi 
(`FIRQ0` - `FIRQ15`). These are reserved for _processor-internal_ modules only (for example for the communication
1135 61 zero_gravi 
interfaces to signal "available incoming data" or "ready to send new data").
1136 60 zero_gravi 
 
1137 61 zero_gravi 
The mapping of the 16 FIRQ channels is shown in the following table (the channel number also corresponds to
1138 
the according FIRQ priority; 0 = highest, 15 = lowest):
1139 60 zero_gravi 
 
1140 
.NEORV32 fast interrupt channel mapping
1141 
[cols="^1,<2,<7"]
1142 
[options="header",grid="rows"]
1143 
|=======================
1144 
| Channel | Source | Description
1145 61 zero_gravi 
| 0       | <<_watchdog_timer_wdt,WDT>> | watchdog timeout interrupt
1146 
| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
1147 
| 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 data received interrupt (RX complete)
1148 
| 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 sending done interrupt (TX complete)
1149 
| 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 data received interrupt (RX complete)
1150 
| 5       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 sending done interrupt (TX complete)
1151 
| 6       | <<_serial_peripheral_interface_controller_spi,SPI>> | SPI transmission done interrupt
1152 
| 7       | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
1153 
| 8       | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
1154 65 zero_gravi 
| 9       | <<_smart_led_interface_neoled,NEOLED>> | NEOLED TX buffer interrupt
1155 
| 10      | <<_stream_link_interface_slink,SLINK>> | RX data buffer interrupt
1156 
| 11      | <<_stream_link_interface_slink,SLINK>> | TX data buffer interrupt
1157 67 zero_gravi 
| 12      | <<_general_purpose_timer_gptmr,GPTMR>> | General purpose timer interrupt
1158 
| 13:15   | - | _reserved_, will never fire
1159 60 zero_gravi 
|=======================
1160 
 
1161 64 zero_gravi 
.Trigger type
1162 
[IMPORTANT]
1163 69 zero_gravi 
The fast interrupt request channels become pending after being triggering by **a rising edge**. A pending FIRQ has to
1164 73 zero_gravi 
be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
1165 60 zero_gravi 
 
1166 
 
1167 64 zero_gravi 
 
1168 60 zero_gravi 
<<<
1169 
// ####################################################################################################################
1170 
:sectnums:
1171 
=== Address Space
1172 
 
1173 65 zero_gravi 
The NEORV32 Processor provides a 32-bit / 4GB (physical) address space
1174 
By default, this address space is divided into five main regions:
1175 60 zero_gravi 
 
1176 65 zero_gravi 
1. **Instruction address space** - memory address space for instructions (=code) and constants.
1177 
A configurable section of this address space is used by the internal/external _instruction memory_ (<<_mem_int_imem_size>> for the internal IMEM).
1178 
2. **Data address space** - memory address space for application runtime data (heap, stack, etc.).
1179 
A configurable section of this address space is used by the internal/external _data memory_ (<<_mem_int_dmem_size>> for the internal DMEM).
1180 
3. **Bootloader address space**. A _fixed_ section of this address space is used by the
1181 61 zero_gravi 
internal _bootloader memory_ (BOOTLDROM).
1182 65 zero_gravi 
4. **On-Chip Debugger address space**. This _fixed_ section is entirely used by the processor's <<_on_chip_debugger_ocd>>.
1183 
5. **IO/peripheral address space**. Also a _fixed_ section used for the processor-internal memory-mapped IO/peripheral devices (e.g., UART).
1184 60 zero_gravi 
 
1185 61 zero_gravi 
.NEORV32 processor - address space (default configuration)
1186 
image::address_space.png[900]
1187 60 zero_gravi 
 
1188 72 zero_gravi 
.RAM Layout - Usage of the Data Address Space
1189 
[TIP]
1190 
The actual usage of the data address space by the software/executables (stack, heap, ...) is
1191 
illustrated in section <<_ram_layout>>.
1192 60 zero_gravi 
 
1193 72 zero_gravi 
 
1194 60 zero_gravi 
:sectnums:
1195 
==== CPU Data and Instruction Access
1196 
 
1197 
The CPU can access all of the 4GB address space from the instruction fetch interface (**I**) and also from the
1198 
data access interface (**D**). These two CPU interfaces are multiplexed by a simple bus switch
1199 
(`rtl/core/neorv32_busswitch.vhd`) into a _single_ processor-internal bus. All processor-internal
1200 
memories, peripherals and also the external memory interface are connected to this bus. Hence, both CPU
1201 
interfaces (instruction fetch & data access) have access to the same (**identical**) address space making the
1202 
setup a modified von-Neumann architecture.
1203 
 
1204 
.Processor-internal bus architecture
1205 
image::neorv32_bus.png[1300]
1206 
 
1207 
[NOTE]
1208 
The internal processor bus might appear as bottleneck. In order to reduce traffic jam on this bus
1209 
(when instruction fetch and data interface access the bus at the same time) the instruction fetch of
1210 
the CPU is equipped with a prefetch buffer. Instruction fetches can be further buffered using the i-cache.
1211 
Furthermore, data accesses (loads and stores) have higher priority than instruction fetch
1212 
accesses.
1213 
 
1214 
[IMPORTANT]
1215 
Please note that all processor-internal components including the peripheral/IO devices can also be
1216 
accessed from programs running in less-privileged user mode. For example, if the system relies on
1217 
a periodic interrupt from the _MTIME_ timer unit, user-level programs could alter the _MTIME_
1218 
configuration corrupting this interrupt. This kind of security issues can be compensated using the
1219 70 zero_gravi 
PMP system (see <<_machine_physical_memory_protection_csrs>>).
1220 60 zero_gravi 
 
1221 61 zero_gravi 
 
1222 60 zero_gravi 
:sectnums:
1223 61 zero_gravi 
==== Address Space Layout
1224 
 
1225 
The general address space layout consists of two main configuration constants: `ispace_base_c` defining
1226 
the base address of the _instruction memory address space_ and `dspace_base_c` defining the base address of
1227 
the _data memory address space_. Both constants are defined in the NEORV32 VHDL package file
1228 
`rtl/core/neorv32_package.vhd`:
1229 
 
1230 
[source,vhdl]
1231 
----
1232 
-- Architecture Configuration ----------------------------------------------------
1233 
-- ----------------------------------------------------------------------------------
1234 
constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000";
1235 
constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000";
1236 
----
1237 
 
1238 
The default configuration assumes the _instruction memory address space_ starting at address _0x00000000_
1239 
and the _data memory address space_ starting at _0x80000000_. Both values can be modified for a specific
1240 
setup and the address space may overlap or can be completely identical. Make sure that both base addresses
1241 
are _aligned_ to a 4-byte boundary.
1242 
 
1243 
[NOTE]
1244 
The base address of the internal bootloader (at _0xFFFF0000_) and the internal IO region (at _0xFFFFFE00_) for
1245 
peripheral devices are also defined in the package and are fixed. These address regions cannot not be used for other
1246 65 zero_gravi 
applications - even if the bootloader or all IO devices are not implemented - without modifying the core's
1247 61 zero_gravi 
hardware sources.
1248 
 
1249 
 
1250 
:sectnums:
1251 
==== Memory Configuration
1252 60 zero_gravi 
 
1253 61 zero_gravi 
The NEORV32 Processor was designed to provide maximum flexibility for the memory configuration.
1254 
The processor can populate the _instruction address space_ and/or the _data address space_ with **internal memories**
1255 
for instructions (IMEM) and data (DMEM). Processor **external memories** can be used as an _alternative_ or even _in combination_ with
1256 
the internal ones. The figure below show some exemplary memory configurations.
1257 60 zero_gravi 
 
1258 61 zero_gravi 
.Exemplary memory configurations
1259 
image::neorv32_memory_configurations.png[800]
1260 60 zero_gravi 
 
1261 61 zero_gravi 
:sectnums!:
1262 
===== Internal Memories
1263 
 
1264 
The processor-internal memories (<<_instruction_memory_imem>> and <<_data_memory_dmem>>) are enabled (=implemented)
1265 
via the <<_mem_int_imem_en>> and <<_mem_int_dmem_en>> generics. Their sizes are configures via the according
1266 
<<_mem_int_imem_size>> and <<_mem_int_dmem_size>> generics.
1267 
 
1268 60 zero_gravi 
If the processor-internal IMEM is implemented, it is located right at the base address of the instruction
1269 
address space (default `ispace_base_c` = _0x00000000_). Vice versa, the processor-internal data memory is
1270 
located right at the beginning of the data address space (default `dspace_base_c` = _0x80000000_) when
1271 
implemented.
1272 
 
1273 61 zero_gravi 
[TIP]
1274 
The default processor setup uses only _internal_ memories.
1275 60 zero_gravi 
 
1276 61 zero_gravi 
[NOTE]
1277 
If the IMEM (internal or external) is less than the (default) maximum size (2GB), there is
1278 
a "dead address space" between it and the DMEM. This provides an additional safety feature
1279 
since data corrupting scenarios like stack overflow cannot directly corrupt the content of the IMEM:
1280 
any access to the "dead address space" in between will raise an exception that can be caught
1281 
by the runtime environment.
1282 60 zero_gravi 
 
1283 61 zero_gravi 
:sectnums!:
1284 
===== External Memories
1285 
 
1286 
If external memories (or further IP modules) shall be connected via the _processor's external bus interface_,
1287 
the interface has to be enabled via <<_mem_ext_en>> generic (=_true_). More information regarding this interface can be
1288 
found in section <<_processor_external_memory_interface_wishbone_axi4_lite>>.
1289 
 
1290 
Any CPU access (data or instructions), which does not fulfill _at least one_ of the following conditions, is forwarded
1291 
via the processor's bus interface to external components:
1292 
 
1293 60 zero_gravi 
* access to the processor-internal IMEM and processor-internal IMEM is implemented
1294 
* access to the processor-internal DMEM and processor-internal DMEM is implemented
1295 70 zero_gravi 
* access to the bootloader ROM and beyond -> addresses >= _BOOTROM_BASE_ (default 0xFFFF0000) will never be forwarded to the external memory interface
1296 60 zero_gravi 
 
1297 70 zero_gravi 
[NOTE]
1298 
If the Execute In Place module (XIP) is implemented accesses map to this module are not forwarded to the
1299 
external memory interface. See section <<_execute_in_place_module_xip>> for more information.
1300 
 
1301 61 zero_gravi 
If no (or not all) processor-internal memories are implemented, the according base addresses are mapped to external memories.
1302 
For example, if the processor-internal IMEM is not implemented (<<_mem_int_imem_en>> = _false_), the processor will forward
1303 
any access to the instruction address space (starting at `ispace_base_c`) via the external bus interface to the external
1304 
memory system.
1305 60 zero_gravi 
 
1306 61 zero_gravi 
[NOTE]
1307 
If the external interface is deactivated, any access exceeding the internal memory address space (instruction, data, bootloader) or
1308 
the internal peripheral address space will trigger a bus access fault exception.
1309 60 zero_gravi 
 
1310 
 
1311 61 zero_gravi 
:sectnums:
1312 
==== Boot Configuration
1313 
 
1314 
Due to the flexible memory configuration concept, the NEORV32 Processor provides several different boot concepts.
1315 
The figure below shows the exemplary concepts for the two most common boot scenarios.
1316 
 
1317 
.NEORV32 boot configurations
1318 
image::neorv32_boot_configurations.png[800]
1319 
 
1320 
[NOTE]
1321 
The configuration of internal or external data memory (DMEM; <<_mem_int_dmem_en>> = _true_ / _false_) is not further
1322 
relevant for the boot configuration itself. Hence, it is not further illustrated here.
1323 
 
1324 
There are two general boot scenarios: _Indirect Boot_ (1a and 1b) and _Direct Boot_ (2a and 2b) configured via the
1325 
<<_int_bootloader_en>> generic  If this generic is set **true** the _indirect_ boot scenario is used. This is also the
1326 
default boot configuration of the processor. If <<_int_bootloader_en>> is set **false** the _direct_ boot scenario is used.
1327 
 
1328 
[NOTE]
1329 
Please note that the provided boot scenarios are just exemplary setups that (should) fit most common requirements.
1330 
Much more sophisticated boot scenarios are possible by combining internal and external memories. For example, the default
1331 
internal bootloader could be used as first-level bootloader that loads (from extern SPI flash) a second-level bootloader
1332 
that is placed and execute in internal IMEM. This second-level bootloader could then fetch the actual application and
1333 
store it to external _data_ memory and transfers CPU control to that.
1334 
 
1335 
:sectnums!:
1336 
===== Indirect Boot
1337 
 
1338 68 zero_gravi 
The _indirect_ boot scenarios **1a** and **1b** use the processor-internal <<_bootloader>>. This boot setup is enabled
1339 
by setting the <<_int_bootloader_en>> generic to _true_, which will implement the processor-internal <<_bootloader_rom_bootrom>>.
1340 61 zero_gravi 
This read-only memory is pre-initialized during synthesis with the default bootloader firmware.
1341 68 zero_gravi 
The bootloader provides several options to upload an executable (via UART or from external SPI flash) and copies it to
1342 
the beginning of the _instruction address space_ so the CPU can execute it.
1343 61 zero_gravi 
 
1344 68 zero_gravi 
Boot scenario **1a** uses the processor-internal IMEM
1345 61 zero_gravi 
(<<_mem_int_imem_en>> = _true_). This scenario implements the internal <<_instruction_memory_imem>> as non-initialized
1346 68 zero_gravi 
RAM so the bootloader can copy the actual executable to it.
1347 61 zero_gravi 
 
1348 
Boot scenario **1b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_) that is connected via the processor's
1349 
bus interface. In this scenario the internal <<_instruction_memory_imem>> is not implemented at all and the bootloader will
1350 68 zero_gravi 
copy the executable to the processor-external memory. Hence, the external memory has to be implemented as RAM.
1351 61 zero_gravi 
 
1352 
:sectnums!:
1353 
===== Direct Boot
1354 
 
1355 68 zero_gravi 
The _direct_ boot scenarios **2a** and **2b** do not use the processor-internal bootloader since the <<_int_bootloader_en>>
1356 61 zero_gravi 
generic is set _false_. In this configuration the <<_bootloader_rom_bootrom>> is not implemented at all and the CPU will
1357 68 zero_gravi 
directly begin executing code from the beginning of the instruction address space after reset. An application-specific
1358 
"pre-initialization" mechanism is required in order to provide an executable _in_ memory.
1359 61 zero_gravi 
 
1360 
Boot scenario **2a** uses the processor-internal IMEM (<<_mem_int_imem_en>> = _true_) that is implemented as _read-only memory_
1361 68 zero_gravi 
in this scenario. It is pre-initialized (by the bitstream) with the actual application executable during synthesis.
1362 61 zero_gravi 
 
1363 
In contrast, boot scenario **2b** uses a processor-external IMEM (<<_mem_int_imem_en>> = _false_). In this scenario the
1364 68 zero_gravi 
system designer is responsible for providing an initialized external memory that contains the actual application to be executed.
1365 
If the external is not already initialized after reset, a simple ROM containing a "polling loop" can be implemented that is
1366 
exited as soon as the application logic has finished initializing the memory with the acutal application code.
1367 61 zero_gravi 
 
1368 
 
1369 
 
1370 60 zero_gravi 
<<<
1371 
// ####################################################################################################################
1372 
:sectnums:
1373 
=== Processor-Internal Modules
1374 
 
1375 
Basically, the processor is a SoC consisting of the NEORV32 CPU, peripheral/IO devices, embedded
1376 
memories, an external memory interface and a bus infrastructure to interconnect all units. Additionally, the
1377 
system implements an internal reset generator and a global clock generator/divider.
1378 
 
1379 
**Internal Reset Generator**
1380 
 
1381 65 zero_gravi 
Most processor-internal modules - except for the CPU and the watchdog timer - do not have a dedicated
1382 60 zero_gravi 
reset signal. However, all devices can be reset by software by clearing the corresponding unit's control
1383 
register. The automatically included application start-up code (`crt0.S`) will perform a software-reset of all
1384 
modules to ensure a clean system reset state.
1385 
 
1386 
The hardware reset signal of the processor can either be
1387 
triggered via the external reset pin (`rstn_i`, low-active) or by the internal watchdog timer (if implemented).
1388 
Before the external reset signal is applied to the system, it is extended to have a minimal duration of eight
1389 
clock cycles.
1390 
 
1391 
**Internal Clock Divider**
1392 
 
1393 
An internal clock divider generates 8 clock signals derived from the processor's main clock input `clk_i`.
1394 
These derived clock signals are not actual _clock signals_. Instead, they are derived from a simple counter and
1395 
are used as "clock enable" signal by the different processor modules. Thus, the whole design operates using
1396 
only the main clock signal (single clock domain). Some of the processor peripherals like the Watchdog or the
1397 
UARTs can select one of the derived clock enabled signals for their internal operation. If none of the
1398 
connected modules require a clock signal from the divider, it is automatically deactivated to reduce dynamic
1399 
power.
1400 
 
1401 
The peripheral devices, which feature a time-based configuration, provide a three-bit prescaler select in their
1402 
according control register to select one out of the eight available clocks. The mapping of the prescaler select
1403 
bits to the actually obtained clock are shown in the table below. Here, f represents the processor main clock
1404 
from the top entity's `clk_i` signal.
1405 
 
1406 
[cols="<3,^1,^1,^1,^1,^1,^1,^1,^1"]
1407 
[grid="rows"]
1408 
|=======================
1409 
| Prescaler bits:  | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
1410 
| Resulting clock: | _f/2_   | _f/4_   | _f/8_   | _f/64_  | _f/128_ | _f/1024_| _f/2048_| _f/4096_
1411 
|=======================
1412 
 
1413 
**Peripheral / IO Devices**
1414 
 
1415 
The processor-internal peripheral/IO devices are located at the end of the 32-bit address space at base
1416 
address _0xFFFFFE00_. A region of 512 bytes is reserved for this devices. Hence, all peripheral/IO devices are
1417 
accessed using a memory-mapped scheme. A special linker script as well as the NEORV32 core software
1418 
library abstract the specific memory layout for the user.
1419 
 
1420 73 zero_gravi 
.Address Space Mapping
1421 60 zero_gravi 
[IMPORTANT]
1422 64 zero_gravi 
The base address of each component/module has to be aligned to the
1423 
total size of the module's occupied address space! The occupied address space
1424 
has to be a power of two (minimum 4 bytes)! Address spaces must not overlap!
1425 
 
1426 73 zero_gravi 
.Full-Word Write Accesses Only
1427 64 zero_gravi 
[IMPORTANT]
1428 73 zero_gravi 
All peripheral/IO devices can only be written in full-word mode (i.e. 32-bit). Byte or half-word
1429 60 zero_gravi 
(8/16-bit) writes will trigger a store access fault exception. Read accesses are not size constrained.
1430 
Processor-internal memories as well as modules connected to the external memory interface can still
1431 
be written with a byte-wide granularity.
1432 
 
1433 73 zero_gravi 
.Unimplemented Modules
1434 70 zero_gravi 
[NOTE]
1435 73 zero_gravi 
When accessing an IO device that hast not been implemented (via the according generic), a
1436 
load/store access fault exception is triggered.
1437 
 
1438 
.Hardware Reset
1439 
[NOTE]
1440 70 zero_gravi 
Most of the IO devices do not have a hardware reset. Instead, the devices are reset via software by
1441 
writing zero to the unit's control register. A general software-based reset of all devices is done by the
1442 
application start-up code `crt0.S`.
1443 
 
1444 60 zero_gravi 
[TIP]
1445 
You should use the provided core software library to interact with the peripheral devices. This
1446 
prevents incompatibilities with future versions, since the hardware driver functions handle all the
1447 
register and register bit accesses.
1448 
 
1449 
[TIP]
1450 69 zero_gravi 
A CMSIS-SVD-compatible **System View Description (SVD)** file including all peripherals is available in `sw/svd`.
1451 
 
1452 64 zero_gravi 
**Interrupts of Processor-Internal Modules**
1453 
 
1454 
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
1455 
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
1456 66 zero_gravi 
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
1457 64 zero_gravi 
 
1458 60 zero_gravi 
**Nomenclature for the Peripheral / IO Devices Listing**
1459 
 
1460 
Each peripheral device chapter features a register map showing accessible control and data registers of the
1461 64 zero_gravi 
according device including the implemented control and status bits. C-language code can directly interact with these
1462 
registers via pre-defined `struct`. Each IO/peripheral module provides a unique `struct`. All accessible
1463 
interface registers of this module are defined as members of this `struct`. The pre-defined `struct` are defined int the
1464 
main processor core library include file `sw/lib/include/neorv32.h`.
1465 60 zero_gravi 
 
1466 64 zero_gravi 
The naming scheme of these low-level hardware access structs is `NEORV32_.`.
1467 
 
1468 
.Low-level hardware access example in C using the pre-defined `struct`
1469 
[source,c]
1470 
----
1471 
// Read from SYSINFO "CLK" register
1472 
uint32_t temp = NEORV32_SYSINFO.CLK;
1473 
----
1474 
 
1475 
The registers and/or register bits, which can be accessed directly using plain C-code, are marked with a "[C]".
1476 60 zero_gravi 
Not all registers or register bits can be arbitrarily read/written. The following read/write access types are
1477 
available:
1478 
 
1479 
* `r/w` registers / bits can be read and written
1480 
* `r/-` registers / bits are read-only; any write access to them has no effect
1481 
* `-/w` these registers / bits are write-only; they auto-clear in the next cycle and are always read as zero
1482 
 
1483 70 zero_gravi 
[NOTE]
1484 60 zero_gravi 
Bits / registers that are not listed in the register map tables are not (yet) implemented. These registers
1485 
/ bits are always read as zero. A write access to them has no effect, but user programs should only
1486 
write zero to them to keep compatible with future extension.
1487 
 
1488 70 zero_gravi 
[NOTE]
1489 60 zero_gravi 
When writing to read-only registers, the access is nevertheless acknowledged, but no actual data is
1490 
written. When reading data from a write-only register the result is undefined.
1491 
 
1492 
 
1493 
include::soc_imem.adoc[]
1494 
 
1495 
include::soc_dmem.adoc[]
1496 
 
1497 
include::soc_bootrom.adoc[]
1498 
 
1499 
include::soc_icache.adoc[]
1500 
 
1501 
include::soc_wishbone.adoc[]
1502 
 
1503 66 zero_gravi 
include::soc_buskeeper.adoc[]
1504 
 
1505 61 zero_gravi 
include::soc_slink.adoc[]
1506 
 
1507 60 zero_gravi 
include::soc_gpio.adoc[]
1508 
 
1509 
include::soc_wdt.adoc[]
1510 
 
1511 
include::soc_mtime.adoc[]
1512 
 
1513 
include::soc_uart.adoc[]
1514 
 
1515 
include::soc_spi.adoc[]
1516 
 
1517 
include::soc_twi.adoc[]
1518 
 
1519 
include::soc_pwm.adoc[]
1520 
 
1521 
include::soc_trng.adoc[]
1522 
 
1523 
include::soc_cfs.adoc[]
1524 
 
1525 
include::soc_neoled.adoc[]
1526 
 
1527 61 zero_gravi 
include::soc_xirq.adoc[]
1528 
 
1529 67 zero_gravi 
include::soc_gptmr.adoc[]
1530 
 
1531 70 zero_gravi 
include::soc_xip.adoc[]
1532 
 
1533 60 zero_gravi 
include::soc_sysinfo.adoc[]

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