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:sectnums:
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==== Processor-Internal Instruction Cache (iCACHE)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_icache.vhd |
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | none |
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| Configuration generics: | _ICACHE_EN_ | implement processor-internal instruction cache when _true_
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| | _ICACHE_NUM_BLOCKS_ | number of cache blocks (pages/lines)
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| | _ICACHE_BLOCK_SIZE_ | size of a cache block in bytes
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| | _ICACHE_ASSOCIATIVITY_ | associativity / number of sets
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| CPU interrupts: | none |
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|=======================
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[NOTE]
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The default `neorv32_icache.vhd` HDL source file provides a _generic_ memory design that infers embedded
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memory. You might need to replace/modify the source file in order to use platform-specific features
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(like advanced memory resources) or to improve technology mapping and/or timing.
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The processor features an optional cache for instructions to compensate memories with high latency. The
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cache is directly connected to the CPU's instruction fetch interface and provides a full-transparent buffering
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of instruction fetch accesses to the entire 4GB address space.
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[IMPORTANT]
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The instruction cache is intended to accelerate instruction fetch via the external memory interface.
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Since all processor-internal memories provide an access latency of one cycle (by default), caching
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internal memories does not bring any performance gain. However, it _might_ reduce traffic on the
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processor-internal bus.
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The cache is implemented if the _ICACHE_EN_ generic is true. The size of the cache memory is defined via
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_ICACHE_BLOCK_SIZE_ (the size of a single cache block/page/line in bytes; has to be a power of two and >=
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4 bytes), _ICACHE_NUM_BLOCKS_ (the total amount of cache blocks; has to be a power of two and >= 1) and
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the actual cache associativity _ICACHE_ASSOCIATIVITY_ (number of sets; 1 = direct-mapped, 2 = 2-way set-associative,
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has to be a power of two and >= 1).
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If the cache associativity (_ICACHE_ASSOCIATIVITY_) is > 1 the LRU replacement policy (least recently
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used) is used.
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[TIP]
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Keep the features of the targeted FPGA's memory resources (block RAM) in mind when configuring
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the cache size/layout to maximize and optimize resource utilization.
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By executing the `ifence.i` instruction (`Zifencei` CPU extension) the cache is cleared and a reload from
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main memory is forced. Among other things, this allows to implement self-modifying code.
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**Bus Access Fault Handling**
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The cache always loads a complete cache block (_ICACHE_BLOCK_SIZE_ bytes) aligned to the size of a cache
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block if a miss is detected. If any of the accessed addresses within a single block do not successfully
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acknowledge (i.e. issuing an error signal or timing out) the whole cache block is invalidate and any access to
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an address within this cache block will also raise an instruction fetch bus error fault exception.
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