| 1 |
60 |
zero_gravi |
<<<
|
| 2 |
|
|
:sectnums:
|
| 3 |
|
|
==== System Configuration Information Memory (SYSINFO)
|
| 4 |
|
|
|
| 5 |
|
|
[cols="<3,<3,<4"]
|
| 6 |
|
|
[frame="topbot",grid="none"]
|
| 7 |
|
|
|=======================
|
| 8 |
|
|
| Hardware source file(s): | neorv32_sysinfo.vhd |
|
| 9 |
61 |
zero_gravi |
| Software driver file(s): | neorv32.h |
|
| 10 |
60 |
zero_gravi |
| Top entity port: | none |
|
| 11 |
|
|
| Configuration generics: | * | most of the top's configuration generics
|
| 12 |
|
|
| CPU interrupts: | none |
|
| 13 |
|
|
|=======================
|
| 14 |
|
|
|
| 15 |
|
|
**Theory of Operation**
|
| 16 |
|
|
|
| 17 |
|
|
The SYSINFO allows the application software to determine the setting of most of the processor's top entity
|
| 18 |
|
|
generics that are related to processor/SoC configuration. All registers of this unit are read-only.
|
| 19 |
|
|
|
| 20 |
|
|
This device is always implemented – regardless of the actual hardware configuration. The bootloader as well
|
| 21 |
|
|
as the NEORV32 software runtime environment require information from this device (like memory layout
|
| 22 |
|
|
and default clock speed) for correct operation.
|
| 23 |
|
|
|
| 24 |
|
|
.SYSINFO register map
|
| 25 |
|
|
[cols="<2,<4,<7"]
|
| 26 |
|
|
[options="header",grid="all"]
|
| 27 |
|
|
|=======================
|
| 28 |
|
|
| Address | Name [C] | Function
|
| 29 |
|
|
| `0xffffffe0` | _SYSINFO_CLK_ | clock speed in Hz (via top's _CLOCK_FREQUENCY_ generic)
|
| 30 |
|
|
| `0xffffffe4` | _SYSINFO_USER_CODE_ | custom user code, assigned via top's _USER_CODE_ generic
|
| 31 |
|
|
| `0xffffffe8` | _SYSINFO_FEATURES_ | specific hardware configuration (see next table)
|
| 32 |
|
|
| `0xffffffec` | _SYSINFO_CACHE_ | cache configuration information (see next table)
|
| 33 |
|
|
| `0xfffffff0` | _SYSINFO_ISPACE_BASE_ | instruction address space base (defined via `ispace_base_c` constant in the `neorv32_package.vhd` file)
|
| 34 |
|
|
| `0xfffffff4` | _SYSINFO_IMEM_SIZE_ | internal IMEM size in bytes (defined via top's _MEM_INT_IMEM_SIZE_ generic)
|
| 35 |
|
|
| `0xfffffff8` | _SYSINFO_DSPACE_BASE_ | data address space base (defined via `sdspace_base_c` constant in the `neorv32_package.vhd` file)
|
| 36 |
|
|
| `0xfffffffc` | _SYSINFO_DMEM_SIZE_ | internal DMEM size in bytes (defined via top's _MEM_INT_DMEM_SIZE_ generic)
|
| 37 |
|
|
|=======================
|
| 38 |
|
|
|
| 39 |
|
|
|
| 40 |
|
|
._SYSINFO_FEATURES_ bits
|
| 41 |
|
|
[cols="^1,<10,<11"]
|
| 42 |
|
|
[options="header",grid="all"]
|
| 43 |
|
|
|=======================
|
| 44 |
|
|
| Bit | Name [C] | Function
|
| 45 |
61 |
zero_gravi |
| `0` | _SYSINFO_FEATURES_BOOTLOADER_ | set if the processor-internal bootloader is implemented (via top's _INT_BOOTLOADER_EN_ generic)
|
| 46 |
60 |
zero_gravi |
| `1` | _SYSINFO_FEATURES_MEM_EXT_ | set if the external Wishbone bus interface is implemented (via top's _MEM_EXT_EN_ generic)
|
| 47 |
|
|
| `2` | _SYSINFO_FEATURES_MEM_INT_IMEM_ | set if the processor-internal DMEM implemented (via top's _MEM_INT_DMEM_EN_ generic)
|
| 48 |
61 |
zero_gravi |
| `3` | _SYSINFO_FEATURES_MEM_INT_DMEM_ | set if the processor-internal IMEM is implemented (via top's _MEM_INT_IMEM_EN_ generic)
|
| 49 |
|
|
| `4` | _SYSINFO_FEATURES_MEM_EXT_ENDIAN_ | set if external bus interface uses BIG-endian byte-order (via package's `wb_big_endian_c` constant)
|
| 50 |
|
|
| `5` | _SYSINFO_FEATURES_ICACHE_ | set if processor-internal instruction cache is implemented (via _ICACHE_EN_ generic)
|
| 51 |
60 |
zero_gravi |
| `14` | _SYSINFO_FEATURES_HW_RESET_ | set if on-chip debugger implemented (via _ON_CHIP_DEBUGGER_EN_ generic)
|
| 52 |
|
|
| `15` | _SYSINFO_FEATURES_HW_RST_ | set if a dedicated hardware reset of all core registers is implemented (via package's _dedicated_reset_c_ constant)
|
| 53 |
|
|
| `15` | _SYSINFO_FEATURES_HW_RST_ | set if a dedicated hardware reset of all core registers is implemented (via package's _dedicated_reset_c_ constant)
|
| 54 |
|
|
| `16` | _SYSINFO_FEATURES_IO_GPIO_ | set if the GPIO is implemented (via top's _IO_GPIO_EN_ generic)
|
| 55 |
|
|
| `17` | _SYSINFO_FEATURES_IO_MTIME_ | set if the MTIME is implemented (via top's _IO_MTIME_EN_ generic)
|
| 56 |
|
|
| `18` | _SYSINFO_FEATURES_IO_UART0_ | set if the primary UART0 is implemented (via top's _IO_UART0_EN_ generic)
|
| 57 |
|
|
| `19` | _SYSINFO_FEATURES_IO_SPI_ | set if the SPI is implemented (via top's _IO_SPI_EN_ generic)
|
| 58 |
|
|
| `20` | _SYSINFO_FEATURES_IO_TWI_ | set if the TWI is implemented (via top's _IO_TWI_EN_ generic)
|
| 59 |
|
|
| `21` | _SYSINFO_FEATURES_IO_PWM_ | set if the PWM is implemented (via top's _IO_PWM_EN_ generic)
|
| 60 |
|
|
| `22` | _SYSINFO_FEATURES_IO_WDT_ | set if the WDT is implemented (via top's _IO_WDT_EN_ generic)
|
| 61 |
|
|
| `23` | _SYSINFO_FEATURES_IO_CFS_ | set if the custom functions subsystem is implemented (via top's _IO_CFS_EN_ generic)
|
| 62 |
|
|
| `24` | _SYSINFO_FEATURES_IO_TRNG_ | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic)
|
| 63 |
61 |
zero_gravi |
| `25` | _SYSINFO_FEATURES_IO_SLINK_ | set if the SLINK is implemented (via top's _SLINK_NUM_TX_ / _SLINK_NUM_RX_ generics)
|
| 64 |
60 |
zero_gravi |
| `26` | _SYSINFO_FEATURES_IO_UART1_ | set if the secondary UART1 is implemented (via top's _IO_UART1_EN_ generic)
|
| 65 |
|
|
| `27` | _SYSINFO_FEATURES_IO_NEOLED_ | set if the NEOLED is implemented (via top's _IO_NEOLED_EN_ generic)
|
| 66 |
|
|
|=======================
|
