OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_sysinfo.adoc] - Blame information for rev 72

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 60 zero_gravi
<<<
2
:sectnums:
3
==== System Configuration Information Memory (SYSINFO)
4
 
5
[cols="<3,<3,<4"]
6
[frame="topbot",grid="none"]
7
|=======================
8
| Hardware source file(s): | neorv32_sysinfo.vhd |
9 61 zero_gravi
| Software driver file(s): | neorv32.h |
10 60 zero_gravi
| Top entity port:         | none |
11
| Configuration generics:  | * | most of the top's configuration generics
12
| CPU interrupts:          | none |
13
|=======================
14
 
15
**Theory of Operation**
16
 
17
The SYSINFO allows the application software to determine the setting of most of the processor's top entity
18
generics that are related to processor/SoC configuration. All registers of this unit are read-only.
19
 
20 65 zero_gravi
This device is always implemented - regardless of the actual hardware configuration. The bootloader as well
21 60 zero_gravi
as the NEORV32 software runtime environment require information from this device (like memory layout
22
and default clock speed) for correct operation.
23
 
24 70 zero_gravi
[NOTE]
25
Any write access to the SYSINFO module will raise a store bus error exception. The <<_internal_bus_monitor_buskeeper>>
26
will signal a "DEVICE ERROR" in this case.
27
 
28
 
29 64 zero_gravi
.SYSINFO register map (`struct NEORV32_SYSINFO`)
30 60 zero_gravi
[cols="<2,<4,<7"]
31
[options="header",grid="all"]
32
|=======================
33
| Address | Name [C] | Function
34 64 zero_gravi
| `0xffffffe0` | `NEORV32_SYSINFO.CLK`         | clock speed in Hz (via top's <<_clock_frequency>> generic)
35 72 zero_gravi
| `0xffffffe4` | -                             | _reserved_, read as zero
36 64 zero_gravi
| `0xffffffe8` | `NEORV32_SYSINFO.SOC`         | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
37
| `0xffffffec` | `NEORV32_SYSINFO.CACHE`       | cache configuration information (see <<_sysinfo_cache_configuration>>)
38
| `0xfffffff0` | `NEORV32_SYSINFO.ISPACE_BASE` | instruction address space base (via package's `ispace_base_c` constant)
39
| `0xfffffff4` | `NEORV32_SYSINFO.IMEM_SIZE`   | internal IMEM size in bytes (via top's <<_mem_int_imem_size>> generic)
40
| `0xfffffff8` | `NEORV32_SYSINFO.DSPACE_BASE` | data address space base (via package's `sdspace_base_c` constant)
41
| `0xfffffffc` | `NEORV32_SYSINFO.DMEM_SIZE`   | internal DMEM size in bytes (via top's <<_mem_int_dmem_size>> generic)
42 60 zero_gravi
|=======================
43
 
44
 
45 63 zero_gravi
===== SYSINFO - SoC Configuration
46
 
47 64 zero_gravi
._SYSINFO_SOC_ bits
48 60 zero_gravi
[cols="^1,<10,<11"]
49
[options="header",grid="all"]
50
|=======================
51
| Bit | Name [C] | Function
52 64 zero_gravi
| `0`  | _SYSINFO_SOC_BOOTLOADER_       | set if the processor-internal bootloader is implemented (via top's <<_int_bootloader_en>> generic)
53
| `1`  | _SYSINFO_SOC_MEM_EXT_          | set if the external Wishbone bus interface is implemented (via top's <<_mem_ext_en>> generic)
54
| `2`  | _SYSINFO_SOC_MEM_INT_IMEM_     | set if the processor-internal DMEM implemented (via top's <<_mem_int_dmem_en>> generic)
55
| `3`  | _SYSINFO_SOC_MEM_INT_DMEM_     | set if the processor-internal IMEM is implemented (via top's <<_mem_int_imem_en>> generic)
56
| `4`  | _SYSINFO_SOC_MEM_EXT_ENDIAN_   | set if external bus interface uses BIG-endian byte-order (via top's <<_mem_ext_big_endian>> generic)
57
| `5`  | _SYSINFO_SOC_ICACHE_           | set if processor-internal instruction cache is implemented (via top's <<_icache_en>> generic)
58 69 zero_gravi
| `13` | _SYSINFO_SOC_IS_SIM_           | set if processor is being **simulated** (⚠️ not guaranteed)
59 64 zero_gravi
| `14` | _SYSINFO_SOC_OCD_              | set if on-chip debugger implemented (via top's <<_on_chip_debugger_en>> generic)
60
| `15` | _SYSINFO_SOC_HW_RESET_         | set if a dedicated hardware reset of all core registers is implemented (via package's `dedicated_reset_c` constant)
61
| `16` | _SYSINFO_SOC_IO_GPIO_          | set if the GPIO is implemented (via top's <<_io_gpio_en>> generic)
62
| `17` | _SYSINFO_SOC_IO_MTIME_         | set if the MTIME is implemented (via top's <<_io_mtime_en>> generic)
63
| `18` | _SYSINFO_SOC_IO_UART0_         | set if the primary UART0 is implemented (via top's <<_io_uart0_en>> generic)
64
| `19` | _SYSINFO_SOC_IO_SPI_           | set if the SPI is implemented (via top's <<_io_spi_en>> generic)
65
| `20` | _SYSINFO_SOC_IO_TWI_           | set if the TWI is implemented (via top's <<_io_twi_en>> generic)
66 70 zero_gravi
| `21` | _SYSINFO_SOC_IO_PWM_           | set if the PWM is implemented (via top's <<_io_pwm_num_ch>> generic)
67 64 zero_gravi
| `22` | _SYSINFO_SOC_IO_WDT_           | set if the WDT is implemented (via top's <<_io_wdt_en>> generic)
68
| `23` | _SYSINFO_SOC_IO_CFS_           | set if the custom functions subsystem is implemented (via top's <<_io_cfs_en>> generic)
69
| `24` | _SYSINFO_SOC_IO_TRNG_          | set if the TRNG is implemented (via top's _IO_TRNG_EN_ generic)
70
| `25` | _SYSINFO_SOC_IO_SLINK_         | set if the SLINK is implemented (via top's <<_slink_num_tx>> and/or <<_slink_num_rx>> generics)
71
| `26` | _SYSINFO_SOC_IO_UART1_         | set if the secondary UART1 is implemented (via top's <<_io_uart1_en>> generic)
72
| `27` | _SYSINFO_SOC_IO_NEOLED_        | set if the NEOLED is implemented (via top's <<_io_neoled_en>> generic)
73 70 zero_gravi
| `28` | _SYSINFO_SOC_IO_XIRQ_          | set if the XIRQ is implemented (via top's <<_xirq_num_ch>> generic)
74
| `29` | _SYSINFO_SOC_IO_GPTMR_         | set if the GPTMR is implemented (via top's <<_io_gptmr_en>> generic)
75
| `30` | _SYSINFO_SOC_IO_XIP_           | set if the XIP module is implemented (via top's <<_io_xip_en>> generic)
76 60 zero_gravi
|=======================
77 63 zero_gravi
 
78
 
79
===== SYSINFO - Cache Configuration
80
 
81
[NOTE]
82
Bit fields in this register are set to all-zero if the according cache is not implemented.
83
 
84
._SYSINFO_CACHE_ bits
85
[cols="^1,<10,<11"]
86
[options="header",grid="all"]
87
|=======================
88
| Bit      | Name [C] | Function
89
| `3:0`    | _SYSINFO_CACHE_IC_BLOCK_SIZE_3_ : _SYSINFO_CACHE_IC_BLOCK_SIZE_0_       | _log2_(i-cache block size in bytes), via top's <<_icache_block_size>> generic
90
| `7:4`    | _SYSINFO_CACHE_IC_NUM_BLOCKS_3_ : _SYSINFO_CACHE_IC_NUM_BLOCKS_0_       | _log2_(i-cache number of cache blocks), via top's <<_icache_num_blocks>> generic
91
| `11:9`   | _SYSINFO_CACHE_IC_ASSOCIATIVITY_3_ : _SYSINFO_CACHE_IC_ASSOCIATIVITY_0_ | _log2_(i-cache associativity), via top's <<_icache_associativity>> generic
92
| `15:12`  | _SYSINFO_CACHE_IC_REPLACEMENT_3_ : _SYSINFO_CACHE_IC_REPLACEMENT_0_     | i-cache replacement policy (`0001` = LRU if associativity > 0)
93
| `32:16`  | -                                                                       | zero, reserved for d-cache
94
|=======================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.